Now that clock control drivers are enabled based on devicetree we
need to remove any cases of them getting enabled by Kconfig.defconfig*
files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a sensor and not
respect the devicetree state of the clock control. Additionally we
can get problems with prj.conf/defconfig getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
This PR adds a KConfig option that allows moving
all .noinit content related to wifi a net stack into external
ram. This free dram space to application.
Linker script files are also modified so that the content
are mapped into external ram.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Base address for PRCI is not used anywhere in the tree for this
platform. Again, if ever used, this needs to come from DT.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
There is no GPIO driver for such platform, and if it existed, all this
information should be provided in Devicetree (as other platform drivers
like UART do).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
- zephyr/toolchain.h is not needed
- gd32vf103.h is not needed (no CMSIS here)
- undefinition not needed, HAL is now patched with a prefix for this
definition.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
SystemInit is declared in gd32vf103.h. Include it instead of relying on
indirect soc.h includes.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Put ace headers alongside other headers. The contents of ace_v1x-regs.h
will be moved around to new headers being added across all series and
SoCs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of enabling WOVCRO clock based on the SOC, use a configuration
to indicate support, so that each platform can specify if WOVCRO is
supported or not.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
If test for WOVCRO clock fails, code shouldn't just choose WOVCRO clock
as the lowest frequency one, but LPRO instead.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
For intel adsp platforms we have a common multiprocessing.c file and
then another multiprocessing.c for ace and multiprocessing_cavs.c for
cavs. Rename the cavs specific implementation to follow the convention.
There is not need to "cavs" suffix since the file is already inside its
specific directory.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Inside the common directory there were files that are CAVS specific and
are not used by ACE_V1X. Lets create a subdir called cavs inside the
common to put files that are common for only cavs plaftorms.
Note that there are still remaining code that in the common folder that
are using cavs namespace like "cavs_ipc_*" that may need some additional
work.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
We already have riscv_clic.h and riscv_plic.h, no need to have the same
declarations in soc_common.h as well.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Now that PWM drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the PWM.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that SPI drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the SPI.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that serial drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the serial.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that gpio drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the GPIO.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Intel ADSP CAVS is now a proper series with all CAVS SoCs running under
it. This will give us to Intel ADSP series:
- CAVS
- ACE v1.x
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In order to coredump dump the ram memory, it is necessary that we define
in the linker scripts two variable to indicate the start and the end of
the ram area. Adding these variables to ace linker script.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
In order to coredump dump the ram memory, it is necessary that we define
in the linker scripts two variable to indicate the start and the end of
the ram area. Adding these variables to cavs linker script.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
cavs/version.h was never used by Zephyr, it was supposed to be needed by
SoF. This no longer seems to be the case, just removing it.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Now that sensor drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the sensor.
Additionally we can get problems with prj.conf/defconfig
as well getting incorrectly overridden.
Fixes#48198
Signed-off-by: Kumar Gala <galak@kernel.org>
This CL adds a DT node, 'power_leakage_io', which property,
'leak-gpios', contains GPIOs that have leakage current. In oerder to get
better power consumption, npcx power driver will disable the connections
between these io pads and input buffers before entering deep sleep.
Then, restore the connections after ec wakes up.
The users can overwrite this property at board DT file. Here is an
example:
&power_leakage_io {
leak-gpios = <&gpio0 0 0
&gpiob 1 0>;
};
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL configures low-voltage (1.8V) detection via GPIO driver with
GPIO_VOLTAGE_1P8 flag. It also adds support for this flag in
pin_get_config() function.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Cleanup npcx low-voltage (1.8V) detection configuration. It removes
unused soc utilities, macros, and DT node. We will configure this
feature by GPIO driver with GPIO_VOLTAGE_1P8 flag later.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
ITE EC chip it81202 and it81302 both have embedded integrated
pd module (support two usbpd ports), this is different from
standalone TCPC. To prevent cc pins leakage, we disable not
active ITE USBPD port cc modules, then cc pins can be used
as gpio if needed.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Declare clock control in the shim header per SoC and remove ifdeffry
from the driver simplifiying it and making it ready for the next
platform.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Declare those register in the adsp_shim header instead of the code
applying ifdefs that limit the scope to only specific SoCs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move those defines and values back to headers. Kconfig is not a good
place for this, later this should move to DTS.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
using once single header to support multiple socs and product
generations is error prone and not easily maintained.
Over time we have been adding conditional code in headers and extending
structs to support new HW features which becomes a problem.
Goal is to keep platform headers in sync with hardware specification and
allow of introduction of new platforms and hardware features by just
introducing a new SoC with its own set of headers.
This is now just a copy of existing cavs-shim.h with slight changes,
goal is to clean this up long term and sync with hardware datasheets and
align on naming as well.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move headers into the include/ folder per soc and rename fw_defs.h to
adsp_memory to align with SOF.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The driver has be DT_INST based for a while so the Kconfig
symbols CONFIG_UART_PL011_PORT0<n> aren't used. So lets
remove them.
Signed-off-by: Kumar Gala <galak@kernel.org>
MISRA C:2012 Rule 14.4 (The controlling expression of an if statement
and the controlling expression of an iteration-statement shall have
essentially Boolean type.)
Use `do { ... } while (false)' instead of `do { ... } while (0)'.
This commit is a subset of the original commit:
5d02614e34a86b549c7707d3d9f0984bc3a5f22a
Signed-off-by: Simon Hein <SHein@baumer.com>
Uses a macro with a define flag to enable register dumps on the DSP
side. On the python side a simple booling flag.
The default disabled both debug flags and makes the tests
considerably quieter.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Any project with Kconfig option CONFIG_LEGACY_INCLUDE_PATH set to n
couldn't be built because some files were missing zephyr/ prefix in
includes
Re-run the migrate_includes.py script to fix all legacy include paths
Signed-off-by: Tomislav Milkovic <milkovic@byte-lab.com>
Include linker sections header to move z_arm_platform_init to text
section. It is now is placed in the TEXT section.
Signed-off-by: Bernard Lee <bernard.lee@nordicsemi.no>
For SAML21-based parts, the REFCTRL register is locked while the ADC is
enabled. Permit some parts to declare that they need the ADC to be
disabled before modifying REFCTRL.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Implement support for SAMR34 and SAMR35 parts, tested on a SAMR34
Xplained Pro dev board. Confirmed operational peripherals: UART, GPIO,
PWM, ADC.
NOTE: The SAMR34 datasheet lists NVIC line 20 for the ADC's interrupt,
but the SAML21 datasheet gives line 22. It appears that the SAMR34 sheet
is incorrect (the ADC doesn't function with line 20), and as such, I have
also omitted the adjustments for TC4 and AC...
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Implement support for SAML21 parts, tested on a SAML21 Xplained Pro dev
board. Confirmed operational peripherals: UART, GPIO, PWM, ADC.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Some tests was built failed due to cannot find the __imr macro:
Try to fix it by including the linker/section.h in soc.h.
Fixes#47830.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
Clean up unused psl functions in scfg.c, unused DT macros, unused psl DT
nodes and related yaml files. Currently, PSL pad configurations are made
by pinctrl mechanism. Please refer
https://issuetracker.google.com/234861079 for more detail.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
irq_lock() returns an unsigned integer key.
Generated by spatch using semantic patch
scripts/coccinelle/irq_lock.cocci
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
HDA is a common IP used across the entire ADSP line and deserves
a name respecting that alongside similiar IP drivers such as the
ADSP GPDMA driver.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Those belong where other attribute macros are usually defined. They are
not xtensa or ADSP specific and are used across Intel SoCs on all
architectures.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of ifdeffing on SOCs and missing things along the way, maintain
platform definitions that are different among SoCs in one single file
per SoC and use data from that file critical spots.
In this case, we were checking for CAVS25, setting one value where
everything else was set to 0, so new SoC like ACE was getting 0 as well,
although it has the same value as TGL.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Clean up unused pinmux function 'npcx_pinctrl_mux_configure()' and
related 'NPCX_DT_IO_ALT*' macro functions.
Please refer https://issuetracker.google.com/234861079 for more detail.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Adding command queue mode can reduce the time between each byte to
improve the I2C bus clock stretching during I2C transaction.
I2C command queue mode of it8xxx2 can support I2C APIs including:
i2c_write(), i2c_read(), i2c_burst_read.
Test:
1. tests\drivers\i2c\i2c_api --> pass
2. Reading 16 bytes of data through i2c_burst_read() can reduce
0.72ms(2.54ms->1.82ms) compared to the original pio mode when the
frequency is 100KHz.
3. krabby platform can boot normally.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Fix build error if CONFIG_PM and CONFIG_INIT_VIDEO_PLL are enabled.
Added 2 missing semicolons.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Introduce a new RISCV_HAS_CLIC symbol for platforms using CLIC,
reorganize the Kconfigs and make the Nuclei ECLIC depending on the new
symbol.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add static MPU regions for this SoC.
These regions will be initialized as static region during system boot.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
cAVS and ACE gpdma driver have several similarities. This commit merge
this two drivers into a single one for Intel ADSP devices.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
zephyr/soc/xtensa/intel_adsp/ace_v1x/irq.c: In function
'z_soc_irq_is_enabled':
zephyr/soc/xtensa/intel_adsp/ace_v1x/irq.c:47:3: warning: 'return'
with no value, in function returning non-void [-Wreturn-type]
47 | return;
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Move to use DEVICE_DT_GET instead of device_get_binding as
we work on phasing out use of DTS 'label' property.
Signed-off-by: Kumar Gala <galak@kernel.org>
Move to use DEVICE_DT_GET instead of device_get_binding as
we work on phasing out use of DTS 'label' property.
Signed-off-by: Kumar Gala <galak@kernel.org>
Change APL_GPIO_DEV_* defines to be DT_NODELABELs instead of
"label" strings. This lets us change users of these defines to
use DEVICE_DT_GET.
We update samples/board/up_squared/gpio_counter to use DEVICE_DT_GET
as part of this change.
Signed-off-by: Kumar Gala <galak@kernel.org>
Uses the dt_compat_enabled Kconfig preprocessor to set defaults
for each HDA driver.
Each direction is uniquely selectable which can be useful when building
with SOF where only some directions may wish to be enabled at any given
time.
By default, given the device tree (intel_cavs.dtsi) only the host
directions are enabled but an overlay may adjust that as needed.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
This adds a new stm32f412Rx in the list of stm32F4 devices.
The module stm32cube/stm32f4/soc/stm32f412rx.h exists
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Change some behaviors when --log-only is passed in order to add support
for DSP power state: D3. This makes it possible to keep `cavstool
--log-only` running permanently in the "real-world" use case where the
Linux kernel loads the firmware and powers down audio when not in use.
More specifically:
- Do not disable D3 when using --log-only.
- Wait forever for the FW at boot time.
- Check live status when an invalid IPC is received and wait forever if
not alive.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Add a new timeout_s parameter that can also be 'None' = infinite.
No functional change. Required to add future support for DSP power
state: D3
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
This CL introduces how to configure PSL (Power Switch Logic) pads
properties such as input detection mode/polarity, pin-muxing and so
on via pinctrl mechanism. It includes:
1. Add two pinctrl properties and their enums for PSL input
detection configuration.
psl-in-mode:
- "level"
- "mode"
psl-in-pole:
- "low-falling"
- "high-rising"
2. Add macro functions to get PSL input detection and pin-muxing
configurations from 'pinmux', 'psl-offset' abd 'psl-polarity'
properties.
Here is an example to configure PSL_IN2 as the PSL detection input and
its mode and polarity.
/* A falling edge detection type for PSL_IN2 */
&psl_in2_gp00 {
psl-in-mode = "edge";
psl-in-pol = "low-falling";
};
A device will be introduced later which uses this pinctrl node to
configure PSL input detection settings and how to turn off VCC1 power
rail by PSL_OUT.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
For vectored interrupts use the generated IRQ vector table instead of
relying on a custom-generated table.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Both idle and suspend states were just being used to set the cpu
idle. That is not necessary, if the pm policy does not find a suitable
power state the kernel automatically calls k_cpu_idle().
This remove unnecessary code and the weirdness of having
min-residency-us set to 0 and other arbitrary values.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
1. Improve the firmware transfer reliability by fixing the misuse
of the socket. Fix the most frequent occurence of the common `recv()`
bug described here:
https://docs.python.org/3/howto/sockets.html#using-a-socket
The longer term fix is to switch to a higher level API like Python
Remote Objects.
2. Not rely on the client's command to disconnect. Previously we
rely on the SIGINT to send stop_command to the server, but it does
not work well in some environments. Refine the whole logic and the
sever disconnect service by checking if the client is alive or not.
These changes make the client-server-based cavstool more stable.
Fixes#46864
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
Header soc.h is included during C++ source file compilation
and required adding C++ casts as implicit casting from void*
is forbidden. Fixed minor warning comparing signed with unsigned
integer.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Replaced hardcoded for intel_adsp_ace15_mtpm board
HP_MEMORY_BANKS value used in SOF code with generic approach -
using PLATFORM_HPSRAM_EBB_COUNT read from Devicetree.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Properly prefixing some include files with "zephyr", also organizing
the order they are included.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
These two timers were sharing pretty much the same code. Actually
mtl timer was a "superset" of cavs timer. Just merge them into a
single one called intel audio dsp timer (intel_adsp_timer).
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Do not duplicate code in new SoC and reuse code from intel_adsp/common.
Move SRAM code into own file in common code and setup SRAM in soc for
MTL platform.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patch implements pm_state_set function for ACE platforms.
This is initial implementation and only includes the basic handling of
PM_STATE_SOFT_OFF.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch add soc_adsp_halt_cpu implementation for ace. Function disable
power and check CPA status to report success. Function should be used only
for secondary cores and can be executed only from primary core.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Poll for CPA bit by which HW confirms that the core has been powered up.
Signed-off-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
Add ace/mtl rom flags definitions.
Set the flags in battr to indicate to rom that it should execute
secondary core procedure.
Signed-off-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
Meteorlake support as part of the Intel ADSP family.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Co-authored-by: Michal Wasko <michal.wasko@intel.com>
Co-authored-by: Konrad Leszczynski <konrad.leszczynski@intel.com>
Co-authored-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Enjia Mai <enjia.mai@intel.com>
Co-authored-by: Flavio Ceolin <flavio.ceolin@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Bonislawski Adrian <adrian.bonislawski@intel.com>
Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
We need more time to run codes because of the performance,
so I tune CONFIG_SYS_CLOCK_TICKS_PER_SEC down to reduce
the times of running k_usleep(1), then it can pass test_usleep().
Verified by follow test pattern:
west build -p always -b it8xxx2_evb tests/kernel/sleep
fixes#46208
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Keep the cavstwist.sh it is still working by specifying an
environment variable when CAVS_OLD_FLASHER is set. Provide
a fallback once the client-server-based tool does not work
well in some conditions.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
Since the timer interrupt is delivered to all cores at the same
time, it needs to be disabled (or masked) to prevent it from
waking a suspended CPU core.
Note that there is no need to re-enable (unmask) timer
interrupt separately as it is being taken care of in
smp_timer_init() when the CPU re-inits itself.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
To power down secondary cores on cAVS 2.5 platforms the primary core
enables the power-saving mode for the respective secondary core and
waits until that core enters idle() and executes the waiti
instruction at which point the core should enter a lower-power mode.
However, that core can then also automatically wake up and execute
its reset path if, e.g. an interrupt is delivered to it. However, it
isn't entirely clear which events are able to wake up cores from that
state. Disabling interrupts on the interrupt controller didn't seem
to prevent that from happening completely. In particular a specific
ADL notebook seems to be susceptible to this problem. Checking for
such sporadic boots and returning to idle fixes the problem.
BugLink: https://github.com/zephyrproject-rtos/zephyr/issues/46372
BugLink: https://github.com/thesofproject/sof/issues/5733
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Select HAS_MCUX_XBARA Kconfig symbol for MIMXRT1062,
since the XBARA Inter-Peripheral Crossbar Switch peripheral is present
on this SOC.
Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
Added mchp mec zephyr image generator python script. It takes
zephyr.bin as input and produces zephyr.mchp.bin.
The default behavior is to not pad to SPI flash size.
(Enable through CONFIG_MCHP_MEC_UNSIGNED_HEADER=y and
CONFIG_MCHP_MEC_HEADER_FLASH_SIZE_256K=y)
zephyr.mchp.bin is composed of:
1. First 4KB contains TAG at offset 0 and header at offset 0x100
2. Offset 0x1000 is the start of zephyr.bin which has been padded
to a multiple of 128 bytes.
3. Boot-ROM EC Info Block (128 bytes)
4. Boot-ROM Co-Signature Block (96 bytes)
5. Boot-ROM trailer (160 bytes) contains the SHA-384 digest of 2-4.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
A full second is too much, and since "Ack local interrupt before
processing IPC" patch, it doesn't seem necessary. This whole second
wait would break tests that log too much content, as the firmware
is already running during the reset - and the host script wouldn't read
the contents, thus some of the logs would be overwritten.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
External libraries can contain processing module code or common library
code. Library manager need to distinguish between both type of modules
for proper loading.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
This commit introduces driver for granting access for own grant
table and for mapping/unmapping foreign gref. Grant tables are used
for data exchange between Xen domains via shared memory page(s) (e.g.
for sharing ring buffer with driver data) This functionality is
widely used and needed for implementing PV backend/frontend drivers.
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
enable swo output for iMX RT 10xx series. SWO pinmux settings are
currently only present for the RT1060 and RT1064
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
It seems a race can happen between the host acknowledging a DONE
interrupt and the DSP being able to mark some IPC as done. To avoid
this, the host script now always acknowledges the DONE interrupt
_before_ processing the IPC message.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Default to 1 CPU core on the Xilinx Zynq-7000 SoC series since Zephyr does
not yet suppport SMP on aarch32.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add Xilinx Zynq-70000 pinctrl header file to define SoC specific
pinctrl_soc_t structure. This is used to store pin configurations for the
pinctrl driver.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Unlock the Xilinx Zynq-7000 System Level Control Registers (SLCR) at boot
to allow write access using the generic syscon driver.
Since the generic syscon driver uses the DEVICE_MMIO_* APIs for
memory-mapped IO we can remove the dedicated SLCR MMU region.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
When using CONFIG_NPCX_IMAGE_OUTPUT_HEX, set the hex_file
runners_yaml_props_target property, so that west flash will flash the
correct file.
Change the cmake flash rules to populate the hex_file value in the
runners.yaml file if either CONFIG_BUILD_OUTPUT_HEX is enabled or some
cmake file set the runners_yaml_props_target hex_file property.
Update the npcx9m6f_evb instructions now that the filename is implicit.
Signed-off-by: Jeremy Bettis <jbettis@google.com>
They may be disabled in some environments (such as Gentoo based
developer mode on Chromebooks). Use extended regular expressions
instead.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Select missing HAS_MCUX_SRC Kconfig symbol for MIMXRT1062,
that allows using NXP i.MX mcux SRC hwinfo driver.
Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
Adds compatibility with Intel ADSP GDB from Zephyr SDK and
from Cadence toolchain to coredump_gdbserver.py.
Adds CAVS 15-25 (APL) register definitions. Implements
handle_register_single_read_packet to serve ADSP GDB
p packets.
Prevents BSA from changing between stack dump printout
and coredump by taking lock. Observed to be necessary for
accurate results on slower simulated platforms.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
Placing these in the __ram_code section generates a relocation error when
building with toolchain version 0.14.1, moving them back to .text fixes
that (presumably with a performance penalty).
Signed-off-by: Keith Packard <keithp@keithp.com>
ESP32 linker loader needs all sections to be align correctly.
When MCUBoot is enabled, device handles provide by device-handles.ld
does not make the ALIGN(4) at the end, which breaks the loader
initialization. This PR make sure that this particular section
is placed in DRAM instead.
For now this is a workaround until this can be handled in loader script.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Referenced spi_flash_rom_patch.c object was wrongly
linked, which can cause crash due to flash cache disabled
operation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
For some reasons RISCV is the only arch where the vector table entry is
called __irq_wrapper instead of _isr_wrapper. This is not only a
cosmetic change but Zephyr expects the common ISR handler to be called
_isr_wrapper (for example when generating the IRQ vector table).
Change it.
find ./ -type f -exec sed -i 's/__irq_wrapper/_isr_wrapper/g' {} \;
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add the definition of address which is used by ROM to jump to FW.
Signed-off-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Enable testcases under tests/drivers/gpio/gpio_basic_api
To run in twister, "-X gpio_loopback" parameter is needed.
Signed-off-by: Yinfang Wang <yinfang.wang@intel.com>
This commit drops the `IRAM_ATTR` macro from the function declarations
because:
1. `IRAM_ATTR` macro makes use of the `__COUNTER__` preprocessor macro,
which increments for every macro invocation and causes the section
specified in the forward declaration to not match that of the
function definition.
2. Section attributes need not be specified for forward declarations.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Commit b91d21d32c added the possibility to define MPU regions from the
device tree, however commit c276088567 removed that possibility for H7
SoC, as it now uses a SoC specific definition of the MPU regions without
the DT-defined regions (probably because the two PRs got developped in
parallel).
Fix that by adding the macro which adds the DT-defined regions to the
STM32H7 specific file.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Currently there are two soc variants (IT81202BX and IT81302BX) on
it8xxx2 series. The IT81202BX is 128-pin package (GPIO K and L groups
aren't bonding with pad).
This makes soc variant configurable and apply corresponding configuration
for a soc.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Remove v1 implementation from log_core and all references in the tree.
Remove modules used by v1: log_list and log_msg.
Remove Kconfig v1 specific options.
Remove Kconfig flags used for distinction between v1 and v2.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
NS16550 driver no longer relies on definitions found in <soc.h>, SoC can
select UART_NS16550_ACCESS_IOPORT instead.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Files including <zephyr/kernel.h> do not have to include
<zephyr/zephyr.h>, a shim to <zephyr/kernel.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
- The MX25UM51345G flash is connected to FLEXSPI PortA for
mimxrt595_evk.
- Updated flexspi_mx25um51345g driver to support DTR OPI mode.
- Tested with tests/drivers/flash.
Signed-off-by: Chay Guo <changyi.guo@nxp.com>
Add watchdog support to the mimxrt595 platform.
The mimxrt595 platform is excluded from the watchdog
test case because the test case uses variables in the
noinit section that need to be retained through a reset
but the rt595 does not retain this memory through a
reset.
Signed-off-by: Chay Guo <changyi.guo@nxp.com>
Enable access to the HS_SPI pins(JP26) on the mimxrt595_evk board.
Using DMA mode, tested with spi_loopback testcase.
Signed-off-by: Chay Guo <changyi.guo@nxp.com>
Enable I2C access to FXOS7000 sensor on the mixrt595_evk board
Tested using samples/sensor/fxos8700 for mimxrt595_evk_cm33.
Signed-off-by: Chay Guo <changyi.guo@nxp.com>
Select HAS_MCUX_ADC_ETC Kconfig symbol for MIMXRT1062,
since the ADC External Trigger Control eripheral is present
on this SOC.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
Write aligned size also to DGMBS register. At least SOF with linux
host and cavs25 seems to need this for the dma to trigger.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
There is a mul instruction bug.
The bug may cause instructions of writing back CPU GPR (e.g mv a0,s2)
which following the mul instruction to fail.
This patch disables the 'M' extension and overwrite integer
multiplication and division arithmetic library routines with using
hardware multiplication and division and nop instructions.
This will ensure that there is no write back GPR instruction to follow
mul instruction to avoid the bug.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Expose the Xtenesa CCOUNT timing register (the lowest level CPU cycle
counter) using the arch_timing_*() API.
This is the simplest possible way to get this working. Future work
might focus on moving the rate configuration into devicetree in a
standard way, integrating with the platform clock driver on intel_adsp
such that the reported cycle rate tracks runtime changes (though IIRC
this is not a SOF requirement), and adding better test coverage to the
timing layer, which right now isn't exercised anywhere but in
benchmarks.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
pl011 driver uses the new device model and maps the mmio space,
so there is no need anymore to add the entry to the mmu_region
array.
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
pl011 driver uses the new device model and maps the mmio space,
so there is no need anymore to add the entry to the mmu_region
array.
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
When using more than one core on cavs25, some hangs were made
"persistent", as it seems not all cores were being properly reset, thus
compromising tests - if a test hangs for any reason, subsequent tests
that were not restrict to a single CPU would also fail.
This patch mitigates these issues by two changes:
- Closely mimics SOF Linux driver way of loading the firmware. So,
explicit stall and reset (and "unstall" and "unreset") of cores, with
appropriate checks that states have been reached;
- More generous sleep before resetting the stream.
Also, the status of ADSPCS (Audio DSP Control and Status) register is
logged more thoroughly to aid debugging in case new issues arise.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
The name change for cavstool.py has also broken the backward
compatibility for SOF testing. Rename cavstool_server.py back
to cavstool.py. Keep the functionality still as same as the previous
one.
And also update the documentation of it.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
The new client-server-based cavstool has broken the SOF CI testing
due to not considering that loading firmware and output log directly
without daemon is still necessary. Fix that when it is not running
as a daemon.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The soc.c source file did nothing, so just remove it. Remove soc
directory from the include list as well, since there's no header in the
directory that needs to be exposed to the Zephyr build.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
Note that in this case, none of the definitions are used in-tree.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
In this case, the file did not use anything defined in <soc.h>, it only
required access to integer types, e.g. uint32_t.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
SOCFPGA_SYSMGR_REG_BASE is the only definition from soc.h used in tree,
move it to the file using it. Note that this looks suspicious: base
address should come from Devicetree. This patch will allow to drop
soc.h.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
arch/cpu.h was not needed, devicetree.h and sys/util.h are required for
DT API and ARRAY_SIZE().
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<soc.h> has been traditionally been used as a proxy to HAL headers,
register definitions, etc. Nowadays, <soc.h> is anarchy. It serves a
different purpose depending on the SoC. In some cases it includes HALs,
in some others it works as a header sink/proxy (for no good reason), as
a register definition when there's no HAL... To make things worse, it is
being included in code that is, in theory, non-SoC specific.
This patch is part of a series intended to improve the situation by
removing <soc.h> usage when not needed, and by eventually removing it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add a new selectable Kconfig option to decide wether the device driver
is a MMIO device or not. Previous to this patch, the decision was maded
based on the existence of a definition in <soc.h>. The design was
fragile, as code compiled anyway if the definition was not present.
All platforms/boards that had the definition in <soc.h> select the
Kconfig option in their respective defconfig files.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Aspeed AST10x0 series SOC has a SYSCON hardware block at address
0x7e6e2000. Enable this option to enable relative driver.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
This patch is doing several things:
- Core ISA and extension Kconfig symbols have now a formalized name
(CONFIG_RISCV_ISA_* and CONFIG_RISCV_ISA_EXT_*)
- a new Kconfig.isa file was introduced with the full set of extensions
currently supported by the v2.2 spec
- a new Kconfig.core file was introduced to host all the RISCV cores
(currently only E31)
- ISA and extensions settings are moved to SoC configuration files
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This PR adds a soft off mode to the RT10xx Power Management API.
Additionally, it corrects the PM API function in rt10xx_power.c to
use the correct function prototype to be properly overridden.
Signed-off-by: Nickolas Lapp <nickolaslapp@gmail.com>
Make the intel_adsp west runner starting to work on all the
intel_adsp boards. Changes include:
1. Make the cavstool.py work as a service in remote host
ADSP board and rename it to cavstool_server.py.
2. Active the runner and adds a common board.cmake file to
specify the default signing key for cavs boards.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
The cavstool_client.py is a client use to communicate with
the firmware loading and running server which dealing with
the requests from the intel_adsp west runner. It supports:
1. Download firmware to remote ADSP host and running.
2. Send the ADSP log messages back to client.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
There was a confusion on MB_MEMx definitions. Both MB_MEM1/2
should be located in SRAM1. Fix this.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Adds few missing zephyr/ prefixes to leftover #include statements that
either got added recently or were using double quote format.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The current sam0 adc driver not implement correctly the adc_reference
enum values. This try homonize adc input referece by tracking VDDANA
at ADC_REF_VDD_1. The ADC_REF_VDD_1_2 were fixed with correct INTVCCx
channel selection.
Fixes#45443
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The stm32f7 (like stm32H7) should be able to disable
the Dcache when using the DMA. This is to avoid any
pb of cache coherency on the DMA buffers.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Update the new API to use K_USER as the flags for both
CONFIG_USERSPACE and CONFIG_TEST_USERSPACE. Also, fix the linker
script to properly include the suites, tests, and rules.
Fixes#44108
Signed-off-by: Yuval Peress <peress@google.com>
This commit adds a call to the Colorama initialisation function during
the module execution so that ANSI color sequences are properly
converted to the relevant Win32 API calls on the Windows.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit introduces changes in three places in order to fix the
problem with timer-related tests on FE310-based boards:
* tests/kernel/sleep/kernel.common.timing
* tests/kernel/tickless/tickless_concept/kernel.tickless.concept
* tests/kernel/workq/work_queue/kernel.workqueue
The first change is the modification of the SYS_CLOCK_HW_CYCLES_PER_SEC
value back to 32768 Hz to match FE310's datasheet description.
The second change is CLINT frequency reduction in Renode simulation
model to 16 MHz to correspond with the oscillator frequency given by the
FE310's datasheet and the HiFive1 board schematic. This fixes the first
two tests.
The last change is reducing the MIN_DELAY define to 100. This causes the
RISC-V machine timer driver to update the mtimecmp register more often,
which in turn addresses the `work_queue/kernel.workqueue` problem with
work items finishing prematurely, causing the above-mentioned test to
fail.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Up till now the usage of CONFIG_NOCACHE_MEMORY also explicitly disables
data cache on the STM32H7 SoC.
With this change the usage of CONFIG_NOCACHE_MEMORY has been decoupled
from data cache enabling as new Kconfig option - namely
CONFIG_DCACHE is now used to explicitly enable it.
After this change it would be possible to use data cache on STM32H7
with DMA buffers, fragile to cache coherency issues, defined with
'__nocache' attribute.
Such approach would improve the overall STM32H7 performance until the
moment when proper (i.e. in-DMA) buffer cache management is developed.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Config pwm open-drain mode without enabling STORE_REG. This CL
collects all active PWM's base address and related index in an
array. Then, pinctrl driver configs its open-drain mode by
finding the corresponding 'channel' index.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Set SYS_CLOCK_TICKS_PER_SEC to 128 for non-tickless kernel.
Previously it was set to 32768 disregarding kernel mode and that
lead to too frequent interrupts in non-tickless mode (tick every
30 us). Change to smaller value.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
ARCH_HAS_USERSPACE and ARCH_HAS_STACK_PROTECTION are direct functions
of RISCV_PMP regardless of the SoC.
PMP_STACK_GUARD is a function of HW_STACK_PROTECTION (from
ARCH_HAS_STACK_PROTECTION) and not the other way around.
This allows for tests/kernel/fatal/exception to test protection against
various stack overflows based on the PMP stack guard functionality.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
PHY TX power configuration must be added into soc level.
It was previously hardcoded in hal_espressif, which was removed.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The GigaDevice HAL defines CAN_MODE_NORMAL, which conflicts with the
zephyr/drivers/can.h header definition. Undefine it in soc.h.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The GigaDevice HAL defines CAN_MODE_NORMAL, which conflicts with the
zephyr/drivers/can.h header definition. Undefine it in soc.h.
Fixes: #45611
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Updated PSoC 6 implementation to use hal_infineon/mtb-pdl-cat1
This PR is reflected changes according to Task#1 for RFC#42883.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
On STM32WB and dual-core STM32H7 MCUs, the RNG peripheral is shared
between the cores and its access is protected by a hardware semaphore.
Locking was not performed in the current entropy driver, leading to a
race condition when multiple cores concurrently used the RNG. This
commit implements the necessary logic for locking the HSEM during entropy
generation on multi-core STM32 MCUs. It also reconfigures the RNG in case
the configuration was changed by the other core, as this can happen e.g
on STM32WB MCUs.
Signed-off-by: Thomas Altenbach <taltenbach@witekio.com>
Add initial pin control support for the A53 core of the imx8mm. Since
the UART console driver is not currently enabled for this platform,
there is no way to test the full pin control enablement. Therefore,
CONFIG_PINCTRL is still not selected for this platform, although the
required DTS definitions and pin control headers are present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for IOMUXC peripheral present
on mimx8ml8_m7 soc. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a
new header and compatible binding to handle the
different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for IOMUXC peripheral present
on mimx8mq6_m4 soc. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a
new header and compatible binding to handle the
different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for mcimx7_m4 SOC. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a new header and
compatible binding to handle the different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for mcimx6x. The IOMUXC peripheral present on
this SOC is identical to the one used on the iMX RT10xx series, so the
dts bindings are reused.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Refactor iMX RT pin control support to use more generic names, as the
IOMUXC peripheral is present on non RT iMX application cores.
Additionally, make selection of the pin control driver occur at the SOC
level.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This CL is the initial version for npcx pinctrl driver and introduces
pinctrl nodes for both IO-pads and peripheral devices for each npcx
series. Users can set pin configuration via these nodes in the board
layout DT file. It also wraps all configurations related to pin-muxing
in pinctrl_soc.h. Regarding the other pin properties, we will implement
them later.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The drive-mode property is nRF specific, so prefix it with `nordic,`,
same as the `nordic,invert` property.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Enabling an eSPI channel (r.g. Peripheral Channel, Virtual Wire Channel,
etc.) during an eSPI transaction might (with low probability) cause the
eSPI_SIF module to transition to a wrong state and therefore response
with FATAL_ERROR on an incoming transaction.
This CL workarounds this issue by clearing the bit 4 of NPCX eSPI
specific register#2.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Convert the can_mode enum to a bit field to prepare for future extensions
(CAN-FD mode, transmitter delay compensation, one-shot mode, 3-samples
mode, ...).
Rename the existing modes:
- CAN_NORMAL_MODE -> CAN_MODE_NORMAL
- CAN_SILENT_MODE -> CAN_MODE_LISTENONLY
- CAN_LOOPBACK_MODE -> CAN_MODE_LOOPBACK
These mode names align with the Linux naming for CAN control modes.
The old CAN_SILENT_LOOPBACK_MODE can be set with the bitmask
(CAN_MODE_LISTENONLY | CAN_MODE_LOOPBACK).
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add reentrant _gettimeofday_ call so that build
won't fail. This is only a workaround for now.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This PR adds missing configuration to enable newlibc
and cpp code to run in ESP32S2 SoC. This isn't enough though.
Toolchain changes are also needed and will come up next.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Make the available heap for the 128k bank smaller
so that it frees up space for some samples
as pktqueue and smp. In the context of toolchain,
this enables having twister test to pass in those tests
that requires more memory.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Current Espressif porting requires standard include as
part of hal implementation. compiler_flags.cmake checks for
variant name to keep those stdinc in build.
Instead of using variant name as check, use this new CONFIG
to make it clear and to allow having toolchain integrated
in zephyr-sdk package.
stdinc dependency in hal_espressif will be worked out and removed
soon.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add reentrant _gettimeofday_ call so that build
won't fail. This is only a workaround for now.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This PR adds missing configuration to enable newlibc
and cpp code to run in ESP32 SoC. This isn't enough though.
Toolchain changes are also needed and will come up next.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Enable pin control for lpc11u6x soc by selecting CONFIG_PINCTRL=y.
At this time no drivers are ported.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add nSIM-based (simulator) boards with
* nsim_hs5x - single core ARCv3 HS5x 32 bit CPU
* nsim_hs5x_smp - SMP, two core ARCv3 HS5x 32 bit CPU
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
soc: arm: privilege: add Cyclone V SoC FPGA suppport
Add support for the Intel Cyclone V SoC FPGA (arm Cortex-A9).
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
This is a follow-up to commit 586e26e8fc.
Add missing `qdec0` node labels in definitions of SoCs that have only
one QDEC instance so that the `HAS_HW_NRF_QDEC0` option is properly set
for them. Use the same pattern as in the WDT case and keep the existing
`qdec` labels for backward compatibility.
Also update validation of base addresses so that both QDEC0/QDEC and
QDEC1 are checked.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
ADC threshold control register offset is provided by devicetree, this
change will add this property into `adc_npcx_config` structure and
update macro to access register accordingly. Driver behavior is not
meant to be impacted.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
The pm hooks for this target were not updated to follow the current API.
These weak functions will never be called for the pm subsystem.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Fix writing of ICC_SRE_EL3 to or-in bits to align
with original intent to read-modify-write this
register.
Also disable FIQ and IRQ bypass so interrupt delivery
occurs through GIC. Platforms may choose to override
this behavior in z_arm64_el3_plat_init implementations.
Remove ICC_SRE_EL3 config from viper and qemu since
this is now handled in the arm64 arch core.
Signed-off-by: Eugene Cohen <quic_egmc@quicinc.com>
Assembler files were not migrated with the new <zephyr/...> prefix.
Note that the conversion has been scripted, refer to #45388 for more
details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Linker files were not migrated with the new <zephyr/...> prefix. Note
that the conversion has been scripted, refer to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Enable the UTMI PLL (UPLL) clock and add a static definition of its clock
frequency.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
Enable the UTMI PLL (UPLL) clock and add a static definition of its clock
frequency.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
soc_config.c for snps_nsim had no actual code, just a bunch of includes.
Deleting as it has no value (and triggered a compliance warning because
file had no newline at EOF).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In order to bring consistency in-tree, migrate all soc code to the
new prefix <zephyr/...>. Note that the conversion has been scripted,
refer to zephyrproject-rtos#45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
<zephyr/zephyr/types.h> is no longer available, <zephyr/types.h> should
be used instead.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Currently we use incorrect memory layout for SMP boards as
we put data (which need do be accessible from all cores) to
DCCM which is private for each CPU core.
This works for nSIM which doesn't simulate CCMs (as we don't pass
corresponding nSIM options for SMP configurations) however
it won't work if we run that code on real HW (we want to achieve
that nSIM configurations are also runnable on HAPS - FPGA platform).
Let's fix that issue by using DDR instead of CCMs for SMP
configurations (nsim_hs_smp and nsim_hs6x_smp).
While I'm at it - switch UP HS6x configuration (nsim_hs6x)
for DDR usage instead of CCMs - to make that configuration closer
to the HAPS config we have.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Sometimes the remote ssh server is not on default port. This patch makes
cavstwist.sh accept an ssh port in the host address: host[:port].
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Add OpenISA RV32M1 pinctrl header file to define SoC specific pinctrl_soc_t
structure. This is used to store pin configurations for the pinctrl driver.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This reverts commit 91d4b7766c.
Zephyr SDK 0.14.1 now includes QEMU 6.2, which supports the emulation
of the MVE instructions.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Adds a log backend that maintains a ringbuffer in coordination
with cAVS HDA.
The DMA channel is expected to be given some time after the logger
starts so a seperate step to initialize the dma channel is required.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Update the Microchip XEC PS2 driver to support MEC172x.
NOTE: MEC15xx has two PS2 controllers and
MEC172x has one.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
add pincontrol headers for IOCON peripheral present on NXP iMX RT600
and RT500 SOCs, and update LPC pin control driver for iMX RT family
differences.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This modification is required to enable flash encryption.
Using hal implementation of spi_flash calls maintains
compability amongs different socs while offering
latest esp-idf enhancements.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
added support for NXP iMX RT600/RT500 to use to SDHC driver, with SD
subsystem. Tested with RT685 EVK
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable new USDHC driver for all RT10xx boards, since those will have
the SDHC driver selected by Kconfig
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Changes signature so it takes uint32_t instead of pointer to a
register.
Later `sys_read*` and `sys_write*` functions are used, which cast
given address to volatile pointer anyway.
This required changing types of some fields in LiteX GPIO driver and
removal of two casts in clock control driver.
There was a weird assert from LiteX GPIO driver, which checked whether
size of first register in dts was a multiple of 4.
It didn't make much sense, so I removed it.
Previous dts was describing size of a register in terms of subregisters
used. New one uses size of register, so right now it is almost always
4 bytes.
Most drivers don't read register size from dts anyway, so only changes
had to be made in GPIO and clock control drivers.
Both use `litex_read` and `litex_write` to operate on `n`bytes.
Now GPIO driver calculates this `n` value in compile time from given
number of pins and stores it in `reg_size` field of config struct like
before.
Registe sizes in clock control driver are hardcoded, because they are
tied to LiteX wrapper anyway.
This makes it possible to have code, independent of CSR data width.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Adds LITEX_CSR_DATA_WIDTH option to Kconfig
Depending on its value appropriate read/write handling is used
for accessing CSR registers.
By using `>=` in preprocessor conditions it is somewhat future-proofed.
Doesn't touch `litex_read` and `litex_write` yet.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Add the appropriate hooks effectively replacing the old implementation
with the new one.
Also the stackguard wasn't properly enforced especially with the
usermode combination. This is now fixed.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
.module_init sections is used to keep all components constructor
functions.
Zephyr uses -ffunction-sections option which will create a section for
each function. Unfortunately, this creates a section named .module_init
for the function module_init() used to initialize the processing module
generic layer.
Thus, places module_init() in the constructor area named .module_init
which is wrong.
To avoid this we rename .module_init section for constructors to
.initcall.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
The linker script for the intel_s1000 was missing an include for the
snippets-rodata.ld file which is needed for any applications using the
`zephyr_linker_sources(RODATA <linker_script>)` cmake function.
Signed-off-by: Yuval Peress <peress@google.com>
The common linker script for cavs_v?? was missing an include for the
snippets-rodata.ld file which is needed for any applications using the
`zephyr_linker_source(RODATA <linker_script>)` cmake function.
Signed-off-by: Yuval Peress <peress@google.com>
This PR removes common-rom.ld section so that logging sections
can now be mapped into RAM area.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This PR removes common-rom.ld section so that logging sections
can now be mapped into RAM area.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This PR removes common-rom.ld section so that logging sections
can now be mapped into RAM area.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
In c5b59282d6, Kconfig option
CPU_CORTEX_M_HAS_CACHE was added only to a subset of stm32h7 soc
descriptions.
There is no reason not to extend to all socs as they all actually
feature a cache.
Fixes#45073
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
We no longer need to relocate the SDK power management
source file to SRAM. Instead specific functions from the
SDK file are relocated to the ramfunc section.
This commit fixes Issue#44670
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
CONFIG_RISCV_ATOMICS_ISA enables A extension.
CONFIG_RISCV_MUL_ISA enables M extension.
CONFIG_FLOAT_HARD enables F extension. (FPU)
Since we changed to use configuration options to enable extensions,
we no longer need to specify extensions using zephyr_compile_options.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
If a Zephyr binary is booted on the Zynq-7000 not via JTAG download,
but via u-boot's ELF boot function instead, Zephyr will have to revert
certain changes made by u-boot in order to boot properly:
- clear the ICache/DCache enable, branch prediction enable and
strict alignment enforcement enable bits in the SCTLR register.
By default, u-boot will also set up the MMU prior to Zephyr
doing so as well, this can be avoided by changing the u-boot
build configuration. Therefore, the MMU enable bit is not changed
at this point.
- set the VBAR register to 0. U-boot moves the interrupt vector
table to a non-standard location using the VBAR register (no
change is made by u-boot for SCTLR.V, only VBAR is changed
to a non-zero memory location).
Without these changes, Zephyr will crash upon the first context
switch at latest, when SVC is invoked and u-boot's vector table
is used rather than the vectors copied to address zero by Zephyr.
In order to perform these changes before coming anwhere near the
MMU / device driver / kernel initialization stages or even the
first context switch, the z_arm_platform_init hook is used, which
is now enabled for the Zynq via the Kconfig.defconfig file.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
pin control definitions present for LPC55xx are not generic to all LPC
IOCON controllers. Make pin control header file LPC55xx specific.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds hda link in and out drivers. The link in and link
out channels of HDA have small differences
with the host channels. Updates the existing
cavs_hda drivers and code to account for these
differences.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
all the consumers of the obsolete pinmux driver is
updated to use pinctrl API, this commit removes
the pinmux driver and assosciated sections.
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
Add pinctrl driver for CC13XX/CC26XX family of SoCs
to facilitate transition from pinmux to pinctrl.
`IOCPortConfigureSet()` from TI hal driverlib used to
implement the generic pinctrl driver.
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
1.Declare the member type to match the kscan_it8xxx2_regs, so
we needn't to transform the local structure in the function.
2.Stop using DRV_CONFIG, DRV_DATA, DRV_REG macros.
3.Delete unused register defines.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
The Cache is an optional configuration of both the ARM Cortex-M7 and
Cortex-M55. Previously, it was just checking that it was just an M7
rather than knowing that the CPU actually was built with the cache.
Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
Zephyr kernel will always execute WFI in k_cpu_idle(), so access to TCM
will be gated. Keep the AHB clock enabled in sleep unless CONFIG_PM is
selected, to avoid this error.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Platform specific functions necessary to enable this feature were
implemented (z_xtensa_ptr_executable() and
z_xtensa_stack_ptr_is_sane() for Intel ADSP platforms.
Current implementation just ensures stack pointer and program counter
are within relevant areas defined in the linker scripts, without going
too fine grained.
Also, `.iram1` section, used by the backtrace code, also added to
Intel ADSP linker script.
Finally, update west manifest to use up-to-date SOF, which contains a
patch to fix build issues related to the linker changes.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Add MPU REGION_FLASH_SIZE definitions for 128M-512M flash sizes, to handle
arm SOCs with large flash regions.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
When we use a third-party or custom bootloader, there is also
need to remove the boot header. Change the select to imply,
so that the boot header can be removed by configuration when
MCUBoot is not used.
Signed-off-by: Frank Li <lgl88911@163.com>
Align definitions with definitions used in SOF upstream and define
CONFIG_XTENSA_WAITI_BUG for cAVS1.8, cAVS2.0 and cAVS2.5 platforms. On
these platforms, a workaround is needed with waiti.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
DBGMCU register, which is used for SWO pin configuration,
may not have TRACE_MODE bits in some STM32 MCUs.
Replace register access with LL functions selected based on SoC family.
Fixes#44584
Signed-off-by: Alexander Vasiliev <alex.m.vasil@gmail.com>
Due to a wide range of variuation in the LSI RC oscillator
characteristics given by the datasheet of the soc,
It is necessary to add a delay for hardware watchdog.
This is done by the CONFIG_TASK_WDT_HW_FALLBACK_DELAY
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add soc_secure_mem_read implementation for secure.
This simplifies users code so that ifdefs are not required.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
The limitation on HWINFO_NRF depending on not nonsecure was removed in
52be3030aa.
This caused problems when TF-M was not enabled.
This happens on the thingy53_nrf5340_cpuapp_ns board since this board
is not supported by TF-M.
Introduce proper dependency handling for the soc secure functions
to make HWINFO_NRF unavailable when no secure services exist in
nonsecure.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
This reverts commit b1ad97bc26 since it
causes the following build failure:
cc1: error: requested ABI requires '-march' to subsume the 'F'
extension
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Add pinctrl definition header, to parse pinctrl groups in board level
DTS into pinctrl_soc_pin_t values.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Rather than specify input clock for each peripheral individually, instead
specify the relevant clocks in DTS.
This will enable easier support for non-default coreclk on fe310 in a
follow-up CL.
Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
IT8xxx2 supports the standard 'F' extension for single-precision
floating point: select the relevant Kconfig option for the SoC so
users can build floating-point code.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: Ie6da1d38d5654061553cb1ce13b0a0a96aa71ce0
The autoconf.h header is not required because the definitions present in
the file are exposed using the compiler `-imacros` flag.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Currently the only way for a BOARD/SOC to configure at compile time the
MPU regions is to add, in a soc-specific file, the 'mpu_config' struct
adding static entries for the new regions with the needed attributes
(cacheable, non-cacheable, etc...). This exported struct is then read by
the MPU driver at boot time and used to properly setup the MPU regions.
At the same time it is now possible to introduce new memory regions in
the DT using the newly introduced 'zephyr,memory-region' attribute.
What is missing is the link between these two solutions: that is how to
declare the memory regions in the DT and automatically configure these
regions in the MPU with the correct attributes.
This patch is trying to address exactly this problem.
It is now possible to declare the memory regions in the DT and define
the MPU attributes for the regions using the 'zephyr,memory-region-mpu'
property. When this new property is present together with the
'zephyr,memory-region' property and a the 'zephyr,memory-region'
compatible, the 'mpu_config' struct is automatically extended at
compile-time to host the DT defined regions with the correct MPU
attributes.
So for example in the DT we can now have:
sram_cache: memory@20200000 {
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20200000 0x100000>;
zephyr,memory-region = "SRAM_CACHE";
zephyr,memory-region-mpu = "RAM";
};
and a new region will be created called "SRAM_CACHE" and a new MPU
region will be configure at boot time with the attribute
"REGION_RAM_ATTR".
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This macro conflicts with C++'s std::condition_variable::wait_for
and makes it very difficult to use Zephyr with C++. Replace it with
an all uppercase name which fits the naming standard better.
Signed-off-by: Yuval Peress <peress@google.com>
Add soc_secure_read_deviceid function for reading the device ID from
FICR when executing in non-secure processing environment.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Refactor soc_secure handling to not use TF-M directly in the header.
Move from nRF53 to common since nRF91 also supports TF-M.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Instead of selecting appropriate HAS_HW_NRF_* options for particular
nRF SoCs (and simulated nRF52 target), set their values basing on
information from devicetree.
Correct also semantics of those options so that they are set only when
a corresponding DT node is enabled. This allows using them directly in
Kconfig dependencies of Zephyr drivers for nRF peripherals. Update
appropriately these dependencies.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add missing devicetree nodes representing the following peripherals
in nRF SoCs:
- ACL
- BPROT
- CCM
- COMP/LPCOMP
- CTRLAP
- DCNF
- MPU (nRF MPU peripheral in nRF51 Series, not ARM MPU)
- MUTEX
- MWU
- NFCT
- OSCILLATORS
- POWER (in nRF51 and nRF52 Series)
- PPI
- RESET
- SWI
- USBREG
Add also corresponding bindings and validation of base addresses of
these nodes.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The NXP SDK defines CodeQuickAccess and DataQuickAccess sections
for locating critical items that need faster access. Centralize
the handling of these sections instead of doing it per SOC.
Fixes#44453
Signed-off-by: David Leach <david.leach@nxp.com>
Don't leave idle state if soc isn't waked-up by an interrupt.
(We change to check interrupt controller register)
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
When run the test_mutex_lock_timeout(), we need more time (>300us)
for the testing thread to finish the job, or we will get a fail
(we didn't run the test before).
Because our event timer doesn't handle the float part, and 32768 is
divisible by 8192 which is closest to kernel tick default 10000, I add
CONFIG_SYS_CLOCK_TICKS_PER_SEC = 8192 for all board of it8xxx2 series.
If the CONFIG_SYS_CLOCK_TICKS_PER_SEC = 32768,
the 10 tick of timeout = 300us.
If the CONFIG_SYS_CLOCK_TICKS_PER_SEC = 8192,
the 10 tick of timeout = 1200us.
So we can get more time to finish the job.
Verified by follow test pattern:
west build -p auto -b it8xxx2_evb tests/kernel/sleep
west build -p auto -b it8xxx2_evb tests/subsys/portability/cmsis_rtos_v2
fixes#43513fixes#42847
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Rather than defining them in the header, require a set of defines
be provided to cavs_hda.h as part of the expected input to the API.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Adds an initial driver for HDA streams on cAVS. A common code base is
provided for all HDA streams while the drivers are identified
differently as they have small behavior differences.
Uses dma_status to describe the positions for read/write. Uses dma_reload
to inform when to move the read/write positions. This closely follows
how HDA is being used in SoF
Simple test case is provided for both drivers.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Adds a header only low level driver for HDA streams along with smoke
tests to ensure basic host in and out stream functionality.
The tests require host side interaction. In cavstool a new HDAStream
class encapsulates somewhat a single stream and its registers. This
is manipulated in the tests using IPC with the Host ensuring that a
specific order of operations is done.
This low level driver allows testing certain hardware configurations
and flows with easy to use register dump debugging. It is not
intended to be the end API an application might use. That would be
a DMA driver using this.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
The IPC enum definition and WAIT_FOR macro are useful outside of
the board smoke tests for intel_adsp. They can be commonly used
by other board tests for a variety of peripherals that require
DSP and Host interaction (using cavstool).
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Correct eSPI flash macro so it not always results in zero,
leading to eSPI flash read operation in all cases:
Read, write, erase.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Added support for 8 MB MPU regions for SRAM sizes between 4 and 8 MB,
and 16 MB MPU regions for SRAM sizes between 8 and 16 MB.
Signed-off-by: Johan Öhman <johan.ohman@softube.com>
Customize busy wait timer for micro-seconds accuracy.
Verified by follow test pattern:
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_api
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_error_case
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_monotonic
west build -p auto -b it8xxx2_evb tests/kernel/timer/starve
west build -p auto -b it8xxx2_evb tests/kernel/context
west build -p auto -b it8xxx2_evb tests/drivers/adc/adc_api
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
SMP support might not work if esp_mp.c initialization code
is placed in ROM area. This fix that scenario.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Only cAVS15 is different in terms of definitions, so the ifdef logic can
be simplified quite a bit. Also reorder some of the definitions to
improve readability. No functional change.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Enabled the Shared Memory Reset feature for nRF5340 Application Core
when the RPMsg backend for IPC Service is enabled.
Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
Based on introduction of plain GPIO configurations in STM32 pinctrl
bindings, update STM32 pinctrl/gpio drivers to make this functionality
available.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Some pinctrl related definitions are still defined
in pinmux related files.
Duplicate definitions to prepare pinmux removal.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
All iMX RT 1xxx boards are now expected to use pin control, so the USDHC
pinmuxing callbacks can be removed.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable soc ethernet ref clock output at the SOC level instead of board
level, since it is required for all iMX.RT SOCs
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RT11xx series has similar pin configuration peripheral to RT10xx, with
some differences in register layout. Create new pinctrl definition
header file, and reuse existing driver code for RT10xx.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
iMX.RT parts use a GPR register for some pinmux settings. Update pinctrl
driver to support this GPR register definition.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
OCRAM can be used for DMA, and in this case it should be marked as
noncacheable. Add KConfig symbol and appropriate linker scripts to
enable OCRAM region to be defined as noncacheable, and initialized with
data from flash at boot.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This update current Atmel sam0 pinctrl initiative to current Zephyr
pinctrl API. It update current devicetree bindings and add the sam0
pinctrl driver.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update current Atmel sam pinctrl initiative to current Zephyr
pinctrl API. It update current devicetree bindings and add the sam
pinctrl driver.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit fixes the default value of SYS_CLOCK_HW_CYCLES_PER_SEC
option. The previous value of 32768 is not consistent with the
documentation of FE310 SoC. Only FE310-based boards rely on the default
value of this option; other boards from the Freedom series define it
themselves.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit makes the transition from the pinmux driver to the pinctrl
driver. It also modifies UART, SPI and I2C drivers used in FE310-based
boards to use the new pinctrl API.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
In npcx adc driver, we select 'Scan' (Multiple Channels Operation Mode)
mode by default. It means that selected channels in ADCCS will be
converted automatically. Then, read the measured data from CHNDAT
registers if EOCCEV (Event is set after all selected channels are
converted.) flag in ADCSTS is set.
But we enable the wrong interrupt type, INTECEN, during adc
initialization. Ec will send the interrupt after each channel in ADCCS
is converted. It has no harm to the current driver since the driver
reads all selected channels and turns off ADC converter only after
EOCCEV is set in ISR. But it does generate spurious interrupts.
This CL enables the correct interrupt type, INTECCEN, during adc
initialization. Ec only sends the interrupt after all of channels in
ADCCS are converted.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This is required to include the resource table in the build output. The
Linux remoteproc framework explicitly looks for this section while loading
the elf and may complain if the resource table is missing.
Signed-off-by: Matthias Fend <matthias.fend@emfend.at>
Aspeed ast10x0 series SoCs contain a ARM Cortex-M4F processor. This
processor operates at 200MHz and executes on SRAM.
This patch adds support for ast1030 as the first SoC of this series
which is targeted but not limited at the bridge IC in a server system.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I668af1ff8a36a05da791c3329ae08f5ae712bdd4
KW24 and KW22 series support open drain pins, while rest of kinetis KW
SOCs do not. Don't redefine PORT_PCR_ODE for these SOCs
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Extend the macro with checks for DT properties related to pin
assignments that are defined but would be ignored, depending on
whether PINCTRL is enabled or not, what presumably indicates
a resulting configuration different from what the user expects.
Add also a possibility to indicate that the pinctrl-1 property
should not be checked because the caller does not support the
sleep state.
Rename the macro so that its name better reflects its function.
Update accordingly all drivers that use it.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add Kconfig items that can be used to query if the current SoC
support the HW peripheral CTRLAP.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
As mentioned in #42882, the I2C of IT8XXX2 is designed for two different
IP blocks, so this PR divides this I2C driver into two compatibles.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Using IRQ as source for interrupt values can
fail when installing irq_connect_dynamic, as
IRQ can previously be enabled. This updates
the logic to use source map and allows
default irq_enable() and irq_disable() to call
esp32c3 interrupt allocator implementation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Enable support for mtvec vectored mode for privilege SOCs. This
is an optional feature and takes up addtional code space. It is
necessary to support this feature for privilege SOCs that only
support mtvec vectored mode.
Change was tested on qemu_riscv32 and qemu_riscv64 boards with
CONFIG_RISCV_MTVEC_VECTORED_MODE enabled.
Signed-off-by: William Patty <wpatty24@gmail.com>
The SOF ipc4 driver and Windows driver can't work with
SOF built with zephyr and ipc4 configuration on cAVS 1.8+
platforms. Because the UUIDs of BRNGUP and BASEFW are
copied from APL (cAVS 1.5), which is incompatible with
cAVS 1.8+ platforms.
This patch updates BRNGUP and BASEFW to use cAVS 1.8+ UUIDs.
Signed-off-by: Chao Song <chao.song@linux.intel.com>
Signed-off-by: Rander Wang <rander.wang@intel.com>
The pm_constraint_* APIs were effectively used by the policy manager
only. This patch renames the API to the policy namespace and makes its
naming more explicit:
- pm_constraint_set -> pm_policy_state_lock_get()
- pm_constraint_release -> pm_policy_state_lock_put()
- pm_constraint_get -> pm_policy_state_lock_is_active()
The reason for these changes is that constraints can be of many types:
allow/disallow states, impose latency requirements, etc. The new naming
also makes explicit that the API calls will influence the PM policy
behavior.
All drivers and documentation have been updated accordingly.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Re-running the script that checks for the const qualifier missing on
ISR's parameter.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add support for configuring pins to be used by the nRF PWM, QDEC, and
QSPI peripherals.
A new custom property "nordic,invert" is added to the pin configuration
group binding to allow configuring PWM channel outputs as inverted.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add a 4k indentity mapping in the MMU for the Processor System GPIO
controller if the parent device node is enabled in the device tree.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Removing backend config from board Kconfig.defconfig and moving
it to xtensa_sim backend configuration in logging. Without this
change define persisted even when logging was not using backends
and that impacted what is compiled in.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Move the file from board to soc to make it could be shared by
i.MX8M family. When MCUX_HAL supported in future, this file could
be dropped.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
We could reuse the common linker script, no need use i.MX8M specific
one. BTW i.MX8M family is based on A53 core.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
USB pll clock should be enabled if USB driver is used. Add required
configuration for USB pll clock.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This is mostly the same than the aarch64 one, excepted that we
force the armv8r fvp to run in aarch32 profile. So that we can simulate
the Cortex-R52.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
According to Kconfig guidelines, boolean prompts must not start with
"Enable...". The following command has been used to automate the changes
in this patch:
sed -i "s/bool \"[Ee]nables\? \(\w\)/bool \"\U\1/g" **/Kconfig*
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add build assertions that will ensure that every peripheral for
which a driver instance is created has some pins assigned to it.
Neither pinctrl-0 nor *-pin properties can be currently marked as
required in devicetree, so these assertions will help users avoid
invalid configurations where it could be hard to figure out why
the UART is not working.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
nRF5340 application core should not attempt to pass control over any
pins to the nRF5340 network core if the latter is disabled.
This commit fixes https://github.com/zephyrproject-rtos/zephyr/issues/43476.
Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Commit bdce0a5742 ("soc/intel_adsp: Add a cavs_ipc driver to manage
host IPC") added a new driver for cAVS IPC. Although patch included the
CONFIG_CAVS_IPC option, in practise this had no effect and instead
driver was enabled whenever device tree included IPC hardware. This
caused IPC errors in SOF application builds where two drivers, one out
of tree in SOF and one in Zephyr, initialize the same hardware.
Fix the issue by enabling the driver only when CONFIG_CAVS_IPC is
enabled.
BugLink: https://github.com/thesofproject/sof/issues/5477
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Enables low power clocks for mimxrt1064. This allows the soc to
transition into very low power states during idle, as most PLLs can be
disabled. Power states need to be enabled and selected at the board
level.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add power management code for the RT10xx SOC. By default, the code will
simply gate the core clock and transition the SOC to WAIT mode when
sleeping, but if clocking hooks are register to reduce clock frequencies
these will be called as well, and the SOC core voltage will be lowered
for additional power savings.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add KConfig symbols to select power management HAL drivers required for low
power modes. Set ZTEST_NO_YEILD if PM is enabled, since RT series SOCs
do not connect to a debugger in WAIT mode.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The NXP KE1xF SoC series does not support neither slew rate nor open
drain PORT configuration registers.
Fix pinctrl compilation for the KE1xF by defining dummy register macros
for the SRE and ODE registers.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Remove a redundant symbol that was used as a proxy to enable CONFIG_PM.
If an application needs to enable PM, it should just enable PM subsystem
Kconfig options. Furthermore, there's no clue "SOC_POWER_MANAGEMENT" is
a Microchip specific option.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Rename CONFIG_SOC_POWER_MANAGEMENT_TRACE to CONFIG_NPCX_PM_TRACE so that
it is clear that it's a NPCX specific option.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Remove a redundant symbol that was used as a proxy to enable CONFIG_PM
and CONFIG_PM_DEVICE. If an application needs to enable PM, it should
just enable PM subsystem Kconfig options. Furthermore, there's no clue
"SOC_POWER_MANAGEMENT" is a NPCX specific option.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The ADC driver of IT81302 chip can support channels 0-7 & 13-16.
This PR adds to implement ADC channels 13-16.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This configures soc and flash size definition
using DTSI information instead of hardcoded
values.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This modifies esp32s2 SOC configuration to support MCUBoot.
CmakeLists is moved from board to soc specific. It also
includes MCUBoot changes.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This change updates startup code to setup MMU mappings.
west: update hal_espressif revision so that rom calls, i.e
esp_rom_Cache_*, can properly be used in MMU mapping.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This change creates XiP image handling and proper
LMA and VMA regions configurations.
This also adds common-ram.ld and common-rom.ld sections that
require explicit handling due to image sections limitation
in esptool.
Move additional drivers into IRAM to protect against
flash cache disable read/write operation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add pinctrl include file to define SOC specific pinctrl_soc_t structure,
used to store pin configuration for pinctrl driver
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Attaching SFRO clock to FlexCOMM0 should be conditional on the
device tree as an application may not need SFRO attached to FlexCOMM0.
Signed-off-by: Bryce Wilkins <bryce.wilkins@gmail.com>
The same options were copied to each Kconfig.defconfig, in different
places (my own doing) for both DMA and I2S. This dedups the defines and
moves them into the common soc Kconfig.defconfig.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Acorrding to RM, HIFI4 DSP default configured frequency is:
- 666Mhz for i.MX8
- 800Mhz for i.MX8M
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
The Bluetooth HCI driver based on the RPMsg transport now uses the IPC
service module. The compatible Bluetooth sample - HCI RPMsg - has also
been migrated to the new IPC solution.
Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
Add configurable init priority for nrf53 synchronized rtc module.
Add build time assert to ensure that initialization is done after
mbox.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Make xtensa/intel_adsp/common/rimage_modules.c CAVS-specific by adding a
guard.
Signed-off-by: Konrad Leszczynski <konrad.leszczynski@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Make xtensa/intel_adsp/common/boot.c CAVS-specific by adding a guard.
Signed-off-by: Konrad Leszczynski <konrad.leszczynski@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add a fairly simple test of the IPM-over-IPC driver. This hits all
the code, but works by implementing the host side of the protocol
partially in the C test code. The message is sent with an initial
payload, and then IPC commands from the firmware copy the data over
into the "inbox" region to simulate data being sent via the host.
Then we make sure it lands correctly as if the host driver had done it
directly.
This requries a new command in the cavstool script that will copy a
word from the "outbox" region to the "inbox" region (both are just
different SRAM windows, conceptually no different than the way the
script is already managing log output), but no significant surgery.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Now that we have easy access to code on the host, it's trivial to
check the clock against host timestamps with high precision.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
On cAVS 1.8 (specifically) there seems to be a propagation delay on
the IPC registers. Hitting the TDA register to signal DONE too soon
after clearing the interrupt via TDR can cause the interrupt to be
dropped. Merely polling for it to read back correctly isn't
sufficient, we need an actual sleep here.
(The behavior that a message won't send while an existing message is
in progress is actually a hardware feature that is new with 1.8. My
guess is it's a little glitchy in its first version.)
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
On cAVS before 2.5, core power was controlled by the host. Add a
command to the cavstool.py script to allow us to do that under test
command so we can exercise multiprocessor startup/shutdown outside of
SOF.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Remove the soc_relaunch_cpu() API. There's now nothing that this does
that isn't already done by the kernel's own z_smp_start_cpu() API. We
don't need a SOC-level API for this anymore.
Rename soc_halt_cpu() to soc_adsp_halt_cpu() to clarify the domain,
simplify by removing the synchronization (there's nothing to
synchronize!). Also move its declaration and docs into the soc.h
header.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Things had gotten a little tangled in there so let's do some cleanup.
Remove the distressingly-special-purpose z_reinit_idle_thread() hook
(which existed to support secondary core bringup when
SMP_BOOT_DELAY=y), and just fold that into a generic z_init_cpu(),
which we can call in obvious and symmetric ways from main
initialization, z_smp_init(), and z_smp_start_cpu() (the now-official
programmatic hook for starting cpus).
Remove the "#if CONFIG_MP_NUM_CPUS > 1" exclusions. These weren't
saving any code size and were propagating themselves into platform
layers trying to avoid build failures.
There are some "special" APIs added for SOF which need to go away in
favor of the newer/generic z_smp_start_cpu(). Collect them in one
place and put them under a "#ifdef CONFIG_SOF" to prevent them from
being used in Zephyr apps.
Move some function declarations that didn't have homes into
<kernel/thread.h>.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
As Zephyr begins to absorb drivers for these platforms that had
previously been managed by the SOF app, there's a need for a rapid
board-specific smoke test to use during development.
This starts with the smp_boot_delay test (itself a unit test for a
SOF-derived feature) and adds a host IPC case (that needs to match
code in cavstool.py on the other side of the PCI bus!).
It will grow more features over time as needed.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This is a slightly higher level Zephyr device that manages the host
IPC device for applications. There's an interface to make synchronous
and asynchronous calls, to receive commands via (interrupt context)
callbacks and emit async "done" notifications after processing is
complete. It should work for pretty much any application
architecture.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The constraints API offered by TI HAL is meant to be used externally,
for example, when implementing a policy using their policy mechanism
(not used on Zephyr). The API is likely designed for systems where a
thin RTOS is used (e.g., FreeRTOS, TI-RTOS?), places where you basically
get a Kernel and a few services around, but not a system like Zephyr
where you also get, for example, a power management subsystem. This
means that it gets difficult for an RTOS like Zephyr to use such HAL
APIs while using its own constraints API. The first question is why we
allowed such kind of HAL code to be part of upstream Zephyr. It
certainly does useful things, but it is also uses a HAL infrastructure
which is hardly exportable to an RTOS like Zephyr. Part of the
Power_init() code, for example, should likely be in a clock controller
driver, where Zephyr APIs can be used.
The _solution_ that was done to workaround this case was allowing custom
full re-implementations of the constraints API. So we are basically
overwriting a functional API with custom HAL code because of poor HAL
designs. This is in general a bad design principle. If we allow this, we
can hardly offer any guarantees to the API users. For example, is
re-implemented as thread-safe? What is the API behavior then? ...
Platforms like TI that have incomplete support in Zephyr tend to leverage
to HAL code certain functions that should be proper Zephyr
drivers. Such platforms should not influence the design of APIs because
they lack solid foundations.
This patch removes the custom implementation since the HAL has been
patched so that it forwards PM state constraints to Zephyr.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Currently xenvm board/soc is configured to use GICv2 and there
is no clean way(without modifying the source code) to alter this
configuration to use GICv3.
Due to the increasing number of users wishing to use GICv3, add
a new configuration called xenvm_gicv3 that enables GICv3.
Create a Kconfig file and add a config XENVM_USE_GIC_V3 that,
if set, will cause SOC_XENVM to select GICv3 instead of GICv2.
Update documentation accordingly.
Take the opportunity to remove the unnecessary config options
from the defconfig files.
Signed-off-by: Michal Orzel <michal.orzel@arm.com>
Use CLINT to send interrupts to another CPU. SMP support is kinda
incomplete without it.
This patch only enables it for riscv-privilege platforms - specifically,
"virt" one.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Secondary CPUs are now initialised and made available to the system. If
the system has more CPUs than configured via CONFIG_MP_NUM_CPUS, those
are still left looping as before.
Some implementations of `soc_interrupt_init` also changed to use
`arch_irq_lock` instead of `irq_lock`.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Add a new board to support Intel Tiger Lake H PCH variant of cAVS2.5.
Move common Kconfig options for cavs25 to soc level. No need to
replicate these for every board.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Aligning with the rest of PM API, replace pm_power_state_exit_post_ops
with pm_state_exit_post_ops.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Commit 7cdd10bf89
("soc: arm: nordic: add NRF_DT_GPIOS_TO_PSEL_BY_IDX") added a use of
NRF_GPIO_PIN_MAP to soc_nrf_common.h without including the relevant
HAL header where it is defined, hal/nrf_gpio.h.
Unfortunately, including that header causes even more problems, since
it causes undefined NRFX_ASSERT() calls to appear elsewhere in the
tree.
It's not really worth bothering to use this macro. Just expand it
inline instead.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Extend initialization code for nRF5340 application core to iterate over
child nodes of GPIO pin forwarder node and pass control over detected
pins to the network core.
Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Add a macro that allows to retrieve pin's PSEL from its devicetree
representation taking into account its index into GPIO array.
Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
With a number of the i.MX SoCs (e.g., the i.MX8M Plus), NXP has moved to
supporting the integrated Cortex-M cores with the MCUXpresso SDK (MCUX).
As a result, certain Zephyr drivers (such as the IPM driver) need to be
updated to utlize this new MCUX-based SDK.
This change adds support for the MCUX Messaging Unit driver pulled in by
this PR:
https://github.com/zephyrproject-rtos/hal_nxp/pull/130
Additionally, this change enables the new IPM_IMX_REV2 config for the
mimx8ml8_m7 SoC target which utilizes this new revision of the driver.
Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
The current MCUX IGPIO driver assumes that the target SoC supports
the DR_SET, DR_CLEAR, and DR_TOGGLE functionality, but some do not
(namely, the M7 core of the i.MX8M Plus SoC). Current releases of
the MCUXpresso SDK IGPIO driver contain utility functions to set,
clear, and toggle pins which include provisions to support SoCs
with and without DR_SET, DR_CLEAR, and DR_TOGGLE, and this change
switches to using these utility functions.
Additionally, this change enables GPIO support on the mimx8ml8_m7
target.
Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
This register is a pre-define hardware slave A and can be accessed
through I2C0. It is not currently used, so it can be disabled to
avoid illegal access.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The Xtensa implementation of arch_irq_offload() required that the user
select the correct interrupt manually, and would race with itself if
invoked from separate CPUs (it was saved here by the main
irq_offload() function which has a semaphore to serialize access).
Use the new gen_zsr.py script to automatically detect the highest
available software interrupt, and keep a per-CPU set of
callback/parameter pointers.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Introduce a new "zephyr,memory-region" compatible to be used when a new
memory region must be created in the linker script from the devicetree
nodes using the compatible.
Remove also the LINKER_DT_REGION_FROM_NODE macro and add a new
LINKER_DT_REGIONS macro to cycle through all the compatible regions.
In the same PR modify the DTS files and the linker scripts.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This enables the below configuration so the AP and EC are able to
communicate over eSPI:
CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION
CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
We are enabling logging in the SoC, this should be an application
decision, not a hardware decision.
Additionally, we are disabling logging defaults for testing, which
results in some tests failing on those platforms due to missing messages
in the test output.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not include psl-in related code is the status of vsby-psl-in-list is
disabled, which can help reduce a little RAM/flash size.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Failures to boot are not exclusive to the cavstool.py, they can happen
with the kernel driver and --log-only too. For such a situation this
commit adds a useful delay and these two log lines (before the mmap
crashes eventually):
INFO:cavs-fw:Waiting for firmware handoff, FW_STATUS = 0x81000012
WARNING:cavs-fw:Load failed? FW_STATUS = 0x1006701
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Intel's adsp needs to set, at a minimum, a clocking bit before the driver
can initialize the designware dma controller. In many ways it is the
designware dmac IP but with additional registers and functionality added
on top of it. So the code structure here follows how the hardware
appears to be designed, layered on top of the designware driver.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
This patch adds GPIO and 96board LS (Low Speed)iexpansion connector
support for SiFive HiFive Unleashed and also enables GPIO basic test.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
The XEN_INITIAL_DOMAIN option was defined at board level, however, some
drivers such as the XEN serial driver has dependencies on
XEN_INITIAL_DOMAIN, meaning any new board has to define its own copy of
XEN_INITIAL_DOMAIN. Move the option to SoC Kconfig.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The help for MCHP_ECIA_XEC is defined in
drivers/interrupt_controller/Kconfig.xec. defconfig files must not
re-define prompts or help, just modify the default value.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The SoC Kconfig.defconfig.series files re-defined multiple Kconfig help
entries. The help for such symbols should only be present in places
where symbol is actually defined, not where the defaults are changed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The xtensa/sample_controller linker script is missing the necessary
include statements for linker snippets. So add them.
Fixes#42477
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
replacing usage of the ESPTOOLPY_FLASHSIZE config
by the equivalent dt property path
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
replacing usage of the ESPTOOLPY_FLASHSIZE config
by the equivalent dt property path
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Non-standard `jalr rd, rs` pseudo-instructions are used.
This commit changes them to `ret` for standard return pseudo-instruction
or `jalr rd, rs, 0` for no offset jump register and link.
Fixes#41100.
Signed-off-by: Henry Hsieh <r901042004@yahoo.com.tw>
The ADC driver now supports three different implementations. To maintain
readability, this patch implements an adc_fixup.h that permits more
generic access to relevant registers.
This patch also introduces support for a new third shape ADC - as found
in the SAML21 for example.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Modified Xtensa soc intel_adsp to use nul when building on Windows host
and /dev/null when on Linux.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Divisor must be set to calculate SD host controller clock frequency in
clock driver.
Fixes#42380
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added basic support for the RP2040 SoC. Support
includes booting and starting the kernel, on one
core only.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add handling of secure-only code with TF-M enabled that can only be done
from secure processing environment.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Clear the LPSDSR bit of PWR_CR to restore the voltage regulator
mode when exiting from STOP mode. Leaving LPSDSR set can cause
cause stability issues because the MCU will enter low-power sleep mode
instead of normal sleep mode when the core idles and this is not what
the rest of the implementation expects.
Signed-off-by: Alexander Mihajlovic <a@abxy.se>
Audio users want logging too. This restores feature parity since the
older scripts were removed in commit
cd5302fa00 ("boards/intel_adsp_cavs15: Remove ancient tooling")
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Don't "crash" when passing no argument at all.
Log exceptions, adding for instance the second line:
ERROR:cavs-fw:Could not map device in sysfs; run as root?
ERROR:cavs-fw:[Errno 13] Permission denied: \
'/sys/bus/pci/devices/0000:00:0e.0/power/control'
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Add an cavs-ipc-regs.h header for the SOC with definitions for the IPC
mechanism used for host communication.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There is a hardware bug with stream reset, it won't stop the stream.
I thought it was limited to just the early versions, but it turns out
that 2.5 has it too in some variants. Which is frustrating, because
the TGL chromebook I have doesn't like the START clear. But all
systems work with an extra delay between them, so do that.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This platform was stale for a long time and got a little left behind.
Basic OS stuff was working but secondary core bringup didn't. It has
a slightly different set of choices from the "weird hardware
quirks" menu:
+ Like cAVS 1.5, it boots from a ROM that needs a short delay after
power-up before it can receive the startup IDC.
+ But, like 2.5 and unlike 1.5, it doesn't start running until the
PWRCTL bit for the core gets set by DSP software (1.5 gets launched
by the host). So the delay needed to move down a bit.
+ It wants that PWRCTL bit to be set last, after CLKCTL enables the
clock. (Which makes sense I guess: EE classes always tell you hold
circuits in reset while an initial clock propagates). Not sure why
it was in the reverse order originally; this way works for
everything.
+ The ROM likes to scribble on the interrupt controller and mask its
own IDC interrupts after we've already set it up. They have to be
unmasked. We had code to do this already, thinking it was a
workaround for legecy SOF code (that we never actually located).
Now I'm thinking it was this behavior all along being detected by
SOF's more extensive hardware CI. Take out the test and do it
always, it's like nine instructions.
+ The host/loader-side behavior is a mix of 1.5 and 2.5. It won't
actually start the secondary cores under host command, but it does
need to see bits set for them in ADSPCS for the DSP-initiated
power-up to work (2.5 would just ignore all but core 0's bits).
+ Also, like 1.5, it needs the host DMA stream to be explicitly
stopped (and not just reset) or else further loads will be unstable.
Note that the loader changes now require more logic than just "1.5 or
not", so the platform detection has been enhanced to fully categorize
the device based on PCI ID (not quite: we don't have any 2.0 platform
hardware, so I left that alone for now).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This configures soc and flash size definition
using DTSI information instead of hardcoded
values.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This modifies esp32c3 SOC configuration to support MCUBoot.
CmakeLists is moved from board to soc specific. It also
includes MCUBoot changes.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This change creates XiP image handling and proper
LMA and VMA regions configurations.
This also adds common-ram.ld and common-rom.ld sections that
require explicit handling due to image sections limitation
in esptool.
Move additional drivers into IRAM to protect against
flash cache disable read/write operation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
There's desire for a "log only" mode like the older adsplog script
had. Add a few other quality of life command line options too. And
catch the most obvious user errors to print a message instead of a
stack dump.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This is based closely on the older cavsload.sh script, but updated to
keep up with interesting new twister behavior, with a cleaner
interface for CI integration that doesn't require editing the file,
somewhat better internal documentation, and with a more focused eye on
use as a twister tool specifically.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The existing scripting for these platforms has gotten a little stale.
The loader had bifurcated into a v15 and v25 variant, both of which
lived in the cavs15 board directory. Building off Shao Ming's
excellent (if somewhat surprisingly committed) rework to unify
unchanged parts of the scripts, let's finish the job.
This adds a "cavstool.py" script with the following advantages:
+ It's just one script for everything, with a single unified load
process that works reliably on both 1.5 and 1.8+ hardware.
+ It runs on all cAVS platforms (with a compatible kernel, those
requirements haven't changed)
+ It automatically emitts logging synchronously after loading,
eliminating the race between adsplog.py and cavs-fw.py where you
could see logging from a previous test run.
+ It automatically detects and unloads a linux kernel module managing
the same device (even if SOF has renamed the module again, heh).
+ Timings have been tuned up in general, it's about 2 seconds faster
to get to first log output now.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Re-organize the SoC family/series/model configuration data so that:
* Board definitions can distinguish between the single-core (XC7ZxxxS)
and dual-core (XC7Zxxx) ARM Cortex-A9 models. Further descriptions
of on-chip resources, in particular relating to the programmable logic
capabilities if support of this functionality is to be implemented,
can be added at a later time.
* Separate SoC initialization code exists for the two series, so that
the init code of the XC7Zxxx series can consider SMP while the init
code of the single-core XC7ZxxxS series doesn't have to.
* Device drivers which don't have to distinguish between the single-
and double-core series of the SoC family can use a common configuration
item whenever the pre-processor is used to enable Zynq-7000-specific
code.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
1. Setup VDD_SOC with the appropriate setting
depending on the SoC
2. Do not configure PLL_SYS and PLL_USB. These
are already configured by the ROM code using
the DCD
3. Fix setting for USDHC clock
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Fix for issue #41012 to allow compiler to treat
IRQn_Type to be more than 8-bit. This will ensure NVIC numbers
more than 127 (required for MEC172x device) will work
correctly with irq_enable() API
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The MIPS Malta is an ATX form factor evaluation board made by MIPS
Technologies. Malta board is the most popular platform for MIPS
full-system emulation.
See https://www.linux-mips.org/wiki/MIPS_Malta for details.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Remy Luisant <remy@luisant.ca>
Add a module which is responsible for getting offset between RTCs
used for system clock on NET and APP cores. After getting an offset
between NET and APP clocks, it can be used for logging timestamping
on NET core to ensure that timestamping is in sync on both cores.
Synchronization is done using PPI, IPM task and events and RTC
capture feature.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
All options in Kconfig.soc are only for nrf53 series. Added file
wide guard instead of option specific options.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
This sets CONFIG_KERNEL_VM_SIZE to define the size of virtual
memory region which can be used by the TLB driver. The size is
derived from the actual SOF code where they say the TLB register
space is of size 0x1000. There are 2048 TLB entries (for 2 bytes
per entry), which translates to 8MB of virtual memory space with
4KB pages.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Enables basic power management for the RT11xx series SOCs. The following
power saving measures are currently implemented:
- system reduces core voltage during sleep
- core clock can be gated in deep sleep
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
GPC driver is used for power management operations on RT series SoCs.
Enable inclusion of the driver into the build.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Arm Cortex-M3 DesignStart FPGA-Xilinx edition doesn't have to use XIP.
Our board doesn't need it. Make it optional by replacing "select" with
"imply".
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Change the stm32_power_init to be executed PRE_KERNEL_1
for all the devices with the low power mode (power.c)
When GPIO and UART are not yet up and running.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
gPTP module clock is enabled for rt11xx. gPTP is not working correctly
on the RT10xx or RT11xx series, but this module clock needs to be
enabled
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The SAM spi driver depends on GPIO driver to work. It seems that this
dependency chain it is not handled. This select GPIO driver when SPI
driver is enabled. It rework GPIO and SPI Kconfig to select driver by
devicetree and drop entries at Kconfig.defconfig.series file.
Fixes#41525
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This configures soc and flash size definition
using DTSI information instead of hardcoded
values.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Introduce Pin Function Controller for Renesas R-Car family.
This first implementation support to set a given pin as gpio
or peripheral (GPSR), to set a peripheral function to a
pin (IPSR), to set pull-up, pull-down (PUEN, PUD).
In addition this driver allows to set driving capabilies(DRVCTRL).
Pins are identified thanks to the per SoC binding for
pin definition which also contains pin alternate function
parameters.
Some pins can also have driving capabilities, some have bias
capabilities.
In order to find the correct bias and drive registers pfc_r8a77951.c
describes the different registers.
Each SoCs or package will need to define getters
for these registers: pfc_rcar_get_bias_regs() and
pfc_rcar_get_drive_regs().
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
BBRAM content should be cleared when boot from cutoff. Compare magic
number to decide whether to clear entire BBRAM.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The Q variant is the same as non-Q, except the Q has SMPS built-in.
This symbol addition is to have the correct
SOC definition ("STM32H7A3XXQ")
Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
The newer sys_winstream utility is considerably simpler and much
faster for the reader. Use that instead.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
It's not uncommon to have Zephyr running in environments where it
shares a memory bus with a foreign/non-Zephyr system (both the older
Intel Quark and cAVS audio DSP systems share this property). In those
circumstances, it would be nice to have a utility that allows an
arbitrary-sized chunk of that memory to be used as a unidirectional
buffered byte stream without requiring complicated driver support.
sys_winstream is one such abstraction.
This code is lockless, it makes no synchronization demands of the OS
or hardware beyond memory ordering[1]. It implements a simple
file/socket-style read/write API. It produces small code and is high
performance (e.g. a read or write on Xtensa is about 60 cycles plus
one per byte copied). It's bidirectional, with no internal Zephyr
dependencies (allowing it to be easily ported to the foreign system).
And it's quite a bit simpler (especially for the reader) than the
older cAVS trace protocol it's designed to replace.
[1] Which means that right now it won't work reliably on arm64 until
we add a memory barrier framework to Zephyr! See notes in the code;
the locations for the barriers are present, but there's no utility to
call.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is no need to call soc_mp_init() if CONFIG_MP_NUM_CPUS
indicates only 1 CPU is being used. This also fixes an undefined
reference to soc_mp_init() since mp_cavs.c is not compiled
unless the build is targeting more than 1 CPU.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The reg_def.h was not self-contained: it uses DT API but doesn't
include <devicetree.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This is trick (mapping RAM twice so you can use alternate Region
Protection Option addresses to control cacheability) is something any
Xtensa hardware designer might productively choose to do. And as it
works really well, we should encourage that by making this a generic
architecture feature for Zephyr.
Now everything works by setting two kconfig values at the soc level
defining the cached and uncached regions. As long as these are
correct, you can then use the new arch_xtensa_un/cached_ptr() APIs to
convert between them and a ARCH_XTENSA_SET_RPO_TLB() macro that
provides much smaller initialization code (in C!) than the HAL
assembly macros. The conversion routines have been generalized to
support conversion between any two regions.
Note that full KERNEL_COHERENCE still requires support from the
platform linker script, that can't be made generic given the way
Zephyr does linkage.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Continue the previous work, moving the cAVS hardware dependencies into
a separate file, leaving soc_mp.c with only OS-generic details to
track.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Clean up soc_mp.c a bit. Put all cAVS register use in functions
dedicated to hardware details (e.g. "soc_start_core()"), leave the
Zephyr OS tracking (e.g. the CPU start record, the active cores array,
etc...) in generic code.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
So far board name was used as IDF target. This worked, as the only board
in tree that is based on 'esp32' SoC is actually 'esp32'.
Use CONFIG_SOC instead of CONFIG_BOARD, so that new boards based on
'esp32' SoC can be successfully introduced both downstream or upstream.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Many ARM SoCs included <devicetree.h> likely due to:
1. nvic.h not being self-contained
2. As a result of copy-paste
Some RISC-V SoCs had the same problem, in this case likely due to
copy-paste from ARM. The <devicetree.h> header has been removed using
the following command:
sed -i ':a;N;$!ba;s/#include <devicetree\.h>\n//g' soc/**/soc.h
soc.h files that make a legitimate usage of the API have not been
changed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The header was not self-contained: it uses DT and utility macros but
<devicetree.h> and <sys/util_macro.h> were not included.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The source file uses boolean types internally, however, <stdbool.h> was
not included. It was likely included indirectly before via
<devicetree.h> -> <sys/util.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Almost none of the soc_*.h headers were self-contained. This patch adds
all necessary includes to improve the situation.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The default I2C channel 3 is used by alternate function of GPIO H1/H2
Krabby uses GPIO F2/F3 as I2C channel 3, so we need to add the
compatibility of the GPIO F2/F3.
TEST=test on it8xxx2_evb:
zmake configure -b zephyr/projects/it8xxx2_evb/
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Enable CONFIG_RISCV_PMP in qemu virt soc. Use this SoC as CI testing
platform of RISC-V PMP and Userspace.
Signed-off-by: Jim Shu <cwshu@andestech.com>
NPCX7/9 has a different ADC register structure. NPCX7 has 3 threshold
detectors from offset 0x14 & has 10 input channels. NPCX9 has 6
threshold detectors from offset 0x60 & has 12 input channels.
This commit fixes the NPCX ADC register structure.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
This got broken during the cpu_init unification pass. I appear to
have copied that zero out of code that initialized Zephyr on a
uniprocessor config somewhere. But what it means is that any use of
the S32C1I instruction to store to any memory type will trap an
exception! And even when CONFIG_MP_NUM_CPUS==1, we will emit code to
do that in the atomics layer when SMP=y.
That configuration ("SMP" with 1 cpu) is actually exercised by some
tests, including important ones like timer_api. These got broken.
Fix.
Really it's never correct to have anything but 1:1:1 ("external RCW
transaction") on these CPUs. All Intel cAVS processors have hardware
atomics support. We owe it to all the code we'll run to make sure it
works as documented and doesn't explode.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
When running under a simulator, it's difficult to extract output from
the window (it's difficult with hardware too!). Add "SIMCALL" output
to stderr (it's literally just 3 extra instructions) as an optional
feature so this subsystem itself can be debugged without herculean
effort.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Reword the symbols to make it clear what they mean ("INIT_LPSRAM"
instead of "RESET_MHE_AT_BOOT") and use them correctly instead of
SOC_SERIES_* kconfigs.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
We don't define a MemoryException handler, nor is one appropriate for
this hardware as it stands. And the empty section keeps causing
linker warnings we have to work around. Remove.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Single-core instantiations of this hardware and single-core builds of
firmware still exist, so we should support that without needless
bloat.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The MP startup code had a hardcoded INTLEVEL field of 5 in the initial
value of PS. That's needless, INTLEVEL is a full 4 bit field even if
the number of hardware interrupt levels is lower (and in fact 0xf is
the documented hardware reset state). Set that instead, so that this
code will work with any XEA2 hardware. This also matches the similar
code path in boot startup.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Most of soc.c is actually interrupt handling glue for the intc_cavs
driver. Give it its own file so that SOC initialization and bringup
can live separately.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
XCHAL_HAVE_ICACHE_DYN_ENABLE is not set for any Intel cAVS
hardware, so MEMCTL configuration is not done properly leaving
icache disabled. This can be seen as ~10X slowness when running
code on non-primary cores. Fix the issue by using XCHAL_USE_MEMCTL
to check for MEMCTL usage.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Set TF-M option for nordic HAL library path to use the included
nordic HAL instead of the version that TF-M downloads.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
If there are no console messages input at an interval of 15
seconds, the system will be able to enter suspend mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Copy/paste/diverge struck again; I should have known better.
Fixes very recent and incomplete commit 9a1c5ec78e ("soc/intel_adsp:
cavs-link.ld: add *(.trace_ctx) sections"), see that commit for details.
Part of the fix for thesofproject/sof/issues/5032
This commit does not change `soc/xtensa/sample_controller/linker.ld`
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Having DWT-based NULL-pointer detection enabled by default trips a lot
of users since it will make any debugging fail when enabled. Disable it
by default and let users enable it if they desire to.
Fixes#39216.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Change the settings to support pinctrl on the GD32VF103.
- Split soc/arm/gigadevice/common/pinctrl_soc.h
and put it into include/dt-bindings.
- Leave some definitions that can't handle with device tree compiler
in pinctrl_soc.h.
- Remove dependency to SOC_FAMILY_GD32 because always enabled it
if GD32_HAS_AF(IO)_PINMAX was selected.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
GD32V processor core is used non-standard bitmask
for mcause register. Add option to configure the bitmask
to support GD32V.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
In this commit, the driver sets the PM constraint to prevent the system
from entering the suspend state for a CONFIG_UART_CONSOLE_INPUT_EXPIRED
period when data come in. The constraint releases after the
CONFIG_UART_CONSOLE_INPUT_EXPIRED time expires, .
With this change, the PM policy doesn't have to check the timestamp
by calling npcx_power_console_is_in_use() explictly. So the related
npcx_power_console_is_in_use*() functions can be removed.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Select configuration when mcuboot is enabled.
At this moment, only UNSIGNED image is supported as per
Espressif's mcuboot porting.
This also updates esp32 runner to use proper bin_file name
and updates default bootloader check.
Move CMakeLists.txt content from board to soc directory
as this support is for esp32 architecture and not board
specific.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Booting ESP32 without 2nd stage bootloader is not supported.
Hence, ifdefs in startup code are removed
Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
By enabling SMP option plus the APPCPU, also
completes the SMP port by adding the esp32
specific arch_sched_ipi() function
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
RT11xx can peripheral had incorrect clocking configuration in SOC clock
init code and DTS. Fix peripheral configuration.
Fixes#41251
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The CAVS linker scripts in Zephyr and "plain" (XTOS) SOF seem to share
the same origin and they mostly duplicate each other so they naturally
keep diverging from each other. This commit catches up with the SOF
commit ef43899c580f (thesofproject/sof/pull/2996) which added
the *(.trace_ctx) sections as part of the runtime log filtering
implementation (feature request thesofproject/sof/issues/2172)
Paraphrasing that commit, the goal is to create at link time a C-like
array by regrouping scattered trace contexts so they can be iterated on.
Together with some other changes in SOF, these 3 additional lines are
enough change in Zephyr to fix SOF bug thesofproject/sof/issues/5032
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
The fix for xcc build failures yesterday forgot to preserve the
squashing of stderr from the objcopy steps. As mentioned in the
comments, there are deliberate empty sections in this link that
binutils warns about, but which are actually required, Cadence has
some vector sections in their standard exception table that don't get
populated and rimage has non-code sections that may be left empty for
non-audio-driver applications like tests.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add board support for NXP i.MX8M Plus EVK. This board has the following
features:
Processor : i.MX8M Plus Quad applications processor
Memory : 32-bit LPDDR4 w/6 GB
eMMC 5.0/5.1 w/32 GB
SD/MMC connector
QSPI w/32 MB
Connectivity : MIMO 2x2 Wi-Fi 802.11b/g/n/ac and BT 4.2
2x Ethernet (1x w/ TSN)
PCIe M.2
2x CAN FD DB9 Female connectors
USB : USB 3.0 Type C for Power
USB 3.0 Type A
USB 3.0 Type C
Debug : JTAG connector
MicroUSB for debug console
More information about this board can be found in NXP website: https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK
Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
Recent linker changes got ahead of the toolchain and started using
features not available in the binutils 2.23-based Xtensa toolchain.
Specifically:
+ The section arguments to objcopy don't accept wildcards.
+ It's not legal to have an ALLOC section emitted to a region outside
a declared MEMORY space. So various non-mapped sections populated
by C structs have to be put somewhere with an explicit address.
+ The older linker won't automatically create an empty section just
because you assigned to ".", so the Zephyr tests that lack a
.fw_metadata section get rejected by rimage. The fix here is a
little clumsy: copy the section out of zephyr.elf into a
(potentially-zero-length) temporary file, then add it back to
main.mod as a final step.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The module copy was clearing BSS sections from the module list, but we
already clear the full memory space immediately after SRAM power-up so
that's needless, just like the legacy reset vector bss clear that got
removed earlier. (Yes: that means that this code used to be writing
zeros to .bss three times!)
Similarly, put a symmetric clear on the LP-SRAM bank for safety (it's
not currently used by Zephyr but we do start it up). And move the
cache flush to the end of initialization immediately before OS
handoff.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Both soc.h and adsp/cache.h were very small headers, there's no good
reason to have a separate header just for two one-line inlines.
Merge.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This is some SOF code that got imported into Zephyr. But it's not a
Zephyr API and Zephyr doesn't use it. Unfortunately, the Zephyr
definition is now the one actually used at runtime in SOF, so we can't
remove it.
Put a guard around the definition so nothing else uses it until we get
it moved back home.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Dead code. Unused in Zephyr. Seems like SOF is picking this up from
its own headers via reading CONFIG_MP_NUM_CPUS correctly.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Syntax beautification and general simplification pass:
+ Remove some spurious padding around the _data_end symbol. That's a
Zephyr symbol and should reflect the actual end of the data section in
bytes.
+ Squash a warning that crept in where the linker doesn't like
changing cache mapping and padding at one time, clarify in docs.
+ Use the pre-existing-but-heretofore-unknown-to-me Zephyr
debug-sections.ld include file instead of putting all the DWARF
sections in by hand.
+ Move the .xt* sections to explicit zero addresses, since that's what
debug-sections.ld does for its output and if I don't they'll end up
with funny values.
+ Use Zephyr brace-on-same-line style consistently
+ Remove cargo-cult noop patterns like ALIGN(4) and ABSOLUTE(.) (none
of these sections get furthur relocated!)
+ Clean up the SEGSTART_* API so that it doesn't need to have
CONFIG_KERNEL_COHERENCE guards.
+ Remove a few unused/legacy symbol exports ("end", "__stack") so as
not to pollute the namespace.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This header is now included in only one place, and just contains a
handful of very-bootloader-specific platform tunables that will never
be exported elsewhere. Move that code into the C file. Longer term
we should configure the memory controllers with devicetree as much as
practical, but there's no reason to keep this header around.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Lots of changes to the linkage, none major:
+ Remove all the manually-defined ELF program headers. This was a big
pain to maintain, and I finally figured out why we were doing this:
it turns out to have been a workaround for the flags issue below.
+ Suppress the "empty loadable section" warnings at module generation.
This turns out to be an objcopy issue, when you drop all the
sections from an ELF program header.
+ Set section flags for NOLOAD sections manually. Rimage is very
strict about flags (even to the point of trying to suck in its own
metadata section as program text). This turns out to be really
fragile, as the linker automatically sets flags on the output
section based on the symbols placed in it. Rather than needing to
have one program header per section, or playing games in the
assembly for section definition to make this all match, just set the
flags expressly on the sections we know about on the objcopy command
line.
+ Similarly drop the special memory regions with explicit faked
"physical" addresses that were being used for non-loadable sections
(e.g. .fw_metadata, .static_log_entries). Just link them all after
the rest of the image like other platforms do.
+ Clean up multiple levels of macro indirection for the manifest base
address, which is ultimately coming from kconfig. Now the magic
numbers don't seem so magic.
+ Remove legacy symbol exports for "cacheattr" that we don't use
anymore.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There was a ". = ALIGN(4096);" sitting at the end of the .text section
in the linker. This had the effect of needlessly padding the size of
the segment as packed into and copied out of the firmware DMA image.
There's no value to storing unused bytes in the image. It also makes
analysis easier for changes the modify code size. The following
.rodata section was already being 4k aligned anyway.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The bootloader had always been doing setup for window 0 (the firmware
status word reported to the loader). This then got needlessly
repeated in the main OS startup. Drop that, and move window 3 setup
(the trace/printk output buffer) there too for symmetry.
This means that the clear and cache flush of the buffer can be handled
in only one place too, for some runtime win (before it was being
cleared/flushed once at SRAM initialization time and then again at
window setup).
And as that was the only task remaining in the "adsp.c" file, we can
just remove it entirely.
One nice side effect is that this pushes up the point where we can get
a successful printk() out all the way back into the later stages of
the bootloader.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Now that we have access to IMR memory for non-bootloader tasks, let's
pick the low hanging fruit. SOC code that is only used at
initialization time (or things like core halt/restart which happen
only in non-realtime contexts) are now flagged __imr.
This is good for 808 bytes of code moved out of the main Zephyr image
on cavs_v25.
In the medium term, it would be good to define a system define for
this purpose (a-la Linux __init/__initdata) and start moving core
Zephyr init code too.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The Zephyr symbols are now part of the same link as the bootloader, so
no need to have an assembly entry stub or fixed address at all. Just
call z_cstart() as a normally-relocated function. Interestingly
Zephyr never put a declaration for it in public headers, because this
appears to be the first platform calling it from C.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Now that the IMR boot code is built as part of the main Zephyr
executable, remove the old stuff and its directory. The C file
becomes "boot.c" in the common directory and the two
bootloader-specific headers move into common/include.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The presence of a separate build for the bootloader code has always
been a wart with this platform. Sharing of code between the two has
required great care. We've had bugs with mismatched include paths,
macro definitions and compiler flags, etc... And of course it's not
possible for one to see the other; in theory we'd like the ability to
call back into IMR code after startup, to use the space for temporary
storage, etc...
So let's finally do it. This really isn't that complicated when you
see it in isolation:
+ Move the module manifest metadata into an "rimage_modules.c", and
put them in their own NOLOAD section where we can grab them later
with objcopy.
+ Make a new "imr" memory region in the main linker and just paste the
bootloader linkage (which is now using its own specific sections) in
there.
+ After zephyr.elf is built and cache-remapped, we can extract the imr
sections and the appropriate manifest for the bootloader rimage
module, and then do the converse by excluding them for the main
image module.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Define an __imr attribute macro that allows the bootloader to
expressly specify symbosls to go into IMR memory, use it pervasively
in the bootloader code, and remove the traditional section names from
boot_ldr.x.
This doesn't do anything by itself, but it is a necessary step for
getting the bootloader and Zephyr code to live together in the same
link.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Startup on these devices was sort of a mess, with multiple variants of
Xtensa and platform initialization code from multiple ancestries being
invoked at different places for different purposes. Just use one code
path for everyone.
Bootloader entry starts with a minimal assembly stub that simply sets
WINDOW{START,BASE}, PS and a stack pointer and then jumps to C code.
That then uses the cpu_early_init() implementation from cAVS 2.5's
secondary cores to finish Xtensa initialization, and then flows
directly into the pre-existing bootloader C code to initialize cache
and memory and copy the HP-SRAM image, then it invokes Zephyr via a
simple C function call to z_cstart().
Likewise, remove the "reset vector" from Zephyr. This was never a
reset vector, reset on these devices goes to a fixed address in a ROM.
CPU initialization is handled explicitly and completely in the
bootloader now, in a way that can be unified between the main and
secondary cores. Entry from the bootloader now goes directly into
z_cstart() via a C call (via a single jump instruction placed at the
entry point address -- that's going away soon too once we're using a
unified link).
Now that vector table initialization happens in a uniform way, there's
no need to copy the VECBASE value during arch_start_cpu().
Finally note that this also reverts the
CONFIG_RESET_VECTOR_IN_BOOTLOADER kconfig variable added for these
platforms, because it's no longer a tunable and true always.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Remove an unused strcmp() implementation. Flatten the call tree for
HP-SRAM initialization for clarity. Better isolate the platform
dependencies so e.g. hp_sram_pm_banks() becomes a clean noop on 1.5.
Also removes some dead/vestigial "error" handling, which wasn't being
propagated anywhere. Note that error detection and handling is a bad
idea, but this is VERY early code. We don't have even a theoretical
way of getting information back to the host until after SRAM is
initialized and window zero is set up. (And even then there's no
protocol available other than signaling "FW_ENTERED" or... not).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Our "TLB"[1] initialization on secondary cores for cAVS 2.5 was
forgetting to initialize instruction caching, leading to a performance
regression. Clean this up and augment so that it matches the (larger,
non-C-callable) HAL implementation.
This will also allow us to use the same code on the main core in
upcoming changes.
[1] It's not a TLB, it just uses the TLB management instructions
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This seems to be a mistake in rimage: it wants the text and data
segments of the output module to be page-aligned, but it assumes
.rodata is part of "data" and not "text". So this reorders the
segments to make that happen.
Note that the page alignment is entirely artificial. Nothing is
interpreting the segment boundaries rimage is enforcing except for the
code in the bootloader itself, which doesn't care.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There was some vestigial handling here for Sue Creek (which this code
has never supported, that's a different board in Zephyr) and some code
that apparently managed a bug workaround in the ancestral SOF code.
Neither was buildable. Remove.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Move the very-early core initialization hooks (which are a mix of
Xtensa architectural features and Intel-specific hardwareisms) into a
separate header so they can be shared between the bootloader, main
core, and MP cores.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Adds Xtensa as supported architecture for coredump. Fixes
a few typos in documentation, Kconfig and a C file. Dumps
minimal set of registers shown by 'info registers' in GDB
for the sample_controller and ESP32 SOCs. Updates tests.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
USDHC driver build failure fix for mimxrt685_evk, dat3 pull function was
not defined at the SOC level.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds support for using GPT as the hardware timer source (as opposed to
systick) for all RT1xxx platforms. This requires moving the clock
frequency of these devices into a defconfig so it can be overridden by
the GPT clock frequency.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This enables the GPT timer for use as a hardware clock on the
MIMXRT1064. The timer will be disabled when builds use the GPT timer as
a counter, and the build will fall back to using the Cortex M systick as
a timer. This was tested using the kernel tickless test, to verify the
driver functions as expected.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added a driver to enable the GPT timer on RT1xxx parts to be used
instead of systick as a clock source. The timer is set to run in reset
mode, and uses the low frequency 32kHz oscillator for power savings
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This reverts commit af79664da3.
The patch caused regression on TGL-H systems where only 2 DSP
cores are available. The Kconfig override used by existing SOF
application does not work with Zephyr. A quick fix using
Zephyr board revisions was considered, but review feedback
was that core count difference should be reflected in SoC-level
device tree. This will take more time to develop, so the revert
is needed to fix the immediate regression.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Enable flexspi for RT11xx SOCs. This requires selecting the correct
KConfig symbol for the cortex m4 and m7 SOCs, as well as correcting an
error in the flexspi DTS node and updating the clock init for RT11xx
SOCs.
Note that in addition, the NXP hal must be updated to properly support
including the cache management driver for the Cortex M4.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
As memory region names are now derived purely from devicetree, remove
the `name` parameter from `DT_REGION_FROM_NODE_STATUS_OKAY`. Name is
`zephyr,linker-region` if it exists, otherwise the node path.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
QEMU doesn't currently support MVE until the QEMU 6.2 release is out.
So for now only enable MVE support if we are NOT targetting QEMU.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
STM32H7 has different power supply modes but now Zephyr supports just LDO
and direct SMPS. This commit introduses POWER_SUPPLY_CHOICE configuration
parameter and add support for missed power supply modes.
Signed-off-by: Gennady Kovalev <gik@bigur.com>
Fixes#40730.
Add driver for MEC172x QMSPI with local DMA(LDMA). The driver
support SPI asynchronous operation.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
RT11xx clock init code was not handling difference between RT1160 and
RT1170 Bus_Lpsr clock correctly. Fix this.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
the RT685 contains an additional flexcomm peripheral, that supports
only I2C. This commit adds this peripheral to the device tree,
and enables pins and clocks for flexcomm15.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
There is some legacy code that tries to mask IDC interrupts when
starting up cores. This is there because the IDC interrupt is both
the system IPI when Zephyr is running (and can thus be signaled
asynchronously to the code calling arch_start_cpu()) and the messaging
protocol to the boot ROM on the other CPU. So the idea is that we
mask interrupts after startup so nothing is confused.
But that's needless in the current architecture. We maintain a
synchronized cpus_active[] record that will show true/active for any
CPU between the end of its SMP startup sequence and the beginning of
the shutdown process in soc_halt_cpu(), and false at all other times.
An IPI will never be sent to a CPU that is running in the boot ROM,
because such a CPU will be flagged as inactive. Likewise a ROM
startup IDC will never be sent to a CPU running Zephyr code for the
converse reason. Remove all that code.
Unfortunately SOF itself still needs an interrupt unmask step at CPU
startup, because it's still doing its own masking (probably according
to the same algorithm that we imported). Leave that in place as a
minimal workaround until we get that fixed upstream.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Investigation by Kai Vehmanen has shown that there is a very short
delay needed before starting the secondary core on cAVS 1.5 hardware.
What we finally realized is happening is that on these devices,
secondary core power is managed by the host. The cavs-fw.py test
integration powers the second core on at system startup and lets
Zephyr start it later, but SOF will power it up and send an IPC to the
firmware immediately.
There is a period after power-up but before the ROM is available
(unclear whether this is a race vs. hardware, the ROM firmware, or the
kernel driver, or potentially some combination); interrupts latched
earlier than that seem to be cleared by CPU initialization.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These registers were defined in the new interface, but still being
used with bare bits (and in one spot a legacy field access macro).
Clean things up and use macros pervasively. To be fair: in this
particular case the field names aren't particularly descriptive...
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The usage of this interface is correct, but the docs in the header
spoonerized the source and destination of masking in the INTCTL
registers. Oops.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Put the initial stack in (slow) IMR memory instead of HP-SRAM. Very
little happens on this stack anyway before Zephyr switches off to the
interrupt stack and/or main thread. And this will allow us to start
running stackful C code much earlier in the boot process.
This puts the stack into the region of memory immediately below the
IMR image (because that edge of the image is easier to detect in
code). On all current platforms, that's offset quite a bit into IMR
space and leaves plenty of room. But we should have some kind
architectural way to reserve this space...
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The memory layout for the boot loader was needlessly complicated, with
separate fixed regions defined at fixed addresses, all in a file that
needs to be contiguous and DMA'd from the host in a single block. The
end result was a lot of magic numbers and wasted space.
Clean things up so that it links in a single region expressed (for the
benefit of rimage, I think) as a single program header in the ELF
file.
This is in preparation for further changes to unify the bootloader
stage with the main Zephyr image in a single link.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This board, whose hardware is just a cAVS 1.8 device without an x86
host CPU, started life (as all the cAVS devices did) as a
cut-and-pasted copy of the same basic code.
Because of hardware and schedule limitations, it didn't get the same
unification treatment that all the other platforms did. But it turns
out that in SMP configurations (which... it's not clear if we actually
test on hardware?) it wants to use the cavs_timer driver, which now
uses the new SOC API and not the old one. Which s1000 doesn't expose.
So... I guess we have to continue to cut and paste until we can find
time to unify this. Add a copy of the new shim/IDC headers to this
SOC and expose them via devivcetree.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Adds a driver using the SNVS high power and optionally low power
RTC instances. A device specific function `mcux_snvs_rtc_set` is
provided to update the current counter value.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
RT11xx SOC definitions did not enable USDHC controller. Select Kconfig
symbols required to enable it.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
A Cortex-M specific function (sys_clock_isr()) was defined as a weak
function, so in practice it was always available when system clock was
enabled, even if no Cortex-M systick was available. This patch
introduces an auxiliary Kconfig option that, when selected, the ISR
function gets installed. External SysTick drivers can also make use of
this function, thus achieving the same functionality offered today but
in a cleaner way.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
data cache mode setup and enabling should be done only when
CONFIG_ESP_SPIRAM is enabled. Otherwise, memory layout will
conflict with defaults.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
The default config for cavs25 should be a 4 core config. Variants that
have less cores, need to override the config option to a smaller value.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
ARC_HAS_ACCL_REGS should set to y to protect ACCL and ACCH registers
during irq. These registers could be used as GPRs by compilers and
therefore need store/restore during irq.
Signed-off-by: Yuguo Zou <yuguo.zou@synopsys.com>
The device PM callback needs to be used only to suspend/resume devices.
If the system cannot be suspended because UART is in a particular
state, the pm_constraint_set/release API should be used. For NPCX UART,
the chip can't enter low power idle state until UART completes the data
transmission.
This commit changes NPCX UART to use pm_constraint_set/release & fixes
UART lost data from low power idle.
Fix#40621
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This adds the SoC specific bits to enable GDB stub,
mainly the description for the register file, and
memory regions.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
RT600 uses the mcux flexspi driver, which can produce RWW hazards when
calling code linked into flash (such as the logging subsystem). Disable
logging in flexspi driver by default for RT600 series.
Fixes#40744
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit adds support for IMX6SX PWM.
The PWM module is the same module present on the IMX7D and so dts
bindings has been renamed following the one present on linux.
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
Some PM cases were not handled correctly (missing default statement).
The error was caught by CI while doing other PM related work.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Since the addition of pinctrl the common folder is added to the Zephyr
include path. This can be re-used to place the soc_nrf_common.h header
in the common folder and include it directly, without the need of
relative paths.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add initial support for nRF pin controller driver. The implementation in
this patch does not yet support any peripheral. Only states
representation and basic driver functionality is introduced.
Note:
The nrf_pin_configure function has been marked as __unused since it may
not be used in certain scenarios until all peripherals are supported by
the pinctrl driver. For example, if only UART/E is supported but the
board does not enable UART, the function will never get called. However,
that board will likely have other peripherals that will gain support in
the future.
Thanks to Marti Bolivar for bindings documentation.
Co-authored-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add initial version for STM32 pinctrl driver. Driver has been written
re-using many of the already existing parts in
drivers/pinmux/pinmux_stm32.c.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The IDC driver was written for Tiger Lake era devices, but works fine
on the earlier hardware too. Make it selectable; if you don't
configure IPM_CAVS_IDC, then you get the new driver.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There was an attempt in the old code to express this as a formal
protocol with a proper field definitions, etc... But in fact no such
protocol really exists. This scheme is only used in one place to send
one specific message to code fixed in ROM on legacy devices that only
knows how to recognize this specific value. And 2.5 and later
hardware are moving away from it anyway.
Just express it directly, and explain in comments.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The CAVS_IDC_IPM driver happens to be used only on non-2.5 hardware,
but it's best to be clear in the conditional compilation when we're
talking about hardware-dependencies and when we mean software
configuration. This was mixed up in a few spots.
Also fix a warning that creeps in on non-default drivers choices about
an undeclared ipm function.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
While the linker scripts for these platforms had diverged in form, the
behavior remained compatible. Link all cAVS devices with the same
linker script included from the common directory (it's a verbatim copy
of the cavs_v25 script).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
While technically this file can change for any instantiation of Xtensa
hardware, in practice all these devices have identical interrupts
setups. These files were duplicates, so there's no value in keeping
them in per-sub-soc directories. (Really we should wire it up so that
the generator gets run automatically with the build, but that will
need to wait for a rework of interrupt entry).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
All the in-use contents of these files have now been moved to the
intel_adsp core, and they are configured via devicetree and kconfig.
Remove the legacy headers.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These two register blocks are defined in the platform layers, but
never change (except on 1.5 where they don't exist). I don't want to
write a full devicetree interface for them as I can't find good docs
currently. They are used only at system initialization, so move the
definitions to the single file where they're used. In the longer term
we will want to move at least the GPDMA setup into a driver anyway.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These registers were hardwired in the platform layer. Move to
devicetree, via a struct interface that looks like the pre-existing
shim layer.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These values (used to arrange the bootloader within IMR memory) are
mostly computed or fixed to values that don't chagne between
platforms. Only the manifest address and the location of the data
section change. Put those in kconfig, move the rest to the global
header.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The bootloader code on this SOC has its own cmake rules, which means
it doesn't get the Zephyr-specific magic from the toolchain layer and
the code needs to handle fixups manually. (Specifically: we have a
xcc_missing_defs.h header to provide gcc symbols that xcc doesn't
have, and assembly needs to be built with _ASMLANGUAGE so headers
don't include C syntax.)
Long term the right solution here is to build the bootloader as part
of the Zephyr binary.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The locations of the memory windows within the reserved SRAM region
was being construted via a bunch of magic numbers referencing
(potentially historical?) SOF usage of those areas. But Zephyr only
ever touches two of these windows, and only cares about the sizes and
offsets. The complexity was hurting and not helping (especially since
there was no attempt made to unify these values with the ones that are
actually live in the SOF tree).
Replace with kconfig variables that simply specify the offset. Only
one platform has a nonstandard layout anyway. That allows SOF to move
things around in a clean way if it wants. Ideally we should be
presenting a proper API for managing this region, though.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Same as for the HP-SRAM memory region. It's already exposed in
devicetree, so take the per-platform values out (including some dead
code on 2.5) and put them in a global header.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The platform layer (except cAVS 1.5, which computed it via alternate
means as an offset on other stuff) was specifying the entry point as
an explicit address needlessly. In fact the linker scripts already
are written to place the entry point at the first address of linkable
RAM, which is already available as the RAM_BASE symbol.
Unify.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These registers are identical on all platforms, the only difference
being that cAVS 1.5 places them at a different address.
Create a devicetree node to track the register block, and replace the
platform header code with a global API defined once (it works like the
pre-existing shim struct).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There is a diverged definition for SRAM_REG_FW_END, which exists to
prevent the Zephyr window initialization from changing values that
were already set by the ROM or bootloader (though this is incomplete,
as we're not ensuring the memory is actually the same space except by
convention; we also don't have any Zephyr-side visibility as to the
content of this struct).
That was silly; the only thing worse than one magic number is four
magic numbers in different files. Write a formula that works for all
the platforms and put it in the C file where it's used.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There was a divergent set of definitions for a "RAM" region for the
benefit of memory layout in the platform headers. In fact there was
only one platform dependence (cAVS 1.5 has 32k instead of 64k
reserved). Put that into kconfig in a single place, and add a warning
that this is a trap region with hidden dependencies in both Zephyr and
SOF. Good enough until we clean this up and make everything visible
to the linker.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There are multiple "fake" (not part of image) sections needless linked
to explicit addresses right now. This should be cleaned up, but in
the meantime let's at least put their definitions all in one place so
they aren't cut/pasted into every platform.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These macros (LPSRAM_MASK, SRAM_BANK_SIZE, HOST_PAGE_SIZE) never
change, and are always used in just one file.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The HP SRAM block address and size is specified in four different ways
(devicetree, "SRAM_*", "HP_SRAM_*" and "L2_SRAM_*" macros). Unify,
moving the C definition (which just fetches it from dts) to a single
header and out of the platform layer.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This was an abstraction layer without a purpose. All existing
platforms have the same (LXn core) layout. When we need to split this
out in the future, the right thing will be to use the values already
provided by the platform core-isa.h and not duplicate them anyway.
Think of this as a first step to an incoming rework of the Zephyr
Xtensa interrupt entry generation, which is long overdue.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The generic bootloader code used a per-device "platform.h" file
imported from SOF. These turn out to have very little actual content.
Move them to the core directory in a single header for now, pending
some rework to place the settings in devicetree.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The linker script (and a little bit of SOF) still has support for an
older mechanism for bootstrapping secondary cores by copying code into
lp-sram from a "manifest" emitted by the linker. This actually never
worked in Zephyr, and we've implemented a different scheme that uses a
small runtime-copied trampoline instead.
Remove.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Each platform was defining its own shim.h header, with slightly
variant field definitions, for a register block that is almost
completely compatible between versions. This is made worse by the
fact that these represent an API imported fairly early from SOF, the
upstream version of which has since diverged.
Move the existing shim struct into a header ("cavs-shim.h") of its
own, remove a bunch of unused symbols, fill in definitions for some
registers that were left out, correct naming to match the hardware
docs in a few places, make sure all hardware dependencies are source
from devicetree only, and modify existing usage to use the new API
exclusively.
Interestingly this leaves the older shim.h header in place, as it
turns out to contain definitions for a bunch of things that were never
part of the shim register block. Those will be unified in separate
patches.
Finally: note that the existing IPM_CAVS_IDC driver (soon to be
removed from all the intel_adsp soc's) is still using the old API, so
redeclare the minimal subset that it needs for the benefit of the
platforms in transition.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Reorganize the initialization code to cleanly separate the platforms
and clarify which code is common. The #if'ery was sort of a mess.
This is in preparation for an incoming patch that unifies the shim
register definitions across platform variants.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Misc cleanup, no non-trivial logic changes.
Swap in new ("rsr <reg>, REGISTER_NAME") syntax for Xtensa SR's in
place of inconsistent usage of the older one ("rsr.REGISTER_NAME
<reg>").
Remove the legacy handling of !KERNEL_COHERENCE cases for allocating
the cpu start record. That has long been a requirement of
multiprocessor code on this platform.
Remove the synchronous testing of the "alive" flag in
arch_start_cpu(). Nothign about that API is intended to be
synchronous, and in fact the Zephyr SMP layer is already doing the
same trick.
Remove some vestigial dead code at the end of z_mp_entry(). It was
apparently intended to handle the case where a CPU function returned,
but that's not legal anyway. And it was only enabled in the case
where there was only one CPU anyway, which was an impossible situation
(you can't evercall arch_start_cpu() successfully on a system with
only one core, for obvious reasons -- the only core is already
running!). Replace with an assertion.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The cAVS bootloader code (for... somewhat silly reasons) doesn't build
via the same paths as regular Zephyr object files, so it wasn't
getting the _ASMLANGUAGE define. That meant that Zephyr headers
defining BIT() were using syntax incompatible with some assemblers
(specifically the Cadence xcc assembly; current gas versions were
fine).
Not 100% sure this is the best spot to put this, but the root fix is
to get the bootloader building into the same link as the rest of
Zephyr anyway.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Program flow will behave incorrectly (memory and instruction fetches
return invalid data) if Flexspi is accessed by the Flexspi driver while
being used as XIP memory by the Cortex M7.
Set logging to disabled by when XIP mode is used in the memc and
flexspi drivers, and warn the user if they attempt to enable it.
Fixes#40133
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable pinctrl by default, since it is an essential component on almost
every firmware. Inclusion of series defconfig has also been guarded with
SoC availability (was missing).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a pin control driver for GD32 SoCs using the AFIO model.
Thanks to Gerson Fernando Budke for testing and implementation
suggestions.
Co-authored-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
- refactors cache initialization functions by moving it from
soc.c and placing it in soc_cache.c
- moves SPIRAM's bss zeroing before SPIRAM initialization
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Despite the "F4" prefix, GD32F403 is an SoC with significant differences
compared to other F4 MCUs:
- It has a completely different HAL
- It has significant hardware differences, for example, the pinctrl
mechanism uses AFIO (all others use AF)
The grouping principles applied to other similar vendors such as ST
can't be applied for GD32 due to these reasons, so the approach taken
here is to define series based on the used HAL. A different HAL likely
means that there are significant hardware differences between, e.g. F403
and F405. The vendor likely chose a confusing naming scheme, but we need
to deal with it.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The Flexspi memory address defines the location of the externally
attached flash to the MXRT600 based board. The flexspi has two
different memory spaces for secure and non-secure access that are
not aligned for the Flexspi register space and the memory map
address space. The normal method of handling this via the two
different dts files for secure/non-secure is not able to handle
this because a base address is applied uniformly across multiple
reg items.
Changes include:
- pull flexspi out of peripherals block to allow it to be explicitly
expressed in the respective secure/non-secure SOC DTS files.
- move the flash size definition to the board level definition and
use the size of the actual flash device found on the board.
:
Signed-off-by: David Leach <david.leach@nxp.com>
Use SMPS power supply only if enabled.
The default power supply configuration for the
NUCLEO board with -Q subfix is SMPS,
so it's essential to match with hardware configuration
to avoid deadlocks due to mismatch.
if a custom board with LDO configuration is in use,
then no need to enable `CONFIG_POWER_SUPPLY_SMPS`
Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
IT8XXX2 uses shared ns16550.c driver which does not provide a power
management callback(pm_action_cb), so create driver to handle
IT8XXX2 specific UART features.
note: pm_action_cb(old name: pm_control_fn)
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Applying similar changes to cavs_v20 as in commit
8bc4539cec:
Older binutils, like the (nine-year-old!) 2.23 version that powers
many Cadence XCC toolchains, happen not to support the "~" operator to
perform bitwise negation. And they generate an absolutely hilarious
series of inscrutable error messages when they try to tell you this
fairly simple fact.
Just fold it into the constant.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This reverts commit 3cc14b2c2b.
Revert this due to the same reason as commit
a29b66bbf5:
Unfortunately this mechanism doesn't seem to actually work on the SDK
linker. The emitted sections, when passed a symbol name as the "start
address" just appear wherever the "." variable was pointing (in this
case, into the cached region). That breaks the kernel coherence
layer, obviously.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Updates to MEC172x eSPI driver to support ACPI shared
memory region and EC Host Command Subsystem through
ACPI_EC1 and Embedded Memory Interface (EMI).
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add Kconfig items that can be used to query if the current SoC
support the HW peripherals for some peripherals that are missing.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Provide some factorization in pm_power_state_set procedure
to prepare shutdown case introduction.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The mismatch between the slot number and the sequence ("id") made me
suspect a bug for too long. Fix one related comment and add two more. No
code change.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Use i2c_hal functions to enable support for
multiple SoCs.
Use DT compat to enable I2C from device
tree configuration
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This joins all clock control handling to same source
by using hal clock functions. It also brings ESP32C3
clock support.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add baseline support for mimxrt1160_evk Cortex M4 and M7 cores
UART shell, synchronization, and hello world have all been verified to
build and run correctly.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The FIU/UMA module in the NPCX chip provides an dedicated SPI interface
to access the SPI flash. This commit adds the driver support for it.
With this commit, the application can call the flash APIs
(via spi_nor.c) to access the internal flash of NPCX EC chips.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I32bbf09f6e014b728ff8e4692e48151ae759e188
Add the power state of deep doze. When system enters deep doze, the
clock of CPU and EC can be stopped to reduce power consumption. And
enable the UART Rx WUI before entering deep doze to wake up EC and
CPU.
Tested on it8xxx2_evb board. It will reduce 5.25mA when system enters
deep doze mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit removes usage of Xen emulated PL011 SBSA UART in favor of
Xen PV console minimal implementation. Now boot log and application
output can be directly taken from hypervisor domain console, instead of
virtual UART.
Also Xen VM doc was updated according to these changes.
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
Add SoC-specific code, the basic device tree and Kconfig data as well
as the corresponding linker command file for the Xilinx Zynq-7000
family of SoCs. This SoC - either as a QEMU simulation or on actual
hardware such as the Avnet/Digilent ZedBoard - is suitable as an ini-
tial target for the ARMv7 Cortex-A support.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
MEC172x eSPI driver, eSPI pin programming, interrupt updates related
to eSPI and other updates for MEC172x eSPI driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Errata ES0392 Rev 8:
2.2.9: Reading from AXI SRAM may lead to data read corruption
Workaround: Set the READ_ISS_OVERRIDE bit in the AXI_TARG7_FN_MOD
register.
This is applicable only to RevY (REV_ID 0x1003)
Fixes#38933
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
When built with XCC for Apollolake, Zephyr fails to boot with the
default multi-core option enabled. Invalidate cache before reading
the firmware image to fix that.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Add support for i.MX8MP target.
This has a 1 Xtensa HiFi4 core, with 64 KB TCM,
256KB OCRAM, 8MB SDRAM and 1 SAI as audio interface.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Refactors all of the ADC drivers to use a shared driver class
initialization priority configuration, CONFIG_ADC_INIT_PRIORITY, to
allow configuring ADC drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.
The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to preserve the
existing default initialization priority for most drivers. The
exceptions are lmp90xxx, mcp320x, and mcux_adc16 drivers which have
dependencies on GPIO, SPI, and/or DMA drivers and must therefore
initialize later than the default device priority.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Refactors all of the clock control drivers to use a shared driver class
initialization priority configuration,
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, to allow configuring clock control
drivers separately from other devices. This is similar to other driver
classes like I2C and SPI.
Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_OBJECTS or
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new
option is the lower of the two, which means earlier initialization.
The even lower defaults for STM32 and Arm Beetle are preserved by
SoC-family level overrides.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Use the shared CONFIG_SERIAL_INIT_PRIORITY for driver initialization
priority.
Override the default value for the NEORV32 SoC to ensure the serial
driver is initialized after the syscon driver by default.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add a Kconfig option, similar to the one that is already available
for nRF5340, that allows enabling the REG0 (VDDH) DC/DC converter
in nRF52840. Make use of this option in Nordic boards: nRF52840 DK
and nRF52840 Dongle.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Configures the default serial driver initialization priority for NXP
SoCs to ensure that serial drivers initialize after clock control
drivers.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Uses the stats subsys to provide simple but useful debugging stats for
power management state changes and timing.
Removes the no longer needed PM_DEBUG config option
Replaces the use of PM_DEBUG for a test clock output pin for mec1501 and
adds in its place an SoC Kconfig option to enable it.
Adds a STATS_SET macro for assigning a value to a stat group field
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
The parameters to FIELD() should be the position and size of each bit
field. Correct the size of IOMODE and MAXFREQ. Otherwise, the MAXFREQ
field is overwritten by the IOMODE update during espi_npcx_configure().
Signed-off-by: Diana Zigterman <dzigterman@google.com>
Add common header files for Intel SoC FPGA. The header files define the
handoff data structure and system manager base addresses needed by
Agilex initial bring up.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Replaces the prefixes of gpio_matrix_in and gpio_matrix_out
to unify those function calls on all supported socs.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Implement the CPU idle task. The system should enter this task when
there is no any task to ensure power saving.
Tested on it8xxx2_evb board. It will reduce 12.5mA when system enters
the CPU idle task.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Provide power modes implementation for u5 socs.
For now STOP3 mode is not implemented as this mode is not
compatible with LPTIM activation and hence cannot be used
as a workable suspend to idle state using LPTIM as kernel
tick source.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
When existing stop mode 1&2, VCO is set to range 4
and should be set back to range 1 to allow full speed
operations.
Rather than setting VCO at startup, set it inside clock
setting procedure so that it could done
in clock reset procedure when existing stop modes.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
A new stm32f412vx devices is introduced.
The soc devices stm32f412cx, stm32f412vx, stm32f412zx are
removed to have a more generic stm32f412xx Kconfig.
The stm32cube modules stm32f412cx/vx/zx exists.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
GPIO L/K groups:
On IT81202 (128-pins package), the pins of GPIO group K and L aren't
bonding with pad. So we configure these pins as internal pull-down
at default to prevent leakage current due to floating.
GPIOH7:
On IT81202/IT81302, the GPIOH7 isn't bonding with pad and is left
floating internally. We need to enable internal pull-down for the pin
to prevent leakage current, but IT81202/IT81302 doesn't have the
capability to pull it down. We can only set it as output low,
so we enable output low for it at initialization to prevent leakage.
After setting: power saving=2.26mA
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
When exiting Stop mode, if system clock is MSI, MSI oscillator is
selected as wakeup from stop clock; otherwise HSI16 oscillator is
selected.
It is otherwise reconfigured as MSI just after, but it slightly
increases the wake-up time and power consumption.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
When userspace enabled, the zephyr data region should start from
_app_smem_start instead of __kernel_ram_start.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
This patch mainly moves mpu related code from
arch/arm64/core/cortex_r/mpu/ to arch/arm64/core/cortex_r/ and moves
the mpu header files from include/arch/arm64/cortex_r/mpu/ to
include/arch/arm64/cortex_r/
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Code removed:
- IT8XXX2 doesn't support soc level software interrupt hence remove
them.
- To use common macro to access csr (control status register).
- To remove CONFIG_RISCV_HAS_PLIC related code. IT8XXX2 uses its own
interrupt controller code.
- To remove ite_write and ite_read. We don't use them anymore.
Code changed:
- Return true from arch_irq_is_enabled() when external interrupt-enable
bit, and SOC's IER are both true.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
A few HAS_HW_NRF_* Kconfig options for peripherals available in nRF5340
are not selected. Fix it.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Fixes: #38591, #38207, #37861
The commit 65a2de84a9 aligned the data
linker symbol for sections and regions.
The data region symbol start has been placed outside the sections thus
being defined as the address of the region before alignment of the first
section in the data region, usually the `datas` section.
The symbol defining the start address of the data section is after
section alignment.
In most cases the address of the data region start and datas section
start will be identical, but not always.
The data region symbol is a new linker symbol and existing code has
been depending on the old data section start symbol.
Thus, the update to the use of the data region start symbol instead of
data ram start symbol thus results in a different address when the
section is aligned to a different address.
To ensure the original behavior in all cases, the data region start
address is now moved inside the data section.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Following the migration of the clock source configuration in DTS (commit
2691541ad2), HSI is always used as wake-up source on STM32LX. It is
reconfigured as MSI just after, but it slightly increase the wake-up
time and power consumption.
It happens as the file defining STM32_SYSCLK_SRC_MSI is not included.
Fix that.
Fixes#38807
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Similarly to what was done on stm32g0, disable DBGMCU clock
after operation to avoid conflict with openocd.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
If clock is not enabled write access on that registers are no-op.
Disable clock after operation to avoid conflicts with openocd which
can also access this clock when flashing.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
During review of #38681, switching from HAL to LL,
involuntarily enable DBGMCU clock instead of DMA clock.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
On some STM32 boards, for unclear reason,
RTT feature is working with realtime update only when
* one of the DMA is clocked
and sometimes also
* one of the DBGMCU bit STOP/STANDBY/SLEEP is set
Fixes#34324
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
It happens that CM7 wakeups CM4, before CM4 goes to sleep.
Thus when CM4 goes to sleep,
there no more wakeup from CM7. And CM4 hangs.
For a simple synchronisation implementation,
CM4 doesn't go to sleep any more,
instead it waits (active wait) for CM7 to take HSEM
(meaning that clock configuration is finished).
Fixes#38069
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
On STM32L0, there are some hardfault when DBGMCU bit Sleep, Stop
or Standby are enabled. See #37119
For unclear reason, enabling DMA clock fixes this issue.
(similarly than #38561, DMA clock comes with DBGMCU bits)
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Call __reset instead of directly calling __initialize from the common
RISC-V privileged SoC vectors __start. This allows injection of SoC
specific reset code just after setting up the machine trap vector.
RISC-V privilege SoCs without the need for custom reset code can set
CONFIG_INCLUDE_RESET_VECTOR=y to include a __reset stub which simply
calls __initialize.
Fixes: #38396
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
CONFIG_PM_DEVICE was a de-facto requirement when enabling CONFIG_PM=y
since some device, i.e. UART, used the PM device hooks to block
suspension process while the device was busy finishing transmission.
This has now been fixed using constraints, so CONFIG_PM=y can be enabled
without further requirements.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
TI Hal has its own constraint API that is used by its drivers. These
constraints need to be correlated with Zephyr constraints to be
constraints set in the HAL be visible on Zephyr and vice-versa.
Fixes#38362
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
In commit "pm: Fix weak linkage symbols" (PR #35274),
PM SoC hooks were converted to __weak to avoid clash with
new definition of these symbols in subsys/pm/power.c.
G0 power implementation was implemented in parallel
with this change and missed the update.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Older binutils, like the (nine-year-old!) 2.23 version that powers
many Cadence XCC toolchains, happen not to support the "~" operator to
perform bitwise negation. And they generate an absolutely hilarious
series of inscrutable error messages when they try to tell you this
fairly simple fact.
Just fold it into the constant.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Low power modes entry on stm32wb depends on requests coming from both
cores, with no consideration of the fact that C2 is booted or not.
By default, set C2 power mode to shutdown at C1 start up.
If required, it will be updated by C2.
In case C2 is not started, this will allow C1 to enter any power mode
with no dependency on C2.
Fixes#38173
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Setting this bit will wake up CPU if it is in low power mode
and an interrupt is pending.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This patch adds support for SiFive Freedom U740 SoC.
First version is minimum only using UART, SPI and L2-LIM area.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
This patch adds support for SiFive Freedom U540 SoC.
First version is minimum only using UART, SPI and DDR memory area.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
The free run timer will be used to count before entering hibernate
mode. Move the related registers to the head file for accessing.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This feature got written twice for two different purposes (to inform
the SOF app of which CPUs are running, and to predicate the delivery
of IPIs to the cores ready to receive the interrupt). Use only one.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
On pre-2.5 cAVS, the initial IDC interrupt to start the other core is
handled by software in the firmware ROM. That means that it has to be
unmasked for the mechanism to work (with 2.5, the interrupt is handled
by hardware regardless of what the masking state in the interrupt
controller is).
Similarly, the Xtensa Region Protection Option entries have already
been set by ROM code when we arrive in enable_l1_cache(), so we can
skip that part on older machines. Also removed because trying to
rewrite those entries was causing inexplicable hangs on cAVS 1.5,
plausibly because the region had active cache lines.
(This patch is separate for easier review in a long evolving PR.
Technically it represents a bisection problem as the "New IDC Driver"
patch before this was a regression. Seems like a safe enough thing to
handle if you land on this.)
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Fix various bugs with the new IDC layer that show up in edge cases
where code relies on correct timing of IPIs (unsurprisingly there is a
lot of code that recovers anyway even if the IPI doesn't arrive
promptly). Leaving this as a separate patch because the prior code in
the PR has already been reviewed and it "mostly" worked:
The unmasking of the L2 interrupt bit (remember there are three layers
of masking of the IDC interrupt) was always operating on CPU0 at CPU
startup because the code had been copied blindly. Unmask the CPU
we're actually launching. It turns out cAVS 2.x re-masks this on CPU
launch automatically.
The global init code to unmask all these interrupts at startup had the
same bug, even though it turned out to be needless (the initialization
state has it unmasked until it turns it back off). Do it right
anyway. Similarly add code to clear out existing interrupt latch
state by ACKing all IDC interrupts at startup. Seems needless, but
behavior isn't documented so let's be safe.
Flag CPU0 as always "active" for the purposes of IPIs. Forgot to do
this earlier, oops.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The alignment on .bss was coming out wrong. The ". = ALIGN(4096);"
statement was being ignored, somewhat inexplicably. This resulted in
the bss symbols being assigned corret-seeming, non-overlapping
addresses. But it overlapped the page-sized padding at the end of
.data.
As it turns out, the rimage format (not the linker or Zephyr) requires
page-sized sections to copy, and the bootloader code does that copy by
writing to the CACHED mapping of the memory (.bss is, like .data,
uncached/coherent by default). So at runtime the CPU was running in a
context where the cache was populated with "booby trap" data at the
start of .bss. True .bss access would hit the memory uncached and see
the "correct" value, but at arbitrary times during execution lines
would be flushed out of L1 cache on top of it.
Oops. This was found by accident, actually, as routine changes to the
linker script to correctly support the case where KERNEL_COHERENCE=n
(i.e. put everything in the cached mapping and nothing in uncached)
suddenly hit rimage failures because of the overlap.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add a SOC API to allow for application control over deep idle power
states. Note that the hardware idle entry happens out of the WAITI
instruction, so the application has to be responsibile for ensuring
the CPU to be halted actually reaches idle deterministically. Lots of
warnings in the docs to this effect.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There is a hardware startup state where power gating can be "enabled"
even though the core is actually launchable via an IDC interrupt (in
fact that's the hardware default). In that state, the CPU will launch
correctly but then unexpectedly shut itself off then it enters the
idle thread.
Don't rely on initialization state, always set the power and clock
gating bits (to disable gating) immediately before CPU launch.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add a struct-based interrupt masking API to match the existing shim
and IDC register interfaces. The existing interrupt controller code
isn't using it yet.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
On cAVS 2.5, there is an inherent race with the IDC interrupt. It's
used for routine IPIs during OS operation, but also for launching a
power-gated core. Recent changes moved the unmasking of the IDC
interrupt earlier, which made it possible for early OS scheduler
behavior (e.g. adding the main thread to the run queue) to
accidentally launch the other cores into LP-SRAM that had not been
initialized.
Instead of treating this with initialization ordering, keep and
maintain a list of active CPUs and check them at runtime to be sure we
never try to IPI a CPU that isn't running yet. We're going to need
this feature when we add live core offlining anyway.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Use the built-in IDC handling and not IPM (which is limited to two
CPUs). Declare two cpus for now, Zephyr tests are having problems
with more at the moment (that isn't a CI configuration, so we may have
work to do).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The original interface for the intra-DSP communication hardware on
these devices was buried inside a Zephyr IPM implementation.
Unfortunately IPM is a two-endpoint point-to-point communication
layer, it can't represent the idea of devices with more than 2 cores.
And our usage (to push a no-argument/no-response scheduler IPI) was
sort of an abuse of that metaphor anyway.
Add a new IDC interface at the SOC layer, borrowing the C struct
convention already used for the DSP shim registers.
Augment with extensive documentation, extracted via a ton of
experimentation on cAVS 2.5 hardware.
Note that this leaves the previous driver in place for the cavs_v15
and intel_s1000 devices. In principle they should use it too (the
hardware registers are identical), but this hasn't been validated yet.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Earlier platforms were relying on the system ROM to have done this
correctly, but with CAVS 2.5 we launch the CPU into our own code
directly. So we need to do those steps manually. And there's also a
new one on this hardware, which has software power control over the
cache SRAM.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Hardware defaults for the secondary CPUs have the S32C1I instruction
set to be atomic only with respect to the local L1 cache, which is
basically useless on a multiprocessor platform. The CPU0 boot path
sets this manually, so we need to duplicate that here.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
On MP cores that don't come through the core entry point
(e.g. TGL/v2.5) we reach C code with hardware defaults for the RPO/TLB
settings. Set these up correctly on entry.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This hardware works a little differently. The cores will start up
immediately on receipt of an IDC interrupt (they don't need the host
to be involved), but they don't have a ROM. They start executing at
the start of the LP-SRAM block always. Copy over a tiny trampoline
for them that jumps to the existing multiprocessor startup path.
Also set the PS WOE bit to enable register windows in the startup
path. This isn't the hardware default, and where the ROM would do
that for us before here we need to make sure it's on.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This reverts commit ee7773fb46.
Unfortunately this mechanism doesn't seem to actually work on the SDK
linker. The emitted sections, when passed a symbol name as the "start
address" just appear wherever the "." variable was pointing (in this
case, into the cached region). That breaks the kernel coherence
layer, obviously.
Revert for now, which will regress the XCC build fix pending a proper
root cause.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This aligns the SoC initialization with the one in SOF,
especially the manipulation of clock control and power control
registers. These registers are not entirely the same across
CAVS versions, so we need to deal with them according to
which version we are building for. This also consolidates
the macros for these registers to the one provided by SOF
(soc/shim.h) to avoid duplication. Another note is that
the usage of clock gating bit was not correct. In SOF,
clock gating of SoC cores should be allowed but the old code
in Zephyr prevented clock gating, which has the potential to
prevent the whole DSP from going into low power mode.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The wall clock timer is not (per documentation) part of the
"timestamping" register set on the DSP. And its counter and
comparator registers work fine always. But if the DSP isn't set as
the "owner" of the timestamp hardware, wall clock interrupts never
arrive.
Also grab the PLL ownership too, because SOF already does anyway.
While we don't have a dynamic clock driver yet, we will surely want
one soon and will needt this.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These windows control host visibility of the trace output buffer. The
buffer itself is writable memory always, but until we get to the
register init the host can't see them. Since they contain
printk/logging output, they REALLY need to be initialized earlier than
anything else.
Also remove a rogue memset of the trace buffer. That buffer is
already being initialized in a lazy-evaluated way by the trace output
code, and blowing it away here has the effect of forgetting anything
earlier code was trying to log!
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
the config symbol was missing for some reason even though
the soc does have a flexspi peripheral like most other socs
in the family.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Apply a similar fix for cavs_v20 as was done for other cavs platforms in
commit ee7773fb46 ("soc: intel_adsp: fix linker script for XCC").
Without this fix, cavs_v20 build with fail with 0.13.0 Zephyr SDK.
Fixes: 74cc8bee7c ("xtensa: cavs_v20: use uncached addresses to support SMP")
BugLink: https://github.com/thesofproject/sof/issues/4703
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
PR #37938 aligns many linker symbols name like rom/rodata_regions ...,
but ae350 soc linker script doesn't update for that. Migrate all linker
symbols name to PR #37938 changes.
Signed-off-by: Jim Shu <cwshu@andestech.com>
System heap buffer was moved from dram0_0_seg to dram0_1_seg.
This commit fixes system heap buffer placement.
Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
SMP support on cAVS is implemented by using uncached addresses for all
writable data sections except for stack, i.e. for .data, .bss and
some other specialised ones. So far that has been implemented for
cAVS 1.5/1.8. This patch does the same for cAVS 2.0.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This initial support of L2C driver only contains cache enable and HW
capability checking. Cache management operation isn't supported yet
in this driver.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Andes V5 PMA can let SW programmably configure memory attribute of
physical memory region. This commit enable CONFIG_NOCACHE_MEMORY of
Andes V5 CPUs based on the PMA. Use PMA region 0 to set whole nocache
section as uncached memory.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Support custom RISC-V CSR context switch for Andes V5 CPUs.
Both AndeStar V5 DSP and PowerBrake features have it's own CSR to be
saved for thread and ISR context, so adding these CSRs into the RISC-V
SOC context management framework (CONFIG_RISCV_SOC_CONTEXT_SAVE).
Signed-off-by: Jim Shu <cwshu@andestech.com>
Add andes_v5 SoC series and andes_ae350 SoC. It includes
soc initialization code, linker script, and custom CSR encoding.
Signed-off-by: Jim Shu <cwshu@andestech.com>
This is the initial version of a Zephyr CMake linker file for the arm
architecture.
This file defines memory regions, groups, linker sections and symbols
for the arm architecture.
It also sources the common common-ram.cmake, common-rom.cmake,
debug-sections,cmake, and thread-local-storage.cmake.
It configure sections for SoC families using zephyr_linker_sources()
functions:
- nxp_imx
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
For IMX, for timer interrupt, the interrupt handler
was not the correct one executed and that’s because
the handlers were not at the expected address.
For IMX the size constraint of the interrupt vector
table entry is 0x1C bytes of code, less than usual.
I've added a small indirection to bypass this size
constraint and moved the default handlers to the end
of vector table, renaming them to
_Level\LVL\()VectorHelper.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Add a common part for all i.MX boards.
Add support for i.MX8, which represents i.MX8QM.
This has a 1 Xtensa HiFi4 core, with 64 KB TCM,
448 KB OCRAM, 8MB SDRAM and 1 ESAI, 1 SAI as
audio interfaces.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Cleanup and preparation commit for linker script generator.
Zephyr linker scripts provides start and end symbols for each larger
areas in the linker script.
The symbols _image_text_start and _image_text_end sometimes includes
linker/kobject-text.ld. This mean there must be both the regular
__text_start and __text_end symbols for the pure text section, as well
as <group>_start and <group>_end symbols.
The symbols describing the text region which covers more than just the
text section itself will thus be changed to:
_image_text_start -> __text_region_start
_image_text_end -> __text_region_end
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Cleanup and preparation commit for linker script generator.
Zephyr linker scripts provides start and end symbols for each larger
areas in the linker script.
The symbols _image_rom_start and _image_rom_end corresponds to the group
ROMABLE_REGION defined in the ld linker scripts.
The symbols _image_rodata_start and _image_rodata_end is not placed as
independent group but covers common-rom.ld, thread-local-storage.ld,
kobject-rom.ld and snippets-rodata.ld.
This commit align those names and prepares for generation of groups in
linker scripts.
The symbols describing the ROMABLE_REGION will be renamed to:
_image_rom_start -> __rom_region_start
_image_rom_end -> __rom_region_end
The rodata will also use the group symbol notation as:
_image_rodata_start -> __rodata_region_start
_image_rodata_end -> __rodata_region_end
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Cleanup and preparation commit for linker script generator.
Zephyr linker scripts provides start and end symbols for each section,
and sometimes even size and LMA start symbols.
Generally, start and end symbols uses the following pattern, as:
Section name: foo
Section start symbol: __foo_start
Section end symbol: __foo_end
However, this pattern is not followed consistently.
To allow for linker script generation and ensure consistent naming of
symbols then the following pattern is introduced consistently to allow
for cleaner linker script generation.
Section name: foo
Section start symbol: __foo_start
Section end symbol: __foo_end
Section size symbol: __foo_size
Section LMA start symbol: __foo_load_start
This commit aligns the symbols for _data_ram/rom to other symbols and in
such a way they follow consistent pattern which allows for linker script
and scatter file generation.
The symbols are named according to the section name they describe.
Section name is `data`
A new group named data_region is introduced which instead spans all the
input and output sections that was previously covered by
__data_ram_start, __data_ram_end, and __data_rom_start.
The following symbols are aligned in this commit:
- __data_ram_start -> __data_region_start
- __data_ram_end -> __data_region_end
- __data_rom_start -> __data_region_load_start
The following new symbols are introduced so that the data section is
aligned with other sections:
- __data_end
- __data_start
value identical to __data_region_start but describes start of
the section.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
We add support of mpu v6 therefore it is needed to have a board to
validate that feature. This commit add a new HS nsim simulator
which supports mpu v6.
Signed-off-by: Yuguo Zou <yuguo.zou@synopsys.com>
Move the IDT_LIST memory region to the location recommended by
`intlist.ld`. The documentation specifies that this region should not
overlap other regions, and there is no guarantee that the area after the
`SRAM` region is not used. The end of the address space is much less
likely to be a valid RAM address.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Define soc_interrupt_init as a weak symbol in the common RISC-V
privileged instruction set SoC support.
This allows overriding soc_interrupt_init for SoCs which are not fully
compliant with the RISC-V privileged specification.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Define __soc_handle_irq as a weak symbol in the common RISC-V privileged
instruction set SoC support.
This allows overriding __soc_handle_irq for SoCs which are not fully
compliant with the RISC-V privileged specification.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Follow up on commit bfd45e5b8c
("drivers: remove Kconfig option CONFIG_UART_CONSOLE_ON_DEV_NAME")
Remove Kconfig options
CONFIG_BT_UART_ON_DEV_NAME and CONFIG_BT_MONITOR_ON_DEV_NAME
since all UART drivers are converted to devicetree and we can just use
DEVICE_DT_GET(DT_CHOSEN(zephyr_bt_uart)) and
DEVICE_DT_GET(DT_CHOSEN(zephyr_bt_mon_uart)).
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Microchip MEC172x series I2C driver implementing controller
and target modes. The driver implemenents its own I2C port
pin control functions and does not depended upon pinmux. Future
updates will make use of PINCTRL when that subystem is finalized.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add Kconfig options that allow users to select the way the APPROTECT
mechanism is handled in the SystemInit() function.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
esp32c3 has already supported RISC-V GP, just apply new kconfig option
to it. Forcely select CONFIG_RISCV_GP in esp32c3 at first because it
seems to be necessary in the esp32c3 SoC.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Add norelax option before initializing GP at common entry point.
Remove __global_pointer$ symbol in the SoC linker script because it's
in the arch one. Remove -mno-relax when GP support is enabled.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Initialize GP at common entry point of riscv-privilege SoCs so that
this commit add GP support of these SoCs at once.
As some privilege SoCs want to customize the entry point, they should
disable linker relaxation by `.norelax option` before entrying the
common entry point `__start`.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Creating static libraries for drivers moves some symbols out of IRAM.
This change fixes it.
Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
Creating static libraries for drivers moves some symbols out of IRAM.
This change fixes it.
Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
Creating static libraries for drivers moves some symbols out of IRAM.
This change fixes it.
Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
1. Update soc.c file to add USB clock setup
2. Add a linker script file to move USB transfer
buffer and controller buffers to USB RAM
3. Update Kconfig's to add USB support
4. Add zephyr_udc0 nodelabel
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Update soc.c file to add USB clock setup
2. Add a linker script file to move USB transfer
buffer and controller buffers to USB RAM
3. Update Kconfig's to add USB support
4. Add zephyr_udc0 nodelabel
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The USB config name has changed to USB_MCUX and the
device tree node name has changed from nxp_kinetis_usbd
to nxp_mcux_usbd
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The delay will ensure last byte has been latched in before
This also change the method of reading status register from re-send
read status command on each read to read status register continuously.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
log and libc optimization default config are soc related
and should be moved out from board context.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This reverts commit 7b09d031fa. Because
context save of GP register is removed, we don't need to initialize GP
at thread init. GP will be a constant value so that it could only be
initialized at program start.
Signed-off-by: Jim Shu <cwshu@andestech.com>
The way we currently handle direction finding extension (DFE) support
on Nordic nRF5 controllers relies on required devicetree properties
related to DFE in the "nordic,nrf-radio" node.
That doesn't make sense on radios without DFE support, though.
Any .dtsi for an SoC without DFE support which has such a node would
require extraneous DFE related properties like dfe-antenna-num.
Instead of making the properties required, mark them optional. We
indicate the presence of DFE support via a new 'dfe-supported' boolean
property which the SoC .dtsi files can set (or not) depending on
support.
This gives us the opportunity to do some cleanup in the Kconfig,
removing CONFIG_HAS_HW_NRF_RADIO_BLE_DF since we know from the
devicetree whether DFE support is available.
Handle that change appropriately in radio_df.c. This gives us an
opportunity to improve readability in the devicetree-related macro
magic in that file.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This commit enables the ARM DSP extension on the MPS2 AN521 SoC CPU1
(the CPU1 supports both FPU and DSP).
With this change, the CMSIS-DSP tests running on the
`mps2_an521_remote` board will use the DSP instructions.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
QEMU supports the MPU on Cortex-R platforms so enable it for the
qemu_cortex_r5 platform. This allows running the mem_protect kernel
tests.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
This commit updates the MPS3 AN547 SoC configuration to enable the FPU
as well as the DSP and MVE extensions.
Note that the CPU0 of the SSE-300 (and AN547) supports all of the
extensions mentioned above (as for MVE, it supports both MVE-I and
MVE-F).
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This migrates all the current iterable section usages to the external
API, dropping the "Z_" prefix:
Z_ITERABLE_SECTION_ROM
Z_ITERABLE_SECTION_ROM_GC_ALLOWED
Z_ITERABLE_SECTION_RAM
Z_ITERABLE_SECTION_RAM_GC_ALLOWED
Z_STRUCT_SECTION_ITERABLE
Z_STRUCT_SECTION_ITERABLE_ALTERNATE
Z_STRUCT_SECTION_FOREACH
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Max SPI chunk len was missing from the
implementation, causing SPI to hang up in some
conditions.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
bt_conn_cb section was added into common-rom.ld and
as current ESP has limited segment section number, it
needs to be moved out from there.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
PSoC-6 have different priority bit masks for cortex-m0+ and cortex-m4.
M0: 0-3 (2 bits of NVIC prio, no prio reserved by the kernel)
M4: 0-6 (3 bits of NVIC prio, one level reserved by the kernel)
The current macro that gets priority level value from devicetree apply
same value from cortex-m4 on cortex-m0+. This add missing indirection
to get from intmux node the correct cortex-m0+ priority level value.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add ADC driver version 2 for MEC172x using new in-tree headers
and device tree properties. Update the ADC shell for the new driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Microchip XEC has been using the standard NS16550 driver.
Using the standard NS16550 driver requires extra HW programming
for XEC UART in board level and did not support XEC GIRQ interrupt
programming. We add an XEC specific driver and remove UART specific
register programming from the board level and implement interrupt
support. Also, by implementing a SoC specific driver we can add
driver PM in the future.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Pull a new revision of the hal_ti module that uses dynamic interrupts
instead of build-time ones.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
We try to reduce the ambiguity between 'soc/nuvoton/' and
'soc/nuvoton_npcx' folders. Most if soc vendors name their soc folder by
the company name with SOC_FAMILY suffix instead of the company name
directly. It is clearer if the soc company has different product lines
that aim to specific markets.
In this CL, the 'numicro' suffix is used for Nuvoton Microcontroller
production line. It distinguishes the 'npcx' suffix that used for
Nuvoton Embedded Controller (EC) of Notebook PC product line.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Current location options for linker source files includes init and
noinit ram data, but only a noinit ram section. This makes it impossible
for application code to define an initialized RAM output section,
such as with the Z_ITERABLE_SECTION_RAM() helpers.
Adding a DATA_SECTIONS linker source option for this use case.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
esp32c3 SoC is an rv32imc, so it does not support the atomic builtin.
Since it relies in atomic instructions.
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
RT platforms that support TRNG IP (rt10xx and rt6xx) need to set
RNG and CSRNG to Xoroshiro and CTR_DRBG respectively instead of
using TRNG as random source.
Fixes: #37307
Signed-off-by: David Leach <david.leach@nxp.com>
Deprecate the xoroshiro128+ PRNG algorithm in favour of xoshiro128++.
xoshiro128++ is a drop-in replacement which is invisible from the user
perspective.
xoroshiro128+ is unsuitable because it is explicitly a floating-point
PRNG, not a general-purpose PRNG. This means that the lower 4 bits of
the output are actually linear, not random (from the designers,
https://prng.di.unimi.it/). This means 1/8th of the generated data is
not random.
Additionally, xoroshiro128+ is not a 32bit algorithm, it operates on
64bit numbers. For the vast majority of Zephyr devices, this makes the
PRNG slower than it needs to be. The replacement (xoshiro128++) is
32bit, with no loss in state space (still 128 bit).
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Update the Microchip XEC pinmux driver to use system I/O
routine for read/write of registers instead of direct use
of volatile and CMSIS defines. Add GPIO port number to
bindings instead of using hard coded value from chip headers.
Modify SoC DTSI pinmux syntax, requires "pinmux: pinumx {..."
or the DT macros will not work. Since pinmux is used by MEC152x
we update its chip pinmux DT.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Replace USB configuration option with USB_DEVICE_DRIVER
since on the SoC level the specific driver is selected.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
based on uart rom functions, also enable console driver
on top if this driver enabling logging
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
The host interface type (eSPI/SHI) is selected via HIF_TYP_SEL field in
DEVCNT register. This commit adds a function to set it.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The booter (bootloader) behavior may be different in different NPCX
chip series. One example is that the booter sets host interface type in
NPCX7 series but leave the firmware to set it in NPCX9 series.
This commit adds a new DT node to record variants in its properties.
NPCX drivers can understand if they need to configure the related
setting by checking the node's properties.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Add watchdog support to the mimxrt685 platform.
The mimxrt685 platform is excluded from the watchdog
test case because the test case uses variables in the
noinit section that need to be retained through a reset
but the rt685 does not retain this memory through a
reset.
Signed-off-by: David Leach <david.leach@nxp.com>
* Move definition of flexspi_nor_config_t into soc/ dir so it can
be shared by all i.MX RT based boards.
* Use Kconfig symbol CONFIG_NXP_IMX_RT_BOOT_HEADER instead of
HAL define (which is set based on the Kconfig symbol)
* Rename board files to flexspi_nor_config.c since they
are already namespaced by the board dir.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Introduce soc_port common functions. The sam0 pinmux driver was
refactored to use soc_port_pinmux_set common function.
This create the common base to implement sam0 pinctrl functions.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Some STM32 series (l0, g0, f0) needs to enable clock of
DBGMCU peripheral, before accessing registers
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Create a shared macro to access the pinctrl_0 property. The pinctrl_0
property includes pinmux phandle, pin and alternate function.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Move the implementation of z_platform_init from the NXP Hal
into the main Zephyr tree. This function is Zephyr-specific,
is part of the Zephyr module glue code, and does not need to
reside in the module repository. We also rename the function
to z_arm_platform_init. The commit does not introduce any
behavioral changes.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Platform specific initialization during early boot
has been a feature supported only by Cortex-M; the
Kconfig symbol is defined in arch/arm Kconfig space.
We rename the z_platform_init() function to
z_arm_platform_init(), to indicate more clearly that
this is an internal, private ARM-only API.
This commit does not introduce behavioral changes.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Create version 2 of the MEC GPIO driver to support MEC172x to not
interfere with MEC152x. When the MEC172x ECIA interrupt aggregator
driver is ready, this driver will use ECIA for registering GPIO
interrupt callbacks instead of maintaining its own interrupt table.
Add V2 DT binding.
Add the Kconfig configuration settings for the MEC172x GPIO
V2 driver at the SoC and board level.
Add port id to DT allowing use of DT FOR EACH macro in the driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Update Microchip XEC RTOS timer driver adding MEC172x support and
using more device tree properities in the driver. We must also update
the XEC counter driver to use the new GIRQ DT properties.
Add new properties to RTOS timer and RTC timer YAML. These two timers
are linked due to option using a high speed timer for kernel busy wait.
Add Kconfig logic for XEC RTOS timer to MEC172x SoC.
Enable the Microchip XEC RTOS timer in the MEC172x evaluation board.
Add device tree nodes for most peripeherals.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
In commit "pm: Fix weak linkage symbols" (PR #35274),
PM SoC hooks were converted to __weak to avoid clash with
new definition of these symbols in subsys/pm/power.c.
In this process, few SoCs were missed.
Fix this.
#37226
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The KBC/ACPI event data is 4-byte in width and composed of
event/data/type fields. However, the field position is defined by each
chip vendor via macro and not unified in the current implementation.
The commit uses the structure bit field to define and unify the field
position. It helps the application access it with a common approach.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
it8xxx2 supports 'm', 'a', and 'c' extensions.
Enable them to save flash space and also improve
latency of fetching code from flash.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This CL replaces offset macros of pmc 'multi-registers' such as
PWDWN_CTLn with internal inline functions for better readability.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL replaces offset macros of scfg 'multi-registers' such as DEVALTn
and LV_GPIO_CTLn with internal inline functions for better readability.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add driver implementation and header files for a MEC172x
aggregated interrupt driver. Enable the parent(ECIA) node
to have the driver initialize interrupt hardware for use.
Enable child nodes for those GIRQs used for aggregation.
Refer to chip documention for the list of GIRQs restricted
to aggregation and those which support direct mode.
Add chip level device tree node for MEC172x EC interrupt
aggregator parent and GIRQ children. Each child node contains
a list of sources representing the source bit position in the
GIRQ registers.
Add DT bindings for ECIA and GIRQ nodes.
Add build file(s) and configuration items for the MEC172x ECIA
aggregated interrupt driver. Add and enable the MEC172x interrupt
driver on the MEC172x evaluation board(EVB). Enable parent node to
initialize ECIA hardware. Child nodes are left disabled until a
future driver needs them.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Define SoC hooks as weak symbols so this way applications can
overwritten them defining strong symbols.
The problem is that currently SoCs are defining these interfaces as
strong symbol inhibiting the possibility of applications bring their
own implementation.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Correct SYS_CLOCK_HW_CYCLES_PER_SEC and
SYS_CLOCK_TICKS_PER_SEC to match our real setting value
for precise timing.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Add the missing includes to make the header more portable. It currently
requires other headers to be included before it.
Signed-off-by: Yuval Peress <peress@chromium.org>
XCC's linker cannot properly process our linker script with
regard to cached/uncached memory regions as the linker cannot
correctly calculate addresses using boolean operations.
Fix this by doing address pointer arithmetic manually to
move between cached and uncached memory regions.
The addresses of symbols were compared via nm and they are
the same before and after this change.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
XCC's own xt-objcopy does not recognize the "--dump-section"
command. So simply copy the objecy file into binary so it can
be included in the final bootloader binary.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This moves the inclusion of sys/util.h inside the #if block to
avoid this being included when going through XCC's assembler.
With the old behavior, a bunch of std*.h get pulled in resulted
in build failure as keywords such as "typedef" are not supposed
to be in assembly files according to XCC assembler.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Implement a clock control driver for Microchip MEC172x handling
configuring the 32 KHz input sources for the PLL and peripheral-32k
clock domains. MEC172x differs from MEC152x. MEC152x had one 32K source
for both PLL and peripherals. MEC172x allows the two domains to use
independent 32 KHz sources. Device tree updated to provide addresses
of hardware used by the driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
cc13x2_cc26x2 had its own power policy that was implementing the same
logic available in the default residency policy. Also, this policy was
unnecessarily setting up a timeout to wakeup the system. This is not
necessary, the power subsystem takes care of this.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Implementation of hardware semaphore algorithm of STM32 AN5289
to enter and exit low power
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Add MEC172x chip specific headers for Port 80h debug
capture, quad SPI, and VBAT registers. Update due to
merges.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
reuse the lpc's lpadc driver for rt1170, modify the dts and add
some macro to shield some code of LPC series. Also add the
board support inside the tests/drivers/adc/adc_api/src/test_adc.c,
and a dts node:zephyr,user inside
samples/drivers/adc/boards/mimxrt1170_evk_cm7.overlay
Signed-off-by: Crist Xu <crist.xu@nxp.com>
Add Microchip MEC172x header set 5 chip specific
peripheral headers. Update with recent merged code.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Consensus was reached to locate Microchip MEC172x header files
in the zephyr MEC172x SoC folders. These are the first set of
headers specific to MEC172x and common to the MEC family. Hardware
register structures will be located in peripheral specific headers.
Update based on latest merge of MEC172x related files.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Adding support for the stm32l051 devices.
Signed-off-by: Even Falch-Larsen <even.falch.larsen@nomono.co>
Co-authored-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Added minimal device tree and board files to build Microchip
MEC172x. SOC layer stripped down to allow build for checking
compilation only.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Pin PB5 is part of ARM Cortex-M debug interface and by default
configured to output TDO/TRACESWO signal. Disable TDO/TRACESWO
function on PB5 pin when LOG_BACKEND_SWO is not enabled. This
ultimately frees the pin to be used by standard SoC peripherals.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This commit includes the following:
1. Add symbol for choice option. So we can override the default value
by an earlier definition.
2. NPCX9 doesn't support 33MHz SPI clock in the header. So disable the
option for NPCX9.
3. NPCX9 support 512K flash. Change default to 512k for NPCX9.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
To be able to get a tokenize DT string without the quotes. Deprecate
also DT_ENUM_TOKEN and DT_ENUM_UPPER_TOKEN.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Default Voltage scaling range selection (range2)
doesn't allow to configure Max frequency
switch to range1 to match any frequency
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Default Voltage scaling range selection (range2)
doesn't allow to configure Max frequency
switch to range1 to match any frequency
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Add power management support (runtime-idle and suspend-to-idle)
support for the NXP Kinetis KE1xf SoC series.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Enable the NXP Kinetis Low Power Timer (LPTMR) OS timer driver when
power management is enabled as the Arm SysTick timer cannot wake up the
KE1xF from deep sleep.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Keep the Slow Internal Reference Clock (SIRC) running in low-power
mode.
This allows peripherals that needs to remain operative in low-power
mode to use the SIRC as clock source.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Determine the default CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC from devicetree
when using the Arm SysTick hardware timer.
When the NXP KE1xF SoC series is using the Arm SysTick as hardware
timer, the cycles/second will always be equal to the CPU core clock
frequency.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Adds a devicetree chosen node to the mimxrt1170_evk_cm7 board to link
Segger RTT and SystemView sections in DTCM by default. Enables the AHB
clock while the CM7 is sleeping to allow debug access to the TCM.
Note that automatic RTT control block detection may not search the DTCM
address region, therefore you may need to manually set the RTT control
block address or search range in the Segger host tools (SystemView or
RTT Viewer). For example,
$ JLinkRTTViewer -ra 0x20000000
Tested with:
- samples/subsys/shell/shell_module/
- samples/subsys/tracing/
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The SoC driver name is 'USB High-Speed Interface (USBHS)'. This rename
from usb_dc_sam to usb_dc_sam_usbhs allowing add others SoC drivers
like 'USB Device Port (UDP)' that is found at SAM4S/E variations.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit adds support for stm32wle4xx, stm32wle5xx single core socs,
as well as stm32wl54 dual core soc.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The bootloader itself contains the i.MX RT6xx boot header, so we don't
need to duplicate it when building chainloaded applications.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Refactors the i.MX RT600 SoC series to be more consistent with the i.MX
RT10xx SoC series by choosing a child node (external flash device) of
the FlexSPI bus for zephyr,flash.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
With this patch, zephyr can enable SMP directly. Otherwise
zephyr needs TB-R to provide psci function.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Add strong definition z_arm64_el2_plat_init() and it is controlled
by CONFIG_SOC_FVP_AEMV8R_EL2_INIT.
VMPIDR_EL2 must be set manually on EL2. The purpose of VMPIDR_EL2 is
that holds the value of the Virtualization Multiprocessor ID and This
is the value returned by EL1 reads of MPIDR_EL1
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
This commit adds a new Kconfig option CLOCK_CONTROL_NPCX_EXTERNAL_SRC.
With this option enabled, the internal 32.768 KHz clock (LFCLK) is
generated by the on-chip Crystal Oscillator (XTOSC). Otherwise, the
LFCLK is generated by the Low-Frequency Clock Generator (LFCG).
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
NPCX power.c use LOG_MODULE_DECLARE(soc), but NPCX chip doesn't
register soc log module. This CL register soc log in soc.c to fix NPCX
build error for power management & log system.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Save ra to caller saved register is wrong because it might get
overwritten after another function is called, so we fix this.
Remove clear mip register operation. (it8xxx2 supports machine-mode
only, and MEIP bit of mip is read-only).
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
For esp32c3 related ROM located functions instead
of esp32c3_rom.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
The _PrepC() function is the standard risc-v way
of zephyr entry point, so let it call the z_cstart instead
of calling this function directly.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
replaces the plain memcpy to zero the bss with
the standard zephyr function that does this task.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
Plus added implementation for esp32c3 SoC.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
by adding the soc specific files such: soc initialization code,
linker scripts and support for esp32c3 devkitm
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
hal_espressif repository was updated from esp-idf v4.2
to esp-idf v4.3 to allow latest Espressif chips integration.
As a consequence, it added a few changes in drivers
and peripherals. To maintain bisectability, changes in this
PR cannot be split. Here are some details:
wifi: update linker script by adding libphy and new attributes.
spi: update some APIs and fixed missing wait_idle check
west.yml: esp32: update hal to new version
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Configures Segger RTT and SystemView data linker sections to DTCM by
default on i.MX RT SoCs if there is a zephyr,dtcm chosen node in
devicetree. This fixes a build warning in
samples/subsys/shell/shell_module for the mimxrt1170_evk_cm7 and
mimxrt1170_evk_cm4 platforms, which don't currently have a zephyr,dtcm
chosen node.
Note that there are runtime issues with Segger RTT and SystemView on
this board that need further debug, but submitting this patch now to
address nightly CI failures.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This fixes missing PPP iterable and adds all
common-rom.ld iterables.
ESP32 and esptool does not support more then 16 segments, which
blocks including common iterables section as is.
This partially reverts commit ad0bf94f77
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This adds power management support for the STM32WL series.
Suspend-to-idle is mapped to the three stop states (wake up from any
EXTI, including LPTIM), and soft-off can trigger either standby or
shutdown (wake up in reset).
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
The PS/2 module in npcx provides a hardware accelerator mechanism
including an 8-bit shift register, a state machine, and control logic
that handle both the incoming and outgoing data. The hardware
accelerator mechanism is shared by 4 PS/2 channels. To support it,
this CL separates the PS/2 driver into channel and controller drivers.
The controller driver is in charge of the PS/2 transaction. The channel
driver is in charge of the connection between the Zehpyr PS/2 API
interface and controller driver.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This commit adds the asserts symbol in Kconfig to enable/disable
asserts functionality for stm32 series. These would be used in
stm32cube hal & ll drivers.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
rv32m1_vega don't boot due to device init ordering and changes with the
device model. The soc code is looking for a device pointer for the
intmux. Change to using DEVICE_DT_GET here as that will ensure we get
a valid pointer and by the time we need to utilize the pointer the
intmux driver will have been initialized and thus the device pointer
will be ready.
Also set BUILD_OUTPUT_HEX since we utilize openocd to flash and west
flash is looking for a hex file for openocd targets.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This is a work in progress initial submission for the
Microchip MEC172x family SoC. This submission does
not contain all header files or power management.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
1. Added RT10xx and RT11xx configs
2. Added a new soc file for rt117x. There are clock differences
between the RT10xx and RT11xx series, hence the soc files
have been separated.
Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
Enable Instruction Cache
Warning: no flash driver yet available for STM32l5
But cache coherency management (cache invalidate)
will be rerquired when implementing flash driver.
ICAHE must be disabled for any flash write opeartion.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Enable Instruction cache accelerator for Cortex M4
first 1MB of Flash.
As per Reference Manual: no need for cache coherency management
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Convert the various device_get_binding() calls used to get the device
clock node to use DEVICE_DT_GET. The latter is processed at link time,
so it should be a bit more efficient.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add power management support to STM32L0 series.
The SoC have a single stop state that can be used with LPTIM as a system
timer, as well as a standby mode where the system resets on exit.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
NPCX WIMU CR_SIN is used to wake up soc from NPCX sleep power state.
The wake-up IRQ enabled when UART init. It causes the wake-up IRQ to
generate many extra interrupt events, which causes the system too busy
to handle other events. This PR moves the UART wake-up IRQ enabling
from UART init to npcx_power_enter_system_sleep() to avoid the
interrupt storm.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Set the defalut value of SYS_CLOCK_HW_CYCLES_PER_SEC Kconfig option
from the Device Tree. The `clock-frequency` property of the DT cpu@0
node is a single source of truth defining the CPU frequency. This is
the value used e.g. by all Atmel drivers.
For Atmel SAM family CPU clock is currently the only supported system
clock source. Ensure that kernel understanding of the hardware clock
frequency is the correct one.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Add flash driver for it8xxx2. The driver can implement
flash read, write and erase that will be mapped to the
ram section for executing.
TEST="flash write 0x80000 0x10 0x20 0x30 0x40 ..."
"flash read 0x80000 0x100"
"flash erase 0x80000 0x1000"
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
MPS2 AN521 is a dual (Cortex-M33) core where the two cores
have different capabilities. E.g CPU0 implements TrustZone-M,
while CPU1 implements the FPU. Therefore we introcude separate
Kconfig symbols for the two SoC variants, and use these to
select the different Cortex-M capabilities. We also update
the definitions of __MPU/FPU/SAU/DSP variant in soc.h to make
them get the value from the Kconfig settings, directly.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Adding support for beagleV Starlight board based on Starfive JH7100
SoC. It's a base support, no drivers other than uart has been tested.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
This CL introduces six properties, clock-frequency, core-prescaler,
apb1/2/3/4-prescaler in pcc (Power and Clock Controller) node to
configure clock settings. It also removed the original Kconfig options
used for the same purpose.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Rename OSC_CLK as OFMCLK to meet npcx datasheet. The Oscillator
Frequency Multiplier Clock (OFMCLK), which is derived from
High-Frequency Clock Generator (HFCG), is the source clock of cortex-m4
core and most of NPCX hardware modules.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
We should gurantee that we do not use SRAM during Zephyr early
boot, until SystemInit has returned. This commit aims to ensure
that SystemInit will be branched to, without first pushing args
to stack, even when no optimizations are selected. We chose to
define z_platform_init in assembly directly (instead of using
inline assembly) as it appears to be a cleaner design.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Use a common implementation for z_platform_init
in nRF SoC family. The implementations are
identical, so no need to maintain separate
identical versions of them. The commit does not
introduce behavioral changes.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The was a missing comma in the DEVICE_DT_INST_DEFINE macro and the
SAME71 HAL tweaks the name of a struct so we have to work around that.
Fixes#36095
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This is a follow-up to commit 60d9988401.
Add a third option for the HFXO capacitance that keeps the default
value of the XOSC32MCAPS register untouched. The message in the above
commit incorrectly claimed that external load capacitors for HFXO
(the reset value of the XOSC32MCAPS register) was the configuration
in effect before. In fact, the register value was modified during
the device trimming in the SystemInit() function to use the internal
capacitors, and that is the configuration required for proper RADIO
operation on nRF5340 DK, for instance.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Align cavs25 with cavs15/18 and add memory segment for uncached mapping
of the SRAM to linker script. Assign sections to uncached and cached
segments as done in cavs15/18.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The macros are used to get the pin(s) of a given driver instance. Add
_INST prefix to match convention used by the devicetree.h. The original
macros can now be used to obtain pin(s) of an arbitrary device instance
identified by the nodelabel.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Configures flexcomm2 to operate in USART mode and enables the associated
peripheral clock and pinmuxes. This instance is attached to the Arduino
serial header pins and can be used for Bluetooth serial HCI with a
frdm_kw41z or other BLE controller shield.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Configures flexcomm4 to operate in USART mode and enables the associated
peripheral clock and pinmuxes. This instance is attached to the Arduino
serial header pins and can be used for Bluetooth serial HCI with a
frdm_kw41z or other BLE controller shield.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Switch from using internal 6pf to internal 7pf load capacitor for LFXO.
Use a default clock accuracy of 50PPM as this matches lab results.
50PPM should be sufficient for common operating temperatures of
25degC +- 15.
Signed-off-by: Johan Stridkvist <johan.stridkvist@nordicsemi.no>
Always source the Zephyr base soc and shield (board root) Kconfigs
directly from Kconfig instead of generated Kconfig files.
This has the benefit that it is no longer necessary to generate Kconfig
files to source SoC root and shield (board root) when no custom roots
are provided.
Also this cleans up the doc/CMakeLists.txt and ensures that the
doc/CMakeLists.txt is not getting out of sync with the Kconfig.cmake.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
To support west OpenOCD path image flashing, this generates an npcx hex
image from the npcx BIN image. Moreover, this also changes the name of
npcx output image by CONFIG_KERNEL_BIN_NAME.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Create the pinmux phandle to the ADC driver node in the
devicetree. When the pinmux_pin_set function in
adc_it8xxx2_channel_setup can refer to the setting of
this phandle. It is more flexible to use.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
NPCX7 variants allocate code RAM either at 0x10070000 or 0x10090000.
The MPU requires addresses and region sizes to be aligned, so the
generic cortex_m/arm_mpu_regions.c results in an ineffective setup with
the addresses above.
This adds a custom mpu_regions setup for the npcx7, which covers both
available sizes, resulting in these two possible setups:
- 192kB devices
Code ram: 0x10090000 to 0x100bffff
MPU region: 0x10080000 to 0x100bffff (256k)
- 320kB devices
Code ram: 0x10070000 to 0x100bffff
MPU region 0: 0x10040000 to 0x1007ffff (256k)
MPU region 1: 0x10080000 to 0x100bffff (256k)
In both cases MPU data RAM setting is from 0x200c0000 to 0x200cffff,
matching the generic Cortex-m setup.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add Kconfig options that allow configuration of optional internal
load capacitors for the high-frequency (HFXO) and low-frequency
(LFXO) crystal oscillators in nRF5340.
Default settings used for the new options are those that have been
in effect so far, i.e. external load capacitors for HFXO and 6 pF
internal capacitance for LFXO.
This commit also adds missing SOC_ENABLE_LFXO option dependency on
!TRUSTED_EXECUTION_NONSECURE.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This CL adds the support for npcx9m3f and npcx9m6f chips in ecst.py
script which generates the NPCX firmware header.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL replaces macros for miwu multi-registers' offset with internal
inline functions. This CL also uses soc series definitions to
distinguish the layout of miwu multi-registers between different npcx
series.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL adds the soc drivers for npcx9 series. There are two soc part
numbers, npcx9m3f and npcx9m6f, are introduced. We also move soc family
configurations from /nuvoton_npcx/npcx7/Kconfig.soc to
nuvoton_npcx/Kconfig.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
In npcx9, the number of pinmux registers (DEVALTx) is more than 16. We
need to extend the "group" member in the struct npcx_ALT to configure
the pinmux settings in npcx9.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL moves power policy source file for all npcx series to common
folder. It also abstracts the sources for checking register structures
to common/registers.c to avoid the duplicated sources in the later npcx
series.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL replaces series-prefix "npcx7-" with family-"npcx-" for npcx dts
nodes such as 'espi-vws-map' and 'miwus-int-map'. Since we plan to
introduce the npcx9 and later series, adding a new node such as
npcx9-espi-vws-map for each series is more complicated and not
necessary.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Commit f5c6afeccb attempted to avoid
accessing lpc55xxx flash registers in nonsecure mode by conditionalizing
part of the SoC clock initialization routine on whether the flash driver
was enabled. This caused secure applications without the flash driver
enabled (e.g., hello_world on lpcxpresso55s69_cpu0) to not boot or show
any console output. Fix this by changing the condition to depend on
whether we are building a nonsecure image.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
When we link in crtbegin.o for C++ exception support we end up pulling
in the .tm_clone_table section. We need to update the linker scripts
to handle this. soc/xtensa/sample_controller/linker.ld was already
updated, this fixes the others.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Set `ROM_START_OFFSET` for SAMD5X series to match the value
calculated in the linker file after forced alignments in
`vector_table.ld`.
Signed-off-by: Arvin Farahmand <arvinf@ip-logix.com>
Zephyr kernel masks interrupts before calling the SoC PM
sleep entry point. On the Cortex-Mx family this prevents
wake from peripheral interrupts. The SoC PM layer requires
interrupts to wake the SoC and must prevent the CPU from
vectoring to an interrup until PM exit. The SoC does this
by setting ARM NVIC PRIMASK to 1 and BASEPRI to 0. On
return to the kernel SoC sets PRIMASK to 0 allowing ISR's
to fire. In addition the MEC HW only clears its peripheral
sleep enables if the CPU vectors to an ISR. On wake we
clear the MEC PCR sleep control register which clears all
the peripheral sleep enables so peripherals will be active
before exiting the SoC PM layer.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Fixes part of: #32448
This commit updates the CMake CMAKE_CXX_LINK_EXECUTABLE to include
crtbegin.o and crtend.o at the right locations when linking with gcc.
It also updates linker scripts to ensure proper location of the
exception header frame sections.
This ensure proper handling of exceptions for those architectures
- x86
- xtensa
- riscv32
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Remove (disabled) MPU support for the NXP Kinetis K2x. At least the
MK22F51212, which is the only K2x supported by Zephyr so far, does not
contain an MPU.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Reduce the length of the Kconfig defines related to
null-pointed dereference detection in Cortex-M.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Increase FLASH_PAGE_ERASE_MAX_TIME_US of cpunet to be the same as the
value of cpuapp; FLASH_PAGE_ERASE_MAX_TIME_US is the execution window
duration when doing the flash operation synchronously along the radio
operations (SOC_FLASH_NRF_PARTIAL_ERASE not enabled); the previous
FLASH_PAGE_ERASE_MAX_TIME_US value of cpunet is lower than required.
Signed-off-by: Lang Xie <lang.xie@nordicsemi.no>
When using the LPC55S69 with TF-M, the ROM-based flash
controller is restricted to the secure processing environment
to prevent NS access to flash memory. Any access to the
flash controller will cause a secure fault, and the NS
application will halt execution.
This commit disables access to the IAP flash peripheral
when using the lpcxpresso55s69_ns target, enabling TF-M
to restrict IAP access to the secure side.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
some mwdt compiler options not support cmake function
check_c_compiler_flag, let's add mwdt compiler options for
hsdk boards without check.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
arcmwdt toolchain has various pre build libraries, we can find it in
path: {METAWARE_HOME}/lib, and it will use av2em lib by default.
it's OK for em boards, but not suitable for hs boards. I have tested
hs38_full library for hs boards, it's OK. let's use it.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
NPCX series ROM code changes the chip basic setting by firmware binary
header for loading the firmware from flash to RAM. Add the following to
improve the ec firmware header setting:
- Move the ECST which generates the firmware binary header to NPCX
common folder. All the following NPCX series chips can use this.
- Add ecst setting option in Kconfig.
Signed-off-by: Yuval Peress <peress@chromium.org>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Z_ITERABLE_SECTION_ROM symbols were empty, meaning
that those symbols were not taking place in the linker script.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This CL limits the compiler to consider the eSPI/LPC host wake-up
functions, such as npcx_host_disable_access_interrupt and
npcx_host_disable_access_interrupt, only if eSPI bus module is selected.
Otherwise, we will encounter compiler errors if the communication
between host and ec is via SPI, not eSPI/LPC bus.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit fixes the ADC driver flow. And add internal
reference voltage to ADC driver API. And correct the
data buffer that only need to store raw data.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Set TRACE_MODE to asynchronous and enable trace output pin.
Add soc_config.c in stm32 soc direcotry.
Fixes#34342
Signed-off-by: Andrés Manelli <am@toroid.io>
NPCX clock has some limitations about the frequency range &
synchronization between core clock & other clocks. Add build assert to
check whether NPCX clock setting correct. This also fixed soc_clock.h
to consist with datasheet.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Cleanup along the same lines as the last change to APL/up_squared.
Make sure all hardware configuration is at the board level where it
belongs and not in the soc, don't play games with defaulting timer
drivers. Unify the configuration where possible and make it clearer
which setting goes with which driver.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The addition of a timer driver made a messy situation worse. Move
board-level configuration like clock rates and dividers into the board
and don't try to default it in the soc. Make it clear which kconfig
goes with which driver. Likewise don't try to do driver selection in
the soc, the board (or app) is in a better position to choose.
Also clean up and better unify the up_squared 32/64 bit settings.
Really only CONFIG_BOARD_NAME needs to care about the difference
between these devices.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add QEMU board with single core ARCv3 HS6x 64 bit CPU
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Add the missing .cached section on cAVS 2.0 and 2.5 to fix
compiler warnings.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
PLATFORM_RESET_MHE_AT_BOOT and
PLATFORM_DISABLE_L2CACHE_AT_BOOT have to be defined on cAVS 1.8
too, without them secondary cores cannot be used.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
uncache_to_cache(), cache_to_uncache() and is_uncached() macros
are currently unused in Zephyr, besides the former two are
dangerous because they add and subtract an offset instead of
masking and unmasking a bit, which can lead to wrong addresses
if applied repeatedly. Remove these macros for now, we can
re-add them later if needed in their fixed versions.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Currently only cAVS 1.5 Kconfig selects ARCH_HAS_COHERENCE,
which is wrong. cAVS 1.8, 2.0 and 2.5 have to select it too.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Added support for GPIO driver for Intel Elkhart Lake
board.
The GPIO driver will support pin value read/write operations,
pin direction and interrupt configuration. ACPI enumeration
support and support for different GPIO communities is also
present.
Verified on ehl_crb.
Signed-off-by: U Divya <u.divya@intel.com>
spi1 and i2c0 share peripheral ID number 3.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
UART0, TWI0, and SPI0 have different peripheral IDs (2, 3, and 4
respectively) on this SoC and therefore should not be mutually
exclusive to use.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
There is a choice to log btmon logs over UART or RTT.
You can choose number of RTT buffer, set its name and size.
Replaced CONFIG_BT_DEBUG_MONITOR with CONFIG_BT_DEBUG_MONITOR_UART
for UART usage and CONFIG_BT_DEBUG_MONITOR_RTT for RTT.
Signed-off-by: Magdalena Kasenberg <magdalena.kasenberg@codecoup.pl>
SMP support on cAVS is implemented by using uncached addresses
for all writable data sections except for stack, i.e. for .data,
.bss and some other specialised ones. So far that has been
implemented for cAVS 1.5. This patch does the same for cAVS 1.8.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
According to RM0041.pdf clock tree for stm32f100xx devices is
different from both STM32F10X density and connectivity lines devices,
but is a combination of both.
Rework symbols definitions so that STM32F100xx is neither of those
and uses:
- CLOCK_STM32_PLL_MULTIPLIER as on SOC_STM32F10X_DENSITY_DEVICE
- CLOCK_STM32_PLL_PREDIV1 as on SOC_STM32F10X_CONNECTIVITY_LINE_...
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Fixes an issue with mcuboot where the SoC will freeze when the dpll is
disabled since `atmel_samd_init` was already run in the bootloader.
Signed-off-by: Abram Early <abram.early@gmail.com>
We need to clear interrupt status, before we enable the interrupt.
So I let ite_intc_isr_clear() to be global function.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Allow SMP processing for SOF on ADSP. Note, that after this
SOF will build with SMP support enabled on all cAVS versions,
but secondary cores will remain disabled unless an SMP
topology is loaded by the host.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
With SOF secondary cores are booted later at run-time instead
of the traditional simultaneous booting of all the cores.
Adjust arch_start_cpu() to make that possible.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
To disable the IDC interrupt on the interrupt controller a bit
must be set in the MSD register instead of clearing the bit in
the MCD register, which has no effect.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
irq_enable() should be called with the composite IRQ code as its
argument, not just the Xtensa proper part of it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
BT support requires lots of PROVIDE calls that cannot
be added into this linker file. All necessary includes
were moved into hal module to proper handled as needed.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
During configuring the low-voltage power supply of IO pads, the npcx
GPIO driver needs to set the related PORTx_OUT_TYPE bit to 1, i.e.
select to 'Open Drain IO type', also. This CL provides a mechanism that
configuring these bits via 'def-lvol-io-list' node automatically in case
the flag of gpios that have been configured to low-voltage power supply
doesn't contain GPIO_OPEN_DRAIN.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Move the STM32F0 specific ram vector table sections into a dedicated
linker snippet included by the new `SRAM_VECTOR_TABLE` symbol.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add a new Kconfig symbol that explicitly controls whether the vector
table should be placed in RAM. This eliminates the side effect of
`IS_BOOTLOADER` controlling vector table location. Making the condition
a positive assertion also allows the config to be used in CMakeLists
conditions (`zephyr_linker_sources_ifdef()`, etc).
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
The NPCX power management code gets a compile error if CONFIG_PM is
enabled but CONFIG_ARM_MPU is disabled.
Signed-off-by: Keith Short <keithshort@google.com>
It was found that npcx7 series' GPIOs which support low-voltage power
supply, there is an excessive power consumption if they are selected to
low-voltage mode and their input voltage is 1.8V.
To avoid this excessive power consumption, this CL suspends the
connection between IO pads and hardware instances before ec enters deep
sleep mode. Then restore them after waking up.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add support for the FVP Base RevC 2xAEMv8A board to be emulated using
the same FVP. For now the virtual platform is only exposing one core and
the basic set of peripherals (GICv3, ARM arch timer, PL011, etc...).
INFO - Total complete: 256/ 256 100% skipped: 933, failed: 0
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The NATIVE_TASK macro uses macros from the toolchain header.
Instead of relaying on the header to be included by somebody else,
include it explicity here.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Fixes#29915.
Implements the memory layout and MPU configuration for Ethernet buffers
for STM32H7 controllers as recommended by ST. 16 KB of SRAM3 are
are reserved for this. The first 256 B are for the RX/TX descriptors and
configured as strongly ordered, shareable memory. The rest is for RX/TX
buffers and configured as non cacheable memory. This configuration is
automatically applied for H7 chips if the SRAM3 memory is enabled in the
device tree.
Signed-off-by: Mario Jaun <mario.jaun@gmail.com>
Optionally configure Kconfig SYS_CLOCK_HW_CYCLES_PER_SEC using
clock-frequency provided by dt if sysclk node is enabled
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
To allow transition to device tree based clock configuration on
stm32 targets, rework clock_control driver to use intermediate
STM32_ macros initially defined as the equivalent Kconfig macros
for now.
Propagate the change in all code using these macros.
The reason to introduce these new macros instead of configuring
Kconfig flags using dt kconfigfunctions is that we'll need
to be able to inform users that Kconfig flags are deprecated
once the whole family conversion is done, to encourage
out of tree users to adopt this new configuration scheme.
Note: For now STM32H7 series and code is excluded.
This is the same for some series specific code such as
PLL mul/div for L0/L1 and XTRE prescaler on F1 series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This CL adds a override mechanism for pwm module's input clock source
assignment. If the 'clock-bus' property exists, the NPCX_DT_PROP_ENUM_OR
macro function will return an enum upper token value. Otherwise, it
expands to default value in 'clocks' property.
For example, if the users want to select LFCLK as pwm0's input clock,
ths node can be overridden by adding 'clock-bus' property with an enum
string, "NPCX_CLOCK_BUS_LFCLK".
&pwm0 {
status = "okay";
clock-bus = "NPCX_CLOCK_BUS_LFCLK";
};
Signed-off-by: Keith Short <keithshort@google.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Kconfig symbol NFCT_PINS_AS_GPIOS may be defined for all
Nordic nRF SoCs that have the NFCT hardware, so we move
the option definition in nRF common Kconfig file. Also,
we correct the help text to reflect that nRF52 series DKs
and nRF5340 DK have different pins for NFC.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds the soc config for the STM32F031k6 and STM32F031X6.
Add the STM32F031k6 as choice to the Kconfig.soc.
Signed-off-by: Sebastian Schwabe <sebastian-schwabe@gmx.de>
When BT and WiFi coexists, IRAM usage increases a lot.
Add configuration that allow wifi symbols
to be placed in flash, freeing space in IRAM.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add register address including external timer and watchdog(ETWD),
general control(GCTRL), serial peripheral interface(SPI).
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This change enables A, C, D, E, G, H, I, J, K, and L groups,
and fix gpio interrupt function.
This change also pull (and rename) dt-bindings/irq.h to
dt-bindings/interrupt-controller/ite-intc.h, because it is
chip-specific.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Ifee039981c2cc4cf5980e663702a9921e629fc1e
NPCX host access IRQ enables before entering deep sleep. The pending
bit lets chip wake up from sleep immediately. Clear host access IRQ
pending bit before enabling.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
With some additional macro-magic we can remove the CMake-based header
file template feature, and instead take advantage of the usual
DT_INST_FOREACH_STATUS_OKAY() macro.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Most of the Renesas RCar Gen3 based SoC contains a Cortex R7
processor.
This processor has access to the same memory mapped devices than
the Cortex-A5x cores.
- CPU operates upto 800MHz
- Can use ram area from 0x40040000 to 0x42000000
- Has 512 interrupts on GIC-400 compliant with Arm GICv2
Add support for r8a77951 as first SoC of this series which is also
known as H3 ES2.0 and is present present on different boards such as
Salvator and R-Car Starter Kit(H3ulcb).
This first SoC definition is just enough to print Hello World in a
ram console.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
With some additional macro-magic we can remove the CMake-based header
file template feature, and instead take advantage of the usual
DT_INST_FOREACH_STATUS_OKAY() macro.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
xthal_window_spill call has to be placed into IRAM
in order to allow flash cache disabled operation, otherwise
it will crash.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The bootloader application itself should contain the IVT/DCD
in the header, but the chainable application doesn't.
The ROM_START_OFFSET defaults to 0x400 otherwise the linker
alignment isn't taken into account.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
This change allows writing to the flash while running in XIP mode,
and enables mcuboot or NVS settings to be used on i.MX RT socs.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Move the definition of the two IPC RAM blocks from `#define`'s in family
linker scripts to proper devicetree nodes. Use the devicetree nodes to
generate the memory regions.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
The final else was missing in the if ... else if ... construct.
This commit adds a non-empty else {} to comply with coding
guideline 15.7.
Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
This commit is about the it8xxx2 analog to digital converter
driver. Support 8 channels ch0~ch7 and 10-bit resolution.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Fixed the name of nodes in in espi-vw, miwu-wui, and miwu-int
device-tree node. This CL fixed missing nodes in CL d3a94fa8ab.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
When ARM_MPU is defined, the MPU drivers will be built into the final
zephyr target.
Signed-off-by: Haibo Xu <haibo.xu@arm.com>
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Add several default mpu regions(flash/sram/sram_text/sram_ro) for
the Armv8-R aarch64 based Soc.
These regions will be initialized as static region during system boot.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Add essential files to create a new soc.
Introduce a new type of soc series named fvp_aemv8r.
Add a new soc named fvp_aemv8r_aarch64.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Change the GPIO_MMIO32_INIT to take a devicetree node since we want
to use DEVICE_DT_DEFINE. This makes it so that code using
GPIO_DT_SPEC_GET works correctly with GPIO controllers that utilize
GPIO MMIO32.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
With this patch, the UCPD1 _CC1 and _CC2 pins
are disabling the USB Type-C and Power Delivery Dead Battery.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
With this patch, the UCPD1 _CC1 and _CC2 pins
are disabling the USB Type-C and Power Delivery Dead Battery.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
With this patch, the UCPD1 _CC1 and _CC2 pins
are disabling the USB Type-C and Power Delivery Dead Battery.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This CL adds support for console expired mechanism. It implements the
notification to power management module that the module for console is
in use. If the interval that module doesn't receive any input message
exceeds CONFIG_SOC_POWER_CONSOLE_EXPIRED_TIMEOUT, the power management
module is allowed to enter deep sleep mode. This mechanism gives a
window in which the users can organize console input.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
NXP ls1046a is SoC includes the following functions and features:
1. Four 32/64-bit Arm v8 A72 CPUs
2. Cache coherent interconnect (CCI-400)
3. One 32/64-bit DDR4 SDRAM memory controller with ECC
4. Peripheral interfaces include DPAA network, PCIe, USB, SPI,
GPIO, UART, SDHC, IFC, LPUART ...
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Fixed the name of nodes in device-tree files by following rules:
If object is 'phandles', use underscores for object name.
If not, such as 'node' or 'property', use hyphens for object name.
This CL also applies normal style for all nodes in npcx device-tree
files.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The Write Protect pin of the internal SPI flash can be controlled by
WP_IF bit in DEV_CTL4 register. Add functions to set/get the status of
WP pin.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I8a0ce131f006f919a3b38a65722d0d312314ff0a
Initially the flexspi device only supported a flash driver for
external NOR flash. As the controller supports HyperBus devices,
which can be either volatile or non-volatile, the driver iss moved
to drivers/memc.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
soc/arm/st_stm32/CMakeLists.txt already has a
zephyr_include_directories(common) so including in again
soc/arm/st_stm32/common/CMakeLists.txt is redudant.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Use a combination of fixed-clock and fixed-factor-clock devicetree
nodes for describing the clock dividers/multipliers of the NXP Kinetis
System Clock Generator (SCG) present in the KE1xF SoC series.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Split ARM and ARM64 architectures.
Details:
- CONFIG_ARM64 is decoupled from CONFIG_ARM (not a subset anymore)
- Arch and include AArch64 files are in a dedicated directory
(arch/arm64 and include/arch/arm64)
- AArch64 boards and SoC are moved to soc/arm64 and boards/arm64
- AArch64-specific DTS files are moved to dts/arm64
- The A72 support for the bcm_vk/viper board is moved in the
boards/bcm_vk/viper directory
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The compiler shows the array bounds warning message for some boards
which don't set the PSL function.
Change npcx_pinctrl_psl_input_asserted() input parameter from int to
uint32_t to fix it.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
The low power states 0∕1∕2 are added to the stm32wb.
The substate-id is mapping the same Zephyr power state.
They correspond to the stm32wb low power stop0/1/2 modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The debug config will let the clocks active in STOP mode
at init.
The substate-id is mapping the same Zephyr power state.
Plus a minor fix in the Kconfig.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The low power modes are available on the stm32l5 soc
with the mcu STOP0/1/2 modes, depending on the CONFIG_PM
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The low power states 0∕1∕2 are added to the stm32l4.
The substate-id is mapping the same Zephyr power state.
They correspond to the stm32l4 low power stop0/1/2 modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Hex firmware file is flashed by default if JLink is used. Since all
of the SiLabs dev boards have an on-board JLink, enable generating hex
file.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
This CL introduces the implementation of configurating PSL input pads
and setting PSL_OUT to inactive level for ultra-low power consumption.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces the Power Switch Logic (PSL) pads which detect the
wake-up events and turn on/off core power supply (VCC1) for ultra-low
-power consumption in npcx device-tree file.
By adding PSL input-pad objects, psl_in1, psl_in2, and so on, into
'psl-in-pads' property and configuring their 'flag' properties, the
related driver will configure them via soc specific functions later.
For example, if PSL input 1 pad that is plan to detect a 'falling edge'
event, this property should be:
vsby-psl-in-list {
psl-in-pads = <&psl_in1>;
};
And the flag property in psl_in1 should change to
&psl_in1 {
flag = <NPCX_PSL_FALLING_EDGE>;
};
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
PWR clock is required for various operations.
It is enabled by default in clock control driver,
but disabled at clock init.
It appears soc init is run after clock control driver init
and hence PWR is disabled to to this piece of code at
soc init level.
Don't disable PWR here.
(But keep PWR clock enable in case of ...).
A whole clock clean up will be required later on,
but waiting for that to happen, this is the safest we can do.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This config CPU_CORTEX_M_HAS_DWT, is to avoid the
pragma message "Null-Pointer exception detection cannot
be configured on un-mapped flash areas"
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Don't allow user to choose CPU_ARCEM / CPU_ARCHS options
but select them when exact CPU type (i.e. EM4 / EM6 / HS3X/ etc)
is chosen.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
The AN547 is a Soft Macro Model implementation of the SSE-300 subsystem
with Ethos-U55 and Cortex-M55 components targeting the MPS3 board.
The SoC support is based on the AN521 MPS2+ support that already exists
in Zephyr.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In NPCX chips, System Configuration module can configure not only
pinctrl but also misc. functionality such as glue and flash write
protection. This change moves the scfg driver from the pinctrl folder
to soc/arm/nuvoton_npcx/common and renames it to avoid confusion.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This CL solves an interrupt storm caused by plenty of host access
messages when system is in S0. It only turns on the host access
interrupt before ec enters sleep and turns it off after leaving
sleep.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add SoC support to enable Cypress PSoC-6 pinctrl. This add devicetree
macros to handle pinctrl nodes and SoC GPIO methods to configure pins.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
CORTEX_M_SYSTICK should be disabled if LPTIM is selected.
Current implementation is not efficient to do so.
Rework the way the dependency is stated.
Fixes#33342
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The sentry symbols that mark the ends of the newlib heap area were
being placed in cached memory, which violates the coherence rules.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add GPIO driver for QuickLogic EOS S3 SoC.
Co-authored-by: Jan Kowalewski <jkowalewski@antmicro.com>
Signed-off-by: Wojciech Tatarski <wtatarski@antmicro.com>
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
In some stm32 series systick was disabled in order to
allow alternate use of lptim timer as kernel low power ticker.
Doing this, dts based definition of CORTEX_M_SYSTICK Kconfig symbol
is disabled and CORTEX_M_SYSTICK was redefined with 'default y'
in stm32 soc files which makes things more complex to handle to
alternate with LPTIM activation.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Since the removal of Quark-based boards, there are no user of
Minute-IA. Also, the generic x86 SoC is not exactly Minute-IA
so change it to use a fairly safe CPU_ATOM.
Fixes#14442
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This CL prevents changing data content in the write function of host
interface by declaring it as constant pointer.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Turns out that the user can configure the "zephyr.elf" name via
kconfig to be "something_else.elf" instead. And there's a test the
does this. Use the right variable; don't hardcode.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This was added early when we had (somewhat oddly) a log subsystem
backend but not a printk char_out hook. Now we have one backend that
works with both. No need, and this fixes build errors with a handful
of tests that specify LOG_MINIMAL (LOG_PRINTK requires the full log
subsystem and doesn't work with MINIMAL).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
In commit efa05d1e42da ("soc/intel_adsp: Put initial stack into the
CPU0 interrupt stack") the "_end" symbol was accidentally removed from
the linker script. Newlib needs this to size its heap.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
All users of ATMEL_SAM0_DT_INST_DMA_NAME are now using
ATMEL_SAM0_DT_INST_DMA_CTLR so we can remove the macro.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a macro similar to ATMEL_SAM0_DT_INST_DMA_NAME but instead
provides the devicetree node back via DT_INST_DMAS_CTLR_BY_NAME
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Use kinetis SIM clock divider options set in device tree
instead of hardcoded values.
The kl25z device tree did not previously define a MCG node.
This has now been added with the general "nxp,kinetis-mcg"
binding.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Use kinetis SIM clock divider options set in device tree
instead of kconfig.
The kv5x device tree originally used the undefined
"nxp,kv58-mcg" binding for the MCG node. This has been
replaced by the general "nxp,kinetis-mcg" binding.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Use kinetis SIM clock divider options set in device tree
instead of kconfig.
Both the kw40z and kw41z device tree originally used an
undefined "nxp,kw41z-mcg" binding for the MCG node.
This has been replaced with the general "nxp,kinetis-mcg"
binding instead.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
SYSCLK_DEFAULT_IOSC_HZ and BUSCLK_DEFAULT_IOSC_HZ are
not used anywhere in the tree and can be removed
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
The Xtensa L1 cache layer has straightforward semantics accessible via
single-instructions that operate on cache lines via physical
addresses. These are very amenable to inlining.
Unfortunately the Xtensa HAL layer requires function calls to do this,
leading to significant code waste at the calling site, an extra frame
on the stack and needless runtime instructions for situations where
the call is over a constant region that could elide the loop. This is
made even worse because the HAL library is not built with
-ffunction-sections, so pulling in even one of these tiny cache
functions has the effect of importing a 1500-byte object file into the
link!
Add our own tiny cache layer to include/arch/xtensa/cache.h and use
that instead.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Instead of passing the crt1 _start function as the entry code for
auxiliary CPUs, use a tiny assembly stub instead which can avoid the
runtime testing needed to skip the work in _start. All the crt1 code
was doing was clearing BSS (which must not happen on a second CPU) and
setting the stack pointer (which is wrong on the second CPU).
This allows us to clean out the SMP code in crt1.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Zephyr's normal architecture is to do all initialization in the
interrupt stacks. The CAVS code was traditionally written to start
the stack at the end of HP-SRAM, where it has no protection against
overlap with other uses (e.g. MP startup used the same region for
stacks and saw cache collisions, and the SOF heap lives in this area
too). Put it where Zephyr expects and we'll have fewer surprises.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The kernel passes the CPU's interrupt stack expected that it will
start on that, so do it. Pass the initial stack pointer from the SOC
layer in the variable "z_mp_stack_top" and set it in the assembly
startup before calling z_mp_entry().
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There's no need to muck with the cache directly as long as we're
careful about addressing the shared start record through an uncached
volatile pointer.
Correct a theoretical bug with the initial cache invalidate on the
second CPU which was actually doing a flush (and thus potentially
pushing things the boot ROM wrote into RAM now owned by the OS).
Optimize memory layout a bit when using KERNEL_COHERENCE; we don't
need a full cache line for the start record there as it's already in
uncached memory.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The multiprocessor entry code here had some bits that look to have
been copied from esp32, including a clumsy stack switch that's needed
there. But it wasn't actually switching the stack at all, which on
this device is pointed at the top of HP-SRAM and can stay there until
the second CPU swaps away into a real thread (this will need to change
once we support >2 CPUS though).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The trace output layer was using this transformation already, make it
an official API. There are other places doing similar logic that can
benefit.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There was a bunch of dead historical cruft floating around in the
arch/xtensa tree, left over from older code versions. It's time to do
a cleanup pass. This is entirely refactoring and size optimization,
no behavior changes on any in-tree devices should be present.
Among the more notable changes:
+ xtensa_context.h offered an elaborate API to deal with a stack frame
and context layout that we no longer use.
+ xtensa_rtos.h was entirely dead code
+ xtensa_timer.h was a parallel abstraction layer implementing in the
architecture layer what we're already doing in our timer driver.
+ The architecture thread structs (_callee_saved and _thread_arch)
aren't used by current code, and had dead fields that were removed.
Unfortunately for standards compliance and C++ compatibility it's
not possible to leave an empty struct here, so they have a single
byte field.
+ xtensa_api.h was really just some interrupt management inlines used
by irq.h, so fold that code into the outer header.
+ Remove the stale assembly offsets. This architecture doesn't use
that facility.
All told, more than a thousand lines have been removed. Not bad.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
New power states have more granularity than deep sleep and sleep
states. Just get rid of this and keep the same behavior for now.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Maximum GIC SPI is 228, so maximum INTID is 228 + 32 = 260.
So, _sw_isr_table needs to support 260 entries
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Update register addresses and NVIC/GIC interrupt numbers
according to the latest viper RTL version.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
This patch adds weak sys_arch_reboot() function to avoid build error
with CONFIG_REBOOT=y. Some SoC has already had own reboot function
but others (Ex. qemu boards) faced buld error.
- openisa_rv32m1: Not change
- riscv-ite: Do nothing, remove and use arch/riscv function
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
There is no strict reason to use assembly for the reset routine. Move as
much code as possible to C code using the proper helpers.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The name for registers and bit-field in the cpu.h file is incoherent and
messy. Refactor the whole file using the proper suffixes for bits,
shifts and masks.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Enable the driver for the Kinetis Digital-to-Analog (DAC) modules
present in the NXP Kinetis K2x SoC series.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Add some helper macros that will be convenient to use from device
drivers for accessing and error checking pin mux information in the
devicetree:
- NRF_DT_PSEL(): get a PSEL value out of the DT from either a
'foo-pin' or a 'foo-gpios' style property.
- NRF_DT_PSEL_CHECK_NOT_BOTH(), NRF_DT_PSEL_CHECK_EXACTLY_ONE():
helpers for checking that a given devicetree is OK according to
different criteria for setting PSEL properties (NAND or XOR on
whether the properties exist, respectively).
See comments in the patch for more details.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
ARC mpu version used a wrong number 3, could cause conflict in future.
This commit fix this issue to version number 4.
Signed-off-by: Yuguo Zou <yuguo.zou@synopsys.com>
Add the declaration and check of debug interface register.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: Ib8ecd53f1d6139613f39243aee83bdd75a30f5be
In NPCX7 series, it contains two tachometer (TACH) modules that contains
two Independent timers (counter 1 and 2). They are used to capture a
counter value when an event is detected via the external pads (TA or
TB).
The CL also includes:
— Add npcx tachometer device tree declarations.
— Zephyr sensor api implementation for tachometer.
— Enable "tach1" device in npcx7m6fb.dts for testing.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Since the uart device clock will be stopped after ec entered sleep or
deep sleep state and restore its clock automatically, there is no need
to implement code for suspending and resuming devices manually.
The driver still needs to check the current status of uart device when
it wants to change its power state to LOW or SUSPEND power state. It is
crucial to forbid ec enters sleep or deep sleep state when uart device
is busy with transmitting data. Or we will observe broken characters on
the uart console.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces power management driver that improves the efficiency
of ec operation by adjusting the chip’s power consumption to the level
of activity required by the application in npcx series.
The following list summarizes the main properties of the various chip
power states. Please refer the power.c file for more detail.
Main power states in npcx series include:
- Active: Core, RAM and modules operate at the clocks generated by PLL.
- Idle: Enter this state when the Core executes WFI or WFE instruction.
- Sleep: clock is stopped for most of modules but PLL is enabled.
- Deep Sleep: As Sleep mode but PLL is disabled.
- Standby: All power rails are turned off besides standby and battery
power rails.
And this CL implements one power state, PM_STATE_SUSPEND_TO_IDLE, with
two sub-states for Zephyr power management system.
Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency
time is greater or equal to 1 ms
Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency
time is greater or equal to 201 ms
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces a kernel device driver implemented by the internal
64/32-bit timers in Nuvoton NPCX series. Via these two kinds of timer,
the driver provides an standard "system clock driver" interface.
It includes:
- A system timer based on an ITIM64 (Internal 64-bit timer) instance,
clocked by APB2 which freq is CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
- Its prescaler is set to 1 and provide the kernel cycles reading
without handling overflow mechanism.
- A event timer based on an ITIM32 (Internal 32-bit timer) instance,
clocked by LCLK which frequency is 32KHz and still activated when ec
entered "idle/deep idle" power state for better power consumption.
- Its prescaler is set to 1 and provide timeout event mechansim.
- Compensate system timer which clock is gating for better power
consumption after ec left"idle/deep idle" power state.
This CL passed starve, timer_api, and timer_monotonic test suites.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
stm32wb and stm32l4 are devices which supports the low power
from the Kernel PM, so is the PM_DEVICE defined.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In case the policy is not available or defined by th application
the pm_policy_low_power_devices is still valid
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The clock configuration is restored by the stm32_clock_control_init
function of the clock_stm32_ll_common driver
when exiting the low power mode
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In case the policy is not available or defined by th application
the pm_policy_low_power_devices is still valid
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The clock configuration is restored by the stm32_clock_control_init
function of the clock_stm32_ll_common driver
when exiting the low power mode.
Keeping the stm32wbxx_ll_utils.h in case the PLL is used for wb.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Erratum 19 applies to earlier revisions of nRF5340 DK,
which are no longer supported in the tree, so we can
remove the code that handles it.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add Kconfig options to signify that the nRF5340
HW has support for QDEC instances. Select the
options in the nRF5340 Application core definition.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This driver missed #32228 PR that converted STM32 drivers
to use DEVICE_DT_GET for clock activation.
Due to the renaming of STM32_CLOCK_CONTROL_NAME to
STM32_CLOCK_CONTROL_NODE, driver could not compile anymore
Fix this.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Remove support for the Musca-A board. This board is rarely used, few
are available and superceded by Musca-B and Musca-S.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We assume that all x86 CPUs do have clflush instructions.
And the cache line size is now provided through DTS.
So detecting clflush instruction as well as the cache line size is no
longer required at runtime and thus removed.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The NPCX clock driver was already using devicetree, just need to make a
small tweak to use DEVICE_DT_INST_DEFINE and update NPCX_CLK_CTRL_NAME
to match the label for the "nuvoton,npcx-pcc" clock controller.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a simple pinctrl node for the IOF registers under the GPIO
controller node to be used by the pinmux driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add ESPI SAF features to the Microchip eSPI driver as
a separate file. ESPI SAF depends upon the core eSPI
driver adding the ability to attach the system SPI
flash to the EC eSPI endpoint instead of the host
eSPI controller.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
When exiting Stop mode, if system clock is MSI, MSI oscillator is
selected as wakeup from stop clock; otherwise HSI16 oscillator is
selected.
Signed-off-by: Giancarlo Stasi <giancarlo.stasi.co@gmail.com>
nxp_k2x.dtsi: Corrects Multipurpose Clock Generator binding
to utilize nxp,kinetis-mcg. Assign MCG to FlexTimer devices.
Enable FlexTimer clocks via System Integration Module clock
gate control registers.
Kconfig.defconfig.mk22f12: Enable default use of
CLOCK_CONTROL_MCUX_MCG when CLOCK_CONTROL is selected.
Signed-off-by: Ryan Holleran <rhollerar@gmail.com>
In this CL, npcx_miwu_interrupt_configure is no longer responsible for
turning the interrupt off. Although the default state of WK_EN is
disabled, the users still have the chance to configure them when WK_EN
is enabled via npcx_miwu_irq_enable(). Hence, this CL also ensures that
WK_EN is disabled before configuring them.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Simplify pm subsystem removing PM_STATE_LOCK option. Constraints API is
small and is a key component of power subsystem.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This activates spi support for this soc. Closes#26428
```tests/drivers/spi/spi_loopback``` succeeded.
Signed-off-by: Bernhard Krämer <bdkrae@gmail.com>
Add support for backup SRAM initialization found in multiple STM32
microcontrollers. Linker script facilities are also provided to make it
easy to define variables in the backup SRAM.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This was merged by mistake without being tested and is not working
properly. We need to avoid doing a BUILD_ASSERT() when the relevant
property is missing, because we can't use DT_GPIO_CTLR() on an
undefined property. Handle this with COND_CODE_1().
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Only the CAVS 1.5 linker script has full support for the coherence
features, don't advertise it on the other SoC's yet.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The default frequency for this board in Renode is 66 MHz. This needs to
be even with `SYS_CLOCK_HW_CYCLES_PER_SEC` to avoid such problems as in
the #31726 issue.
Unfortunately, the difference in these values was helpful for some tests
that are failing with 66 MHz set in both places. It created artificial
boost in certain circumstances.
The frequencies in the default Renode platform description (`.repl`)
file for MI-V were overridden with 4 MHz value that seems to be better
tolerated based on testing. The `SYS_CLOCK_HW_CYCLES_PER_SEC` was
adjusted as well.
To solve the rest of the issues, `cpu PerformanceInMips` was set to 4.
It seems tests are completed faster with such a value.
This commit fixes#31726.
Signed-off-by: Adam Jeliński <ajelinski@antmicro.com>
According to https://www.arm.com the correct spelling is now "Arm".
Change the Kconfig input prompts to comply.
Signed-off-by: Detlev Zundel <dzu@member.fsf.org>
This is a trivial patch replacing the spaces at the beginning of the
line with tabs. Otherwise checkpatch will not be happy with any
changes in here.
Signed-off-by: Detlev Zundel <dzu@member.fsf.org>
The STM32F2x was the only one of the STM32 series with a lowercase
input prompt. This looks odd in the SoC selection in 'menuconfig'.
Signed-off-by: Detlev Zundel <dzu@member.fsf.org>
Rather than Kconfig vendor symbols, select stm32 watchdog using
compatible.
So user only has to enable the requested node and set
CONFIG_WATCHDOG=y.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This CL added more additional details for KBC (Keyboard and Mouse
Controller) bus in espi_event structure. It helps the application to
handle different 8042 events in the callback function.
The format of event data for KBC 8042 protocol is:
[23:16] - 8042 event type: 1: Input buf full, 2: Output buf empty.
[15:8] - 8042 data: 8-bit 8042 data.
[0:7] - 8042 protocol type: 0: data type, 1: command type.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The network core doesn't have access to the regulators necessary to
support system power management. That has to be done on the
application core.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This reverts commit f38ba314ea.
nrf5340dk_nrf5340_cpunet doesn't support power management, but that
should be handled another way.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The soft off power state should be supported as it is closest to what
used to be deep sleep state 1, which corresponds to the device off
state supported by hardware.
Fixes#31727.
Signed-off-by: Vincent Wan <vanti.coder@gmail.com>
Based upon discussions with HW designers the 32KHz
programming sequence can be simplified. When FW writes
a value to the VBAT 32KHz Clock Enable register HW checks
if the value is the same as the current value. If the same
the HW does nothing. If different HW begins a sequence to
switch off the current 32KHz source, revert to ring oscillator,
and switch to the new source. FW should program the new value
and then spin until the PCR OSC ID PLL Lock bit goes to 1.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This commit adds minimal support for running zephyr as Xen guest. It
does not use xen PV console, which is somewhat hard to implement, as it
depends on xenbus infrastructure. Instead SBSA-compatible PL011 uart is
used.
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
A more comprehensive solution would use E820 enumeration, but we
are unlikely to ever care that much, as we intend to use demand
paging on microcontrollers and not PC-like hardware. This is
really to just prevent QEMU from crashing.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This change moves .rodata for panic handler and fatal.c into DRAM
Moves panic handler and its dependent functions into IRAM
Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
This allows to get much more reproducible results in terms of
amount of tests passed & failed.
But note it requires QEMU for ARC with icount support!
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Enables the FlexSPI flash driver on the i.MX RT SoC family and
configures the peripheral clocks accordingly. We are careful to only
configure the peripheral clocks if we are not executing in place from
the FlexSPI flash.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds a hidden config symbol HAS_MCUX_FLEXSPI selected by NXP SoCs when
the FlexSPI peripheral is present. It will be used as a dependency for a
new FlexSPI flash driver to prevent users from accidentally enabling the
driver on platforms that don't have the necessary hardware.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This targets was previously enabling PM but the code was doing nothing
because the logic was under an unsatisfied ifdef condition.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Change subsystem to use struct pm_state with substate-id instead of
using only the power state category.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Remove conditionals (PM_DEEP_SLEEP_STATES and PM_SLEEP_STATES) from
power management code. Now these features are always available when
power management is enabled.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Migrate the whole pm subsystem to use new power states information
from power_state.h and get states and residency properties from
device tree.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
A more comprehensive solution would use E820 enumeration, but we
are unlikely to ever care that much, as we intend to use demand
paging on microcontrollers and not PC-like hardware. This is
really to just prevent QEMU from crashing.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Fix kernel.common and kernel.common test cases fail due to build error
in platform intel_adsp_cavs15, 18, 20, 25.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
PSoC-6 SoC needs that user define the nvic interrupt number to bind
with the peripheral interrupt line for the Cortex-M0+ CPU. It uses
a multiplex before any NVIC interrupt line. The interrupt vector is
selected using interrupt-parent property with the intmux_chN number
reference.
Note: The PSoC-6 SoC allows that both CPUs receive the same interrupt.
A tipical use is GPIO interrupt handle and user is responsable to
define interrupt line, priority and take care of enable same peripheral
instance on both CPUs only when appropriated.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Update <soc.h> include files. This removes the unnecessary
<kernel_includes.h> file. In addition, add <sys/util.h> to
expose macros and <devicetree.h> following general standards.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Introduce a Kconfig variable that the SoC can set to indicate the
number of instances in Device Tree. This also fixes the accuracy of
the Elkhart Lake instance count where the code was previously assuming
up to 12 instances even though DT lists 15 nodes.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The new APIs are not only dealing with cache flushing. Rename the
Kconfig symbol to CACHE_MANAGEMENT to better reflect this change.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit add support for i2c on imx6sx.
I2C support is based on imx7d and requires NXP HAL.
The Device Tree binding is also changed to better reflect that i2c
driver support both imx6sx and imx7d.
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
Add support for fixed MMIO (non-PCIe) UART devices for the early
serial. All we need to do is to detect if the device is on PCIe and
set the right register address define based on that.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add definitions for UART1/2 when they're accessible through fixed MMIO
addresses (instead of PCIe), and mark all UARTs not normally available
with the UEFI BIOS as "disabled".
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Part of GPIO pads in npcx series support low-voltage (1.8V) level
detection. In order to introduce this feature, this CL adds a new
NPCX-specific controller property, lvol_io_pads, in devicetree file.
For example, here is devicetree fragment which turn on low-voltage
support of i2c1_0 port.
/ {
def_lvol_io_list {
compatible = "nuvoton,npcx-lvolctrl-def";
lvol_io_pads = <&lvol_io90 /* I2C1_SCL0 1.8V support */
&lvol_io87>; /* I2C1_SDA0 1,8V support */
};
};
Then these pads will turn on 1.8V level detection during initialization.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add some helper macros that will be convenient to use from device
drivers for accessing and error checking pin mux information in the
devicetree:
- NRF_DT_GPIOS_TO_PSEL(): converts a devicetree GPIO phandle
<&gpioX pin flags> to the "PSEL style" registers found in
nRF SoC family IPs. The conversion is done at
build time and relies on devicetree properties.
- NRF_DT_CHECK_GPIO_CTLR_IS_SOC(): make sure a GPIO controller
in a phandle-array property is one of the SoC GPIO controllers
by checking its compatible is nordic,nrf-gpio.
See comments in the patch for more details.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The QEMU RISC-V VirtIO board is capable:
- 8 x CPU
- 256 MiB RAM
- PMP
- PCI
- ISA string: RVnnIMAFDCSU
- mul/div
- FPU with double precision
- MMU
- Compressed instructions
Devicetree was extracted from QEMU as described in virt.dtsi.
The same .dtsi SOC description is used for 32-bit and 64-bit.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
In npcx7 series, the Timer and Watchdog module (TWD) generates the
clocks and interrupts used for timing periodic functions in the system.
It also provides watchdog reset signal generation in response to a
failure detection.
The CL also includes:
— Add npcx watchdog device tree declarations.
— Zephyr watchdog api implementation.
— Add Watchdog definitions for npcx7 series in
tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c for
supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This commit is about the it8xxx2 i2c master driver which
includes six SMBus channels. The enhanced channel i2c3,
i2c4, i2c5 are controller which are designed to support
the I2C protocol.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Sets the device tree chosen node for instruction tightly coupled memory
(ITCM) on all i.MX RT boards. Leverages the common Cortex-M linker
section instead of the SoC-specific one.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds missing DTCM_ADDR and CCM_ADDR macros needed by the linker script
generated by scripts/gen_relocate_app.py.
Moves associated bss_end, noinit_end, and data_end linker symbols to
account for section relocation. Without this change, the section sizes
calculated in z_bss_zero() and z_data_copy() are incorrect.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
STM32L152xC SoC differs from other L1 SoCs in RAM (32KiB) and
flash (256KiB) size, EEPROM size (8Kib) and amount of interrupts
(57, see STM32Cube). Devicetree and Kconfig support.
Signed-off-by: Noelle Clement <noelleclement@hotmail.com>
Currently Zephyr links reset-vector.S twice in xtensa builds:
into the bootloader and the main image. It is run at the end
of the boot loader execution and immediately after that again
in the beginning of the main code. This patch adds a
configuration option to select whether to link the file to the
bootloader or to the application. The default is to the
application, as needed e.g. for QEMU, SOF links it to the
bootloader like in native builds.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Disable RTC WDT enabled (by default) by 2nd stage bootloader in ESP-IDF.
This WDT timer ensures correct hand-over and startup sequence from
bootloader to application.
Enabling bootloader caused system clock initialization to fail
when clock rate is greater then 80MHz. This also fixes
esp32 clock source code.
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
Add check that validates that the base addresses specified in DT nodes
representing the ECB peripheral match the addresses of that peripheral
defined in MDK.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Looks like those two SoCs still had old header information depending on
Kconfig from SOF, remove those and set trace size directly.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
All other silabs_exx32 socs already have this change applied, only
efr32bg13p was missing. This is now done, so all silabs_exx32 are
similar.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
In order to simplify the handling of DMA_STM32_V1/V2 and DMAMUX_STM32
symbols, set them directly based on related compatible status.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
LPRAM_BASE and LPRAM_SIZE are duplicates of LP_SRAM_BASE and
LP_SRAM_SIZE respectively. Remove them and use LP_SRAM_*
consistently everywhere.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
On cAVS 1.8, 2.0 and 2.5 LSPGISTS and LSPGCTL are located in a
different shim register range, they cannot be accessed, using the
usual SHIM_BASE offset.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
CONFIG_BOOTLOADER_MCUBOOT is never used in cAVS builds, remove
code, supposedly supporting it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
shim.h on cAVS 2.5 contains register definitions, copy-pasted
from other architectures. Fix them to correct values.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Tigerlake H has less RAM and fewer cores. Both should be
supported, selectable at the board level. For now use the H
configuration as more readily available for testing.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
A configuration with CONFIG_MP_NUM_CPUS > 1 and CONFIG_IPM_CAVS_IDC not
defined is valid if COMFIG_SMP is disabled.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Shim register location on cAVS 1.5 is different than on 1.8 and up,
fix it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The current unused memory calculation is broken because it doesn't
take into account the stack area, allocated at the top of HP SRAM.
Until this is fixed disable powering down unused RAM.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
1. SOF doesn't have to be built in .bin format
2. don't include soc.c and soc_mp.c twice in cmake
3. remove an unused mailbox.h header
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
On cAVS 1.5, 2.0 and 2.5 platforms the correct manifest address is
0xB0032000.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
rimage dropped its "-m" parameter and switched over to using "-c"
for a configuration file, including a target name.
Add support for extended manifest for all cAVS versions.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Cnfigures the LPC55xxx SoC with dual-core (first core boots the second)
and enables the on-SoC mailbox to handle inter-core communication.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
The STM32F105xx is effectively an STM32F107xx without Ethernet. As such,
it's possible to include the STM32F105's device tree from STM32F107, and
add in any additional nodes (currently just DMA2, though according to
the datasheet, this may be supported by the STM32F105xx and other parts
too).
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Leftover from old renaming commits. This function is not private and
should not start with underscore.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
For a while now, we've had two APIC drivers. The older was preserved
initially as the new (much smaller, "new style") code didn't have
support for Quark interrupt handling. But that's long dead now. Just
remove it.
Note that this migrates the one board using this driver (acrn) to
CONFIG_APIC_TIMER instead.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Unify default configurations to support both SMP and UP:
1. make SMP default, although it's currently disabled in prj.conf
2. use CAVS timer by default in both UP and SMP configurations
3. make MP_NUM_CPUS, IPM and IPM_CAVS_IDC depend on SMP
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Some SoCs try to select power management in a way that can bypass the
dependency on system clock. Make the selection conditional on the
dependency.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The NPCX SMB modules provides full support for a two-wire SMBus/I2C
synchronous serial interface. Each SMBus/I2C interface is a two-wire
serial interface that is compatible with both Intel SMBus and Philips
I2C physical layer. There are 8 SMBus modules and 10 buses in NPCX7
series.
In NPCX7 series, the SMB5 and SMB6 modules contain a two-way switch to
support two separate SMBus/I2C buses (ports) with one SMB module
(controller) Please refer Section 4.7.2 in the datasheet. In order to
support it, this CL seperates the i2c driver into port and controller
drivers. The controller driver is in charge of i2c module operations
and internal state machine. The port driver is in charge of pin-mux
and connection between Zehpyr i2c api interface and controller driver.
All of modules have separate 32-byte transmit FIFO and 32-byte receive
FIFO buffers. These FIFO buffers reduce firmware overhead during long
SMBus transactions by allowing the Core to write or read more than one
data byte at a time to/from the SMB module.
The CL also includes:
— Add npcx i2c port/controller device tree declarations.
— Zephyr i2c api implementation.
— Add "i2c-0" aliases in npcx7m6fb.dts for i2c test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
The System Glue module includes the three major functions:
— Power Switch Logic (PSL)
— SMBus multi-bus, wake-up support
— Simple Debug Port (SDP)
In NPCX7 series, the SMB5 and SMB6 modules contain a two-way switch to
support two separate SMBus/I2C buses (ports) with one SMB module
(controller). Since a single SMB module is able to serve only one
SMBus/I2C bus at a time, SMB_SEL registerin Glue module is used to
control theconnection of I2Cn_0 and I2Cn_1 interface pins to the SMBn
module (where n is 5, 6).
This CL provides a soc specific pin-control function called
"soc_pinctrl_i2c_port_sel" to switch buses (port) of the same SMB module
(controller). It will be used in the following i2c driver.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
The existing implementation of the adsplog.py script worked fine for
individual runs (e.g. when running specific code) but had no support
for detecting system reset events and thus could not be used for
monitoring applications like test automation. It also could not
handle the case where a rapid log burst would overflow the buffer
before being noticed at the client. Also, the protocol here was also
rife with opportunities for race conditions. Fix all that up via what
is mostly a rewrite of the script. The protocol itself hasn't
changed, just the handling.
Also includes some changes to the trace_out.c code on the device side.
These are required to get ordering correct to make race conditions
tractably handleable on the reader side.
Some of the specific cases that are managed:
* There is a 0.4s backoff when a reset is detected. Continuing to
poll the buffer has been observed to hang the device (I'm fairly
sure this is actually a hardware bug, reads aren't visible to the
DSP software).
* The "no magic number" case needs to be reserved for detecting system
reset.
* Slot data must be read BETWEEN two reads of the ID value to detect
the case where the slot gets clobbered while being read.
* The "currently being filled" slot needs to always have an ID value
that does not appear in sequence from the prior slot.
* We need to check the full history in the buffer at each poll to
detect resets, which opens up a race between the read of the "next
slot" (which is absent) and the full history retrieval (when it can
now be present!). Detect that.
* A null termination bug in the current output slot got fixed.
Broadly: this was a huge bear to make work. It sounds like this
should be a simple protocol, but it's not in practice.
Also: clean up the error reporting in the script so it can handle new
PCI IDs being added, and reports permissions failures on the required
sysfs file as a human-readable error.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The toolchain variant per SoC is not always the soc name, so set this
per SoC and use this in the SDK instead of hardcoding the soc name.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This CL introduces two kinds of op codes for espi_api_lpc_read_request
and espi_api_lpc_write_request Zephyr espi api functions.
One is for supporting ACPI and shared memory region to access ACPI data.
The other is customized for certain platforms such as Chromebook and so
on.
This CL also introduced the following configurations to add the
flexibility of these settings.
1. ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM:
Host I/O peripheral port number for shared memory region. The default
value is default 0x0900
2. ESPI_NPCX_PERIPHERAL_ACPI_SHD_MEM_SIZE:
Host I/O peripheral port size for shared memory in npcx series.
Please notice the valid value in npcx ec series for this option is
8/16/32/64/128/256/512/1024/2048/4096 bytes. The default value is 256
bytes.
This CL also turn off hardware-wire feature which generates VW events
that connected to hardware signals such as SMI and SCI. We will set
VW output events directly via espi_api_send_vwire() api function.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Musca-S1 is a Cortex-M33 based SoC. It's similar to the
Musca-B1, but among other things the embedded flash has
been replaced with embedded MRAM (eMRAM) memory.
The Musca-S1 files have been created based on the Musca-B1
SoC and board files.
Add the Musca-S1 board to the list of allowed platforms
for the TF-M integration examples.
Change-Id: I4f517d28d0a5b8c4a3fc3fab73adb5519acfc3c2
Signed-off-by: David Vincze <david.vincze@linaro.org>
This commit adds the soc config for the STM32F303x8.
Add the STM32F303x8 as choice to the Kconfig.soc.
Fixing indention error in Kconfig.soc.
Signed-off-by: Sebastian Schwabe <sebastian.schwabe@mailbox.tu-dresden.de>
Set rom offset to 0x400 if application is compiled with
CONFIG_BOOTLOADER_MCUBOOT.
Please note that mcuboot is not yet supported on stm32h7 devices
Signed-off-by: Nicolas VINCENT <nicolas.vincent@vossloh.com>
In native_posix and nrf52_bsim add the cpu_hold() function,
which can be used to emulate the time it takes for code
to execute.
It is very similar to arch_busy_wait(), but while
arch_busy_wait() returns when the requested time has passed,
cpu_hold() ensures that the time passes in the callers
context independently of how much time may pass in some
other context.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Fix TIMER0 and RTC0 being selectable when using out-of-tree Bluetooth
controller.
Generalize the Kconfig to have the features that use the HW peripheral
select them as reserved to make the dependencies more manageable.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
The fix_elf_addrs script runs objcopy over a binary that (due to some
legacy section definitions in a mildly complicated linker file) has a
few zero-length sections at address zero. Objcopy considers this a
warning condition (though oddly the linker from the same version of
binutils which produced that binary does not!), which will be detected
as a CI failure.
Just eat the warnings. Long term we should rework linkage to remove
the legacy stuff that is getting tripped over.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
- Remove SYS_ prefix
- shorten POWER_MANAGEMENT to just PM
- DEVICE_POWER_MANAGEMENT -> PM_DEVICE
and use PM_ as the prefix for all PM related Kconfigs
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This CL replaces all DT_ prefix with NPCX_DT_ for all macros used
for providing npcx device information in soc_dt.h It avoided the
ambiguity with the DT_ prefix for system DT macros/defines.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
As best any of us could figure this was intended to indicate that the
macro is a function to be passed to UTIL_LISTIFY.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Set rom offset to 0x400 if application is compiled with
CONFIG_BOOTLOADER_MCUBOOT.
Please note that mcuboot is not yet supported on stm32h7 devices
Signed-off-by: Nicolas VINCENT <nicolas.vincent@vossloh.com>
NPCX7 includes a 10-bit resolution Analog-to-Digital Converter (ADC). Up
to 10 voltage inputs can be measured and a internal voltage reference
(VREF), 2.816V (typical) is used for measurement. It can be triggered
automatically in Autoscan mode. Each input channel is assigned a
separate result register, which is updated at the end of the conversion.
The CL also includes:
— Add npcx adc device tree declarations.
— Zephyr adc api implementation.
— Add adc definitions of npcx7 in
tests/drivers/adc/adc_api/src/test_adc.c for supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
STM32H753xx is similar to STM32H743xx except that it has crypto/hash
hardware acceleration and the memory configuration is always 2Mbytes
flash and 1Mbyte RAM.
Signed-off-by: Petri Oksanen <petri@iote.ai>
Include generic header stm32_ll_hsem.h from stm_hsem.h (which is used
by multiple drivers) instead of depending on soc.h.
Signed-off-by: Martin Jäger <martin@libre.solar>
SOF uses different SSP clock rates on different cAVS versions. Frequency
tables are provided in platform_ssp_freq[] arrays in clk.c for each
version and the default entry is selected by the SSP_DEFAULT_IDX index.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The current SAM4S define at board level common flags that should be on
soc defines. Add common flags at SoC Kconfig defines and drop the
correspondent at board defines.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current SAM4E define at board level common flags that should be on
soc defines. Add common flags at SoC Kconfig defines and drop the
correspondent at board defines.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add separated Kconfig file for Bluetooth 5.1 Direction Finding.
Enable controller support for:
- transmission of CTE
- 2us antenna switching
- 1us antenna switching
if build for nRF52833 SOC.
Add HAS_HW_NRF_RADIO_BLE_DF to nrf52833 SOC configuration.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
This commit adds a new driver category for memory controller
peripherals. There is no API involved for now, as it has not been found
necessary for first implementation.
STM32 Flexible Memory Controller (FMC) is the only controller supported
for now. This peripheral allows to access multiple types of external
memories, e.g. SDRAM, NAND, NOR Flash...
The initial implementation adds support for the SDRAM controller only.
The HAL API is used, so the implementation should be portable to other
STM32 series. It has only been tested on H7 series, so for now it can
only be enabled when working on H7.
Linker facilities have also been added in order to allow applications to
easily define a variable in SDRAM.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Configures i.MX RT SoCs that support cacheable external SDRAM to use the
DTCM linker section for Segger RTT and SystemView data.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The SAM4L have a unique I2C driver. It shares simultaneously pins for
both master and slave controllers. Each controller have their own
instance. This introduces the TWIM controller that handles only the
master part.
The TWIM controller uses no copy and the driver was prepared to work
with both 7 and 10 bits address. The controller can handler up to 256
bytes for a single transfer allowing long data communication with
almost no CPU intervention.
The driver was wrote specifically to Zephyr. It receives a transfer
list of from upper layers to a specific device on the bus. It programs
the first and second transfer, if it exists, before start. At end of
full read/write interrupt, will program the next data block. This
process repeats until all transfers be executed. The driver uses
interrupt from TWIM to check for erros or program next tranfer.
Future work can enable low power mode on the driver allowing long
transfers with low power consumption.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add i2c1 interface for stm32l552xx and stm32l562xx microcontrollers
and enable i2c1 that connects to lsm6dso sensor module on the
stm32l562e_dk board.
Signed-off-by: Yestin Sun <sunyi0804@gmail.com>
This commit implements the architecture specific parts for the
Zephyr tracing subsystem on SPARC and LEON3. It does so by calling
sys_trace_isr_enter(), sys_trace_isr_exit() and sys_trace_idle().
The logic for the ISR tracing is:
1. switch to interrupt stack
2. *call sys_trace_isr_enter()* if CONFIG_TRACING_ISR
3. call the interrupt handler
4. *call sys_trace_isr_exit()* if CONFIG_TRACING_ISR
5. switch back to thread stack
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This section was being put in the wrong region, and was in L1-cached
incoherent memory. That's wrong, as users are expected to expressly
ask for "__incoherent" memory and do manual cache management if
required. Default memory of all types should be uncached and
coherent.
Very few spots use this and cache effects tend to be ephemeral, so it
was somewhat obscure. It was discovered via an SMP race when using
logging very close to system start where the log thread on the second
CPU will race with messages added on the first -- log messages are
stored in a __noinit mem_slab.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This platform had separate backends for the log subsystem and printk
handler, which was silly. Unify them to use the same backend so they
don't clobber each other.
This patch appears to be a lot of lines, but it's really mostly code
motion and renaming.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Change adds missing TX power dependencies. nRF52833 and nRF52820 SoCs
also support higher TX power values.
Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
1. Code for the power mananagement is available
in source format
2. Increase the core speed to 250MHz.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
These MCUs have 32Kbytes of Flash and 8Kbytes of RAM. They are still
able to run a number of samples.
Signed-off-by: Steven Daglish <s.c.daglish@gmail.com>
In CMakeLists.txt, the MEC1501 specific timing functions are
only compiled if CONFIG_CORTEX_M_DWT=n. However, in SoC's
kconfig, CONFIG_SOC_HAS_TIMING_FUNCTIONS is defaulted to y
unconditionally. This results in the timing subsys looking
for SoC-based timing functions but those are not compiled.
So add a condition to kconfig similar to CMakeLists.txt where
SoC timing functions are only enabled when CONFIG_CORTEX_M_DWT=n.
Fixes#29969
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add a Kconfig option (enabled by default) the enables the low-frequency
oscillator (LFXO) functionality on the XL1 and XL2 pins in the nRF53
SoC initialization routine. This cannot be done in the clock control
driver, as it was done so far, because that won't work in a setup where
the application core image does not use the system clock at all.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Replace direct register accesses in the SoC initialization routine
with proper calls to nrfx HAL functions.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
We should not be initializing/starting/stoping timing functions
multiple times. So this changes how the timing functions are
structured to allow only one initialization, only start when
stopped, and only stop when started.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The nRF5340 (P)DK is equipped with the MX25R64 flash memory. Add a dts
node for that chip in the board definition as well as the missing QSPI
node in the nRF5340 SoC definition.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The IRQ handler has had a major changes to manage syscall, reschedule
and interrupt from user thread and stack guard.
Add userspace support:
- Use a global variable to know if the current execution is user or
machine. The location of this variable is read only for all user
thread and read/write for kernel thread.
- Memory shared is supported.
- Use dynamic allocation to optimize PMP slot usage. If the area size
is a power of 2, only one PMP slot is used, else 2 are used.
Add stack guard support:
- Use MPRV bit to force PMP rules to machine mode execution.
- IRQ stack have a locked stack guard to avoid re-write PMP
configuration registers for each interruption and then win some
cycle.
- The IRQ stack is used as "temporary" stack at the beginning of IRQ
handler to save current ESF. That avoid to trigger write fault on
thread stack during store ESF which that call IRQ handler to
infinity.
- A stack guard is also setup for privileged stack of a user thread.
Thread:
- A PMP setup is specific to each thread. PMP setup are saved in each
thread structure to improve reschedule performance.
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Nicolas Royer <nroyer@baylibre.com>
This change adds IEEE 802.15.4g (Sub GHz) support for the
cc1352r.
The 2.4 GHz radio and the Sub GHz radio are capable of
operating simultaneously.
Fixes#26315
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
The current MMU code is assuming that both kernel and threads are both
running in EL1, not supporting EL0. Extend the support to EL0 by adding
the missing attribute to mirror the access / execute permissions to EL0.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This change reworks the cc13xx_cc26xx IEEE 802.15.4 driver to use
the TI RF driver API that is available in modules/hal/ti.
There are a number of benefits to using TI's API including
- a stable multi-OS vendor library and API
- API compatibility with the rest of the SimpleLink SDK and SoC family
- potential multi-protocol & multi-client radio operation
(e.g. both 15.4 and BLE)
- coexistence support with other chipsets via gpio
- vetted TI RF driver resources, such as
- the radio command queue
- highly tuned / coupled RTC & RAT (RAdio Timer) API
Fixes#26312
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
This qemu device is REALLY slow in icount mode. When I run it outside
of icount and watch the simulator advance the clock device in real
time, it looks to me like it expects the counter to be running at ~125
MHz. But it's set to a 12 MHz clock rate in its config, and trying to
use a 1000 Hz tick rate.
At those settings (and with the shift=3 argument to icount), I'm
measuring about 10k cycles to handle a minimal timer interrupt. But
if you do the math, that comes to 12k cycles per tick. The interrupt
takes as long as a tick! That would never work, except for the fact
that the timer driver on this device cheats and doesn't try to align
to ticks (basically ignoring all the lost time). And even that breaks
on the scheduler_api test (which does both tick and cycle math and
tries to compare them) when it's fixed to properly align itself.
One solution might be to set the clock rate to what qemu appears to
believe is the correct 125 MHz value. And that causes the test to
complete, but all tests now take ~10 minutes of real time because the
simulator is so slow!
So just make up some clock rates, it's a simulated platform after all.
I chose 5 MHz cycle time and 100 Hz tick rate, which on my device is
about half of "real" speed and very acceptable.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
As discuss in PR #28805, sloppy idle function still has some bug and
barely used, so we can remove it safely.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
Enables the mcux flexcan driver on i.mx rt socs by default when
CONFIG_CAN=y.
This fixes a runtime failure in tests/subsys/canbus/isotp/conformance on
the mimxrt1064_evk board:
Assertion failed at WEST_TOPDIR/zephyr/tests/subsys/canbus/isotp/conformance/src/main.c:883: test_main: (can_dev is NULL)
CAN device not not found
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
With STM32Cube updates
https://github.com/zephyrproject-rtos/hal_stm32/pull/75
'..._hal_rcc.c' and '..._hal_rcc_ex.c' are now systematically
compiled, due to more and more dependencies from HAL IP on rcc.
So USE_STM32_HAL_RCC and USE_STM32_HAL_RCC_EX becomes useless.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Adds the necessary bits to initialize TLS in the stack
area and sets up CPU registers during context switch.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This IPC protocol is designed to tell the host driver that the audio
firmware is ready. It's not used within the Zephyr in-tree test code,
which does not run under the control of a host driver. And SOF
already does this on its own, the Zephyr attempt to do it first (and
incorrectly) confuses the driver IPC.
Just remove it. This is clearly application code, not platform code.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Sets the device tree chosen node for data tightly coupled memory (DTCM)
on i.mx rt boards that aren't already using DTCM as the chosen SRAM.
Leverages the common cortex-m linker section instead of the soc-specific
one.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Removes the DATA_LOCATION Kconfig symbol from the i.mx rt soc series and
refactors corresponding boards to use a device tree chosen node instead.
The external SDRAM is chosen on all boards that can support it;
otherwise the internal DTCM is chosen.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Refactors the i.mx rt soc series to enable device configuration data
(DCD) by default when the smart external memory controller (SEMC) is
present. This is in preparation for removing the DATA_LOCATION Kconfig
symbol and using a device tree chosen node instead.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add support for interrupt driven MSI-X PVM feature for Viper.
Function mask bit update is tracked with snoop interrupt
and vector mask bit update is tracked with pcie pmon lite
address range access detection interrupt.
Both the interrupts are required to enable this feature.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Deprecate the Musca-A board and SoC support to be removed in 2.6.0.
There are a number of issues with the Musca-A and there exists both the
Musca-B and Musca-S1.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The linker will emit a warning condition when a section with a
declared alignment doesn't naturally start on that alignment (which
begets the question of why the declared alignment syntax exists at
all...).
Do the alignment for .bss between the sections instead as a simple
workaround.
Note that this alignment isn't architecturally required, as current
Zephyr targets don't use the page-aligned pseudo-MMU on this hardware;
the only requirement is alignment to the 64 byte cache stride. It
should work to pack .bss tightly. But when I try that, I get an error
from the rimage tool, which is apparently unprepared for
non-4k-aligned sections?
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The header scheme for the IPM_CAVS_IDC driver changed and this legacy
platform (which is really a very close cousin of intel_adsp/cavs_v15)
broke. Fix things up. Longer term we should unify the two.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add a printk default hook that works in very early boot and doesn't
depend on the logging subsystem (which can still be used if desired,
of course). It speaks the same protocol, is somewhat smaller (MUCH
smaller if the app doesn't otherwise need the logging and ring buffer
dependencies), and more efficiently uses the output slot space by
doing line buffering and flushing only when needed.
Most importantly this one is MP-safe via both locking and cache
coherence management, and can work reliably when SMP is enabled.
(Note that "reliable" means that all output appears without corruption
-- simulateous logging by two CPUs can still interleave bytes, of
course).
Longer term, if we keep this protocol it would be good to unify the
two backends to reduce duplicated code.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Implement the kernel "coherence" API on top of the linker
cached/uncached mapping work.
Add Xtensa handling for the stack coherence API.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Xtensa CPUs have incoherent L1 caches, which is deeply inconvenient
for SMP systems. But as a treatment for this, the ADSP memory map
contains the RAM twice, in separate 512MB regions that can be managed
separately by the Xtensa TLB/cacheattr mechanism. The low mapping is
set to bypass the cache where the high mapping is cached.
Set up linkage to use both as appropriate, then reassemble the final
sections to a contiguous region. Read-only areas (.text, .rodata) are
cached. Data sections are uncached by default, except for a special
".cache" section that may be used by higher level code to flag static
areas (e.g. stacks) which don't store multiprocessor-shared content.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Significant rework of the Intel Audio DSP SoC/board layers. Includes
code from the following upstream commits:
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Thu Jun 25 16:34:36 2020 +0100
xtesna: adsp: use 50k ticks per sec for audio
Audio needs high resolution scheduling so schedule to nearest 20uS.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 24 13:59:01 2020 -0700
soc/xtensa/intel_adsp: Remove sof-config.h includes
This header isn't used any more, and in any case shouldn't be included
by SoC-layer Zephyr headers that need to be able to build without SOF.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Sat Jun 20 15:42:58 2020 -0700
soc/intel_adsp: Leave interrupts disabled at MP startup
This had some code that was pasted in from esp32 that was inexplicably
enabling interrupts when starting an auxiliary CPU. The original
intent was that the resulting key would be passed down to the OS, but
that's a legacy SMP mechanism and unused. What it actually did was
SET the resulting value in PS.INTLEVEL, enabling interrupts globally
before the CPU is ready to handle them.
Just remove. The system doesn't need to enable interrupts until the
entrance to the first user thread on this CPU, which will do it
automatically as part of the context switch.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 23 13:57:54 2020 +0300
dts: intel_cavs: Add required label
Add required label fixing build for CAVS15, 20, 25.
Fixes following errors:
...
devicetree error: 'label' is marked as required in 'properties:' in
bindings/interrupt-controller/intel,cavs-intc.yaml,
but does not appear in
...
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 23 15:19:56 2020 +0300
soc: cavs_v18: Remove dts_fixup and fix build
Remove unused now dts_fixup.h and fix build with the recent code base.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 23 15:12:25 2020 +0300
soc: cavs_v20: Remove dts_fixup and fix build
Remove unused now dts_fixup.h and fix build with the recent code base.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 23 14:59:23 2020 +0300
soc: cavs_v25: Remove dts_fixup fix build
Remove unused now dts_fixup and fix build with the latest code base.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri Jun 12 12:29:06 2020 +0300
soc: intel_adsp: Remove unused functions
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 17:53:58 2020 +0300
soc: intel_adsp: Clean up soc.h
Remove unused or duplicated definitions.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 17:02:23 2020 +0300
soc: intel_adsp: De-duplicate soc.h
Move soc.h to common SOC area.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 15:54:19 2020 +0300
soc: intel_adsp: Remove duplicated io.h
Move duplicated io.h to common SOC area.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri Jun 12 12:39:46 2020 +0300
cmake: Correct SOC_SERIES name for byt and bdw
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri Jun 12 12:39:02 2020 +0300
soc: intel_adsp: Build bootloader only for specific SOCs
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Thu Jun 11 13:46:25 2020 +0100
boards: xtensa: adsp: add byt and bdw boards WIP
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 10 10:01:29 2020 -0700
soc/intel_adsp: Make the HDA timer the default always
The CAVS_TIMER was originally written because the CCOUNT values are
skewed between SMP CPUs, so it's the default when SMP=y. But really
it should be the default always, the 19.2 MHz timer is plenty fast
enough to be the Zephyr cycle timer, and it's rate is synchronized
across the whole system (including the host CPU), making it a better
choice for timing-sensitive applications.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 15:21:43 2020 +0300
soc: cavs_v25: Enable general samples build
Enables general samples build for SOC cavs_v25.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 15:13:53 2020 +0300
soc: cavs_v20: Enable general samples build
Enable general sample build.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 14:35:13 2020 +0300
soc: cavs_v18: Fix build general samples
Fix building general samples for CAVS18.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 14:22:40 2020 +0300
soc: intel_adsp: Add support for other SOCs
Support other SOCs in the "ready" message to the Host.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 13:25:39 2020 +0300
soc: intel_adsp: Move adsp.c to common SOC area
Move adsp.c to common and clean makefiles.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 17:18:18 2020 +0300
boards: intel_adsp: Remove dependency on SOF
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue Jun 9 14:29:44 2020 +0100
soc: xtensa: cavs: build now good for cavs20 + 25
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 15:57:01 2020 +0300
soc: cavs_v15: Fix build for hello_world
Fix build for other then audio/sof targets.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 14:50:12 2020 +0300
sample: audio/sof: Remove old overlays
Removing old overlays used to switch logging backend.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon Jun 8 15:02:01 2020 +0300
soc: intel_adsp: Correct TEXT area
Correct HEADER_SPACE and put TEXT to:
(HP_SRAM_WIN0_BASE + HP_SRAM_WIN0_SIZE + VECTOR_TBL_SIZE)
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 14:44:47 2020 +0300
soc: intel_adsp: Trivial syntax cleanup
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 14:41:07 2020 +0300
soc: intel_adsp: Fix bootloader script path
Make it possible to find linker script if build is done not inside
ZEPHYR_BASE.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue Jun 9 12:10:17 2020 +0100
soc: xtensa: cavs20/25: fix build with new headers - WIP
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 13:35:38 2020 +0300
soc: intel_adsp: Fix include headers
Fixes include headers
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue Jun 9 10:38:50 2020 +0100
soc: xtensa: cav18: updated headers- WIP
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Fri May 1 15:29:26 2020 -0700
soc/xtensa/intel_adsp: Clean up MP config logic
CONFIG_MP_NUM_CPUS is a platform value, indicating the number of CPUs
for which the Zephyr image is built. This is the value kernel and
device code should use to predicate questions like "is there more than
one CPU?"
CONFIG_SMP is an application tunable, controlling whether or not the
kernel schedules threads on CPUs other than the first one. This is
orthogonal to MP_NUM_CPUS: it's possible to build a "SMP" kernel on a
uniprocessor system or have a UP kernel on a MP system if the other
cores are used for non-thread application code.
CONFIG_SCHED_IPI_SUPPORTED is a platform flag telling an SMP kernel
whether or not it can synchronously signal other CPUs of scheduler
state changes. It should be inspected only inside the scheduler (or
other code that uses the API). This should be selected in kconfig by
soc layer code, or by a driver that implements the feature.
CONFIG_IPM_CAVS_IDC is a driver required to implement IPI on this
platform. This is what we should use as a predicate if we have
dependence on the IPM driver for a platform feature.
These were all being sort of borged together in code. Split them up
correctly, allowing the platform MP layer to be unit tested in the
absence of SMP (c.f. tests/kernel/mp), and SMP kernels with only one
CPU (which is pathlogical in practice, but also a very good unit test)
to be built.
Also removes some dead linker code for SMP-related sections that don't
exist in Zephyr.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Jun 8 16:41:55 2020 +0100
soc: xtensa: bootloader - use linker script
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Jun 8 16:26:18 2020 +0100
soc: xtensa: further fix headers - WIP
Simplify the directory structure, WIP for cavs20 and cavs25
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon Jun 8 12:59:30 2020 +0300
soc: cavs_v15: Remove unneeded include
Remove include fixing build.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun Jun 7 12:37:35 2020 +0100
soc:xtensa: adsp: remove sof specific code from soc headers
TODO: v1.8+
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Marc Herbert <marc.herbert@intel.com>
Date: Thu Jun 4 23:19:37 2020 -0700
intel_adsp_*/doc: fix duplicate .rst labels
Quick fix purely to make the build green again.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Author: Marc Herbert <marc.herbert@intel.com>
Date: Thu Jun 4 22:34:40 2020 -0700
samples/audio/sof: use OVERLAY_CONFIG to import apollolake_defconfig
This reverts commit 21f16b5b1d29fca83d1b62b1b75683b5a1bc2935 that
copied it here instead.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri Jun 5 12:34:48 2020 +0300
soc: intel_adsp: Move soc_mp to common
Moving soc_mp to common SOC area, it still needs fixes for taking
number of cores from Zephyr Kconfig, etc.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Jun 4 16:05:06 2020 +0300
soc: intel_adsp: Move memory.h from lib/
For those files from SOF referencing platform/lib/memory.h we have
include.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Jun 4 15:20:09 2020 +0300
soc: intel_adsp: Rename platform.h to soc.h
Rename to prevent including it from SOF.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Jun 4 11:47:55 2020 +0300
soc: intel_adsp: Move headers
Move headers to more convenient place
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Jun 4 11:21:51 2020 +0300
soc: intel_adsp: More SOC cleaning
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Marc Herbert <marc.herbert@intel.com>
Date: Mon Jun 1 15:31:34 2020 -0700
samples/audio/sof: import sof/src/arch/xtensa/ apollolake_defconfig
Import modules/audio/sof/src/arch/xtensa/configs/apollolake_defconfig
into prj.conf and new boards/up_squared_adsp.conf
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Jun 3 15:07:40 2020 +0100
soc:xtensa: adsp: let SOF configure the DSP for audio
Let SOF do this for the moment.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Jun 3 15:06:20 2020 +0100
soc: xtensa: cavs: remove headers similar to cavs15
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 3 15:58:38 2020 +0300
soc: intel_adsp: Move ipc header to common
Remove duplicated headers from CAVS to common SOC part
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 3 13:02:09 2020 +0300
soc: cavs_v15: Remove unneeded headers
Remove also from CAVS15.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 18:34:11 2020 +0300
Remove more headers
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Jun 3 14:12:09 2020 +0100
soc: xtensa: remove cavs sod headers for drivers and trace.
Duplicate cavs15 headers.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Jun 3 14:05:12 2020 +0100
samples: move sof dai, dma and clk configs to SOF
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 17:38:45 2020 +0300
soc: intel_adsp: Remove more duplicated headers
Remove more headers
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue Jun 2 15:50:03 2020 +0100
samples: sof: remove pm realted files.
Use the SOF versions.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 16:55:40 2020 +0300
WIP: Strip lib from include path
WIP, pushed for sync
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 14:44:33 2020 +0300
soc: intel_adsp: Remove more headers
Remove even more common headers
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 14:00:47 2020 +0300
soc: intel_adsp: Remove SOF headers
The headers would be used by audio/sof app directly from SOF module.
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Sat May 30 11:01:26 2020 -0700
soc/intel_adsp: Alternative log reading script
This script speaks the same protocol and works with the same firmware,
but:
* Is a single file with no dependencies outside the python3 standard
library and can be run out-of-tree (i.e. with setups where the
firmware is not built on the device under test)
* Operates in "tail" mode, where it will continue polling for more
output, making it easier to watch a running process and acting more
like a conventional console device.
* Has no dependence on the diag_driver kernel module (it reads the DSP
SRAM memory directly from the BAR mapping in the PCI device)
* Is MUCH smaller than the existing tool.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu May 28 16:17:51 2020 +0300
Decrease HEP pool size to 192000
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:27:00 2020 +0100
soc: xtensa: cavs25: complete support for cavs25
Builds, not tested on qmeu due to missing SOF ROM (TODO)
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:24:26 2020 +0100
soc: xtensa: cavs20: complete cavs20 support
Now boots on qemu.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:22:13 2020 +0100
soc: xtensa: cavs18: complete boot support
Now boots on qemu.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:19:23 2020 +0100
soc: xtensa: cavs15: use cavs15 instead of apl as linker soc name
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:16:06 2020 +0100
TODO: samples: sof: work around missing trace symbols.
Disable local trace.
Needs trace updates finished before this can be removed.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed May 27 15:57:19 2020 +0100
dts: xtensa: rename apl to cavs15 DTS
This DTS is used by more than APL SOC. i.e. all CAVS15 SOCs
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed May 27 15:52:20 2020 +0100
west: commands: sign: Add signing support for other CAVS targets
Sign for CAVS15, CAVS18, CAVS20 and CAVS25 SOCs
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed May 27 15:50:07 2020 +0100
boards: xtensa: cavs: used Zephyr mask macro
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed May 27 15:49:46 2020 +0100
soc: xtensa: move code to SOF
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue May 26 11:40:36 2020 +0100
soc: xtensa: use SOF versions of clk
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 18:38:45 2020 +0300
soc: intel_adsp: Send FW ready for non SOF configuration
Configure windows and send FW ready when used without SOF, should be
loaded with fw_loader script.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 18:02:22 2020 +0300
soc: intel_adsp: Use SOF version of the file
Use exact copy from SOF module.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 17:47:27 2020 +0300
soc: intel_adsp: Clean up include headers
Remove SOF mentions from the SOC headers.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 17:43:05 2020 +0300
soc: intel_adsp: Move SOF specific code to samples/audio/sof
Move SOF specific code to the SOF sample.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 17:39:42 2020 +0300
soc: intel_adsp: Use SOF module's version of mem_window.c
Use exact copy from SOF module.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 17:36:41 2020 +0300
soc: intel_adsp: Use exact copy from SOF module
Use SOF module verion of the clk.c
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 14:03:35 2020 +0300
soc: xtensa: Add {SOC_FAMILY}/common/include path
Add ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/include path if exist.
Fixes issues for xtensa SOCs.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 25 16:18:50 2020 +0100
soc: xtensa: cavs common: fix headers for build
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 25 16:10:57 2020 +0100
soc: xtensa: adsp: add so_inthandlers.h for Intel platforms
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 25 16:08:26 2020 +0100
cmake: xtensa: select correct compiler per CAVS target.
TODO: what about XCC ?
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue May 19 14:59:26 2020 +0300
boards: up_squared_adsp: Move SOF configuration to samples
Move SOF-specific configuration to samples/audio/sof prj.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri May 15 15:29:50 2020 +0300
soc: intel_adsp: Move SOF code to modules/audio/sof
Move SOF dependent code out of SOC area.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu May 14 17:30:38 2020 +0300
Move task_main_start() to audio/sof sample
Start task_main_start() from main of audio/sof sample.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed May 13 15:37:20 2020 +0300
Rename up_xtreme_adsp to intel_adsp_cavs18
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon Apr 27 14:12:59 2020 +0300
Add sample audio/sof for SOF initialization
Add dedicated sample where we put SOF specific initialization.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 11 18:49:36 2020 +0300
WIP: soc: cavs_v18: Cleanup
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 11 15:44:06 2020 +0300
soc: cavs_v15: Move soc init to common part
Moving SOC init to the right place.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 11 15:02:28 2020 +0300
soc: intel_adsp: Move common part to special dir
Moving common part to common/adsp.c
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri May 8 14:37:50 2020 +0300
boards: up_xtreme_adsp: Add initial up_xtreme_adsp board
Add initial board copying existing up_squared_adsp board and using
CAVS1.8 SOC family.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu May 7 15:30:51 2020 +0300
soc: intel_adsp: Generalize bootloader
Move bootloader to soc/xtensa/intel_adsp making it available for other
boards.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue May 5 21:31:00 2020 +0100
boards: xtensa: up_squared: Add support for all CAVS
Add boot support for all CAVS versions. TODO: needs to be made common
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue May 5 21:25:34 2020 +0100
soc: xtensa: intel_adsp: Manage cache for DMA descriptors
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 4 21:10:50 2020 +0100
soc: xtensa: adsp: use 24M567 clock
Use audio clock
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 4 10:04:01 2020 +0100
xtensa: soc: adsp: enable system agent
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun May 3 15:03:07 2020 +0100
soc: xtensa: intel_adsp: increase mem pool to 192k
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun May 3 15:02:31 2020 +0100
soc: xtensa: intel_adsp: re-enable DMA trace
Buffer will be empty (as trace items sent to Zephyr LOG) but
logic is running.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun May 3 11:18:55 2020 +0100
soc: xtensa: intel: dont use uncache region yet.
Some code was still using this region. Use later.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun May 3 10:07:28 2020 +0100
soc: xtensa: intel_adsp: fix notifier init
Topology now loads.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 1 21:18:38 2020 +0100
boards: up2: Need to use sof config for bootloader
This will need uncoupled at some point. For testing today.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 1 21:16:38 2020 +0100
boards: up2: increase heap to 128k
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Apr 30 11:35:19 2020 +0300
boards: up_squared_adsp: Use bigger HEAP
Use HEAP from old demo.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 1 16:06:32 2020 +0100
soc: xtensa: intel_adsp: Fix config.h naming collisions
Rename sof version to sof-config.h
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Apr 30 11:22:42 2020 +0300
Small cleanups
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 29 22:00:44 2020 +0300
tests: sof/audio: Test ll scheduler
Add more tests for scheduler.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 29 18:38:35 2020 +0300
tests: Add first schedule test
Add initial test for testing scheduling.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 29 13:36:23 2020 +0100
soc: xtensa: rmeove build warnings
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 28 18:04:33 2020 +0300
soc/intel_adsp: Register sof logging
Register sof logging for tracing
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 28 14:16:55 2020 +0300
boards: up_squared_adsp: Define HEAP_MEM_POOL_SIZE
Define HEAP_MEM_POOL_SIZE when SOF enabled.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 28 10:09:20 2020 +0300
tests: audio/sof: Add interrupt API for testing
Add initial interrupt API for testing.
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 27 15:54:28 2020 +0100
soc: xtensa: adsp: Update linker script for SOF sections.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 27 11:20:01 2020 +0100
soc: xtensa: adsp: send SOF FW metadata as boot message
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun Apr 26 21:47:20 2020 +0100
soc: xtensa: adsp: re-enable all SOF IP init.
Do all SOF IP init.
TODO: ATOMCTL, WFI on LX6
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sat Apr 25 15:30:40 2020 +0100
soc: xtensa: irq: Make sure IPC IRQ is registered.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 22 20:56:09 2020 +0300
tests: sof: Enable console
Enable console for the test.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 22 17:57:22 2020 +0300
soc: cavs_v15: Fix XTENSA_KERNEL_CPU_PTR_SR
Use correct value for XTENSA_KERNEL_CPU_PTR_SR.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 22 14:48:31 2020 +0300
tests: audio/sof: Add tests for alloc API testing
Add initial tests for allocation API testing. Can be extended for
other later.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 21 17:49:32 2020 +0300
logging: Enable xtensa simulator backend for ADSP
Enable xtensa simulator backend for SOC_FAMILY_INTEL_ADSP.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 20:58:30 2020 +0100
soc: xtensa: add common cpu logic
Support for additional cores.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 21 10:11:07 2020 +0300
Update west.yaml to point to the latest repo
Update west.yaml
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:17:01 2020 +0100
soc: xtensa: cavs: Fix build for clk.c on cavs18+
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:05:31 2020 +0100
soc: xtensa: cavs15: removed unused headers.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:05:09 2020 +0100
soc: xtensa: cavs25: align with SOF headers
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:03:52 2020 +0100
soc: xtensa: cavs20: align with SOF headers
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:03:09 2020 +0100
soc: xtensa: cavs18: Align with SOF headers.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 11:42:39 2020 +0100
west: sof: Updated to latest version.
Now builds, links and runs SOF code (but not to FW ready).
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun Apr 19 13:28:53 2020 +0100
xtensa: intel adsp: build in SOF symbols if CONFIG_SOF
Code now fully links against SOF. Needs to be run tested.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Wed Apr 15 10:19:28 2020 -0700
DO NOT MERGE: temporarily add thesoftproject as remote for sof module
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Wed Apr 15 10:33:40 2020 -0700
ipm: cavs_idc: use the IPC/IDC definitions in SoC
The SoC definitions have the necessary IPC/IDC bits so there is
no need to define them separately.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 15 14:30:20 2020 +0100
TODO: config: Use static config for SOF module.
TODO: needs to be generated as part of SOF kconfig
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri Apr 10 21:56:07 2020 +0100
HACK: Add SOF into build
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 15 13:55:15 2020 +0100
west: modules: Add SOF audio module.
Add support for building SOF as a Zephyr module. This is the starting
point for add SOF audio into Zephyr. Currently builds but does not use
any symbols yet.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 15 13:48:48 2020 +0100
WIP soc: adsp-cavs15: Use same include directory structure as SOF
Use the same directory structure as SOF to simplify porting and allow
SOF to build without Zephyr until porting work is complete.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 15 13:43:44 2020 +0100
WIP soc: adsp-common: Use same include directory structure as SOF
Use the same directory structure as SOF to simplify porting and allow
SOF to build without Zephyr until porting work is complete.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 14:36:32 2020 +0000
WIP: soc: adsp-common: cache is common across all Intel ADSP platforms
De-duplicate soc.h cache definitions.
TODO: this needs done for other common functions.
TODO: need to fix include path
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 30 11:07:43 2020 -0700
WIP: soc: cavs25: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 30 11:07:12 2020 -0700
WIP: soc: cavs20: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 30 11:06:40 2020 -0700
WIP: soc: cavs18: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Mon Mar 30 12:37:17 2020 -0700
soc: intel_adsp: use main_entry.S in common for cavs_v15
The files are identical anyway.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Mon Mar 30 11:38:14 2020 -0700
soc: intel_adsp/cavs_v15: link common code
Let cavs_v15 link against the code compiled under common/.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 13:08:28 2020 +0000
WIP: soc: common: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 14:37:32 2020 +0000
WIP soc: adsp-cavs15: build power down support
Build the power down support for CAVS1.5
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 12:40:17 2020 +0000
WIP: soc: cavs15: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 14:30:08 2020 +0000
soc: cavs15: Add missing SHIM registers.
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 9 15:43:01 2020 +0000
xtensa: intel_adsp/cavs_v15: fix usage of LP SRAM power gating
Remove LSPGCTL as it can cause confusion, use SHIM_LSPGCTL instead.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Feb 26 15:28:48 2020 +0000
boards: up_squared_adsp: Use local xtensa HAL instead of SDK HAL
SDK HAL is deprecated for Intel ADSP SoCs so fix and use local HAL
module.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Mon Mar 30 10:45:15 2020 -0700
soc: add Intel Audio DSP SoC family
This creates a SoC family for the audio DSPs on various
Intel CPUs. The intel_apl_adsp is being moved into
this family as well, since it is part of the CAVS v1.5
series of DSPs.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Mon Mar 30 11:29:02 2020 -0700
soc: xtensa: add CMakeLists.txt
Add CMakeLists.txt under soc/xtensa so that CMakeLists.txt
inside each SoC directory will be included, similar to
what ARM and RISCV have.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 17 12:30:43 2020 -0700
Revert "boards: up_squared_adsp: Add flasher script"
This reverts commit 80f295a9dd.
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 17 12:30:32 2020 -0700
Revert "boards: up_squared_adsp: Update logtool tool"
This reverts commit 7770d182c1.
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 17 12:30:23 2020 -0700
Revert "soc: intel_adsp: Generalize bootloader"
This reverts commit d6a33ef467.
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
soc: xtensa; intel: remove sof-config.h - SQUASH
No longer used.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This defines the TRNG for EFM32GG11 and enables it for trng0
in the dts for the matching development kits.
Signed-off-by: Thorvald Natvig <thorvald@natvig.com>
When converting ELF to a flashable image, the esptool can only
process up to 16 ELF sections. Zephyr has been happily grouping
similar objects into linker sections which can easily go over
esptool's limit. This patch consolidates the kernel, net, log,
and shell objects into their own sections.
Also remove the app_noinit section as no one is emitting
anything into that section, and it's not being used by other
arch/SoC/boards in Zephyr.
Fixes#20980
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The WGM160P module combines the WF200 Wi-Fi transceiver with
an EFM32GG11 MCU
This code is based on the efm32gg_stk3701a board definitions
Signed-off-by: Thorvald Natvig <thorvald@natvig.com>
In order to be in line with other DT_INST macros in zephyr code base,
swap the arguments order in following macro definitions:
*ST_STM32_DT_PINCTRL
*ST_STM32_DT_INST_PINCTRL
Update the users accordingly.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
As an alternative to ST_STM32_DT_INST_PINCTRL, provide
ST_STM32_DT_PINCTRL macro and set of matching internal macros.
This could be used by device drivers that can't use directly
device instances but rather the node label identifier. For instance:
ST_STM32_DT_PINCTRL(0, i2c1);
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Current set of helpers provided for STM32 pinctrl devicetree are
using device instance as input.
In order to prepare for next version that will take node identifier
as input, change existing set of macros using _INST_ namespace.
Additionally rename NODE_ID_FROM_PINCTRL to
ST_STM32_DT_INST_NODE_ID_FROM_PINCTRL.
Finally update existing macros users to this new name scheme.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Before adding new macros, clean up existing file:
* Provide full length description for each macro
* Cascade the device instance pinctl- property index so that
any pinctrl- instance number could be used
* Remove intermediate ST_STM32_DT_PIN macro
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The PLL Q divisor does not exist on stm32g0X0 variants. It should only
be configured for g0X1 variants.
Signed-off-by: Eric Hay <EHay@sierrawireless.com>
In npcx7 series, there're 8 Pulse Width Modulator (PWM) modules and each
one support generating a single 16-bit PWM output. A 16-bit clock
prescaler (PRSCn) and a 16-bit counter (CTRn) determine the cycle time,
the minimal possible pulse width, and the duty-cycle steps.
Beside introducing pwm driver for Nuvoton NPCX series, this CL also
includes:
1. Add PWM device tree declarations.
2. Zephyr PWM api implementation.
3. Add aliases in npcx7m6fb_evb board device tree file for supporting
samples/basic/blinky_pwm application and pwm test suites
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Change default pinmux of functional pads to GPIOs. It includes:
1. PIN96.A0.A2.A4 - If internal flash is supported
2. PIND2.00 - Default PSL inputs
3. PIN31.30.27.26.25.24.23.22 - Keyboard inputs
4. PIN21.20.17.16.15.14.13.12.11.10.07.06.05.04.82.83.03.B1 - Keyboard
outputs
5. Add description for soc_pinctrl_mux_configure() usage.
It also fixed the typo and inverse mistakes in npcx7-alts-map.dtsi.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Do not assume `reg_size` to be a multiple of 4 and
divide it on each call, expect the caller to provide
an already divided value instead.
This change require the LiteX GPIO driver to be modified,
which will come in the following commit.
Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
This CL adds more comments for each macro functions used for device tree
file for better explanations. It also changes all hex values in soc.c to
lower case.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This CL contains the drivers of NPCX Host Sub-Modules that serve as an
interface between the Host and Core domains. For most of them, the Host
can configure these modules via eSPI(Peripheral Channel)/LPC by
accessing 'Configuration and Control register Set' which IO base address
is 0x4E as default. And the interrupts in core domain help handling any
events from host side.
In this commit, we introduced six host sub-modules. It includes:
1. Keyboard and Mouse Controller (KBC) interface.
2. Power Management (PM) channels.
3. Shared Memory mechanism (SHM).
4. Core Access to Host Modules (C2H).
5. Mobile System Wake-Up functions (MSWC).
6. Serial Port (Legacy UART)
The tasks in application layer such as 8042, ACPI and host command can
cooperation with this driver by connecting api or callback functions.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
In npcx7 series, all of them support the Intel Enhanced Serial
Peripheral Interface (eSPI) Revision 1.0. This specification provides a
path for migrating host sub-devices via LPC to a lower pin count, higher
bandwidth bus. In addition to Host communication via the peripheral
channel, it provides virtual wires support, out-of-band communication,
and device mastering option over the Chipset SPI flash.
Becisdes introducing eSPI device in npcx7, this CL also includes:
1. Add eSPI device tree declarations.
2. Add npcx7-espi-vws-map.dtsi to present the relationship between eSPI
Virtual-Wire signals, eSPI registers, and wake-up input sources.
3. Zephyr eSPI api implementation.
4, Add OOB (Out of Band tunneled SMBus) support.
5. Add configuration files for eSPI test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Provides tool set to be used by device drivers in order to be able
to configure device signals.
This does not involve the implementation of a dedicated pinctrl
driver. In this regard, this is equivalent to implementation used
for treatment of current pinmux.c files.
Since STM32F1 uses a different GPIO configuration scheme, its
support is exlcuded for now.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
We need the same logic for each SOC, instead of copypasting
things just put this in a common file. This approach still
leaves the door open for custom memory layouts if desired.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
STM32L151xC SoC differs from other L1 SoCs in RAM (32KiB) and
flash (256KiB) size, and amount of interrupts (57, see STM32Cube).
Devicetree and Kconfig support.
Signed-off-by: Noelle Clement <noelleclement@hotmail.com>
Adds imx rt support.
Allows n-number of can interfaces based on device-tree.
Adds a "common" irq name.
Added CAN bus pins and dts for 1060 and 1064 EVK.
Signed-off-by: Rick Talbott <rtalbott@fastmail.com>
The standard and static MMU regions (_code, _rodata and _data) are
already covering all the available SRAM region and all the needed
sections. Remove the overlapping SRAM region.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
We only need to offset the start of the non-secure image
by 0x400, if TFM is built with BL2 support. In this case
we use the ROM_START_OFFSET Kconfig switch and set to
0x400. This instructs the linker to offset the beginning
of the ROM section by 0x400. In other words, we do not need
to statically move the start of the image by 0x400. This
fixes an issue that prevents from running Zephyr + TFM
without BL2 on Musca B1.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We only need to offset the start of the non-secure image
by 0x400, if TFM is built with BL2 support. In this case
we use the ROM_START_OFFSET Kconfig switch and set to
0x400. This instructs the linker to offset the beginning
of the ROM section by 0x400. In other words, we do not need
to statically move the start of the image by 0x400. This
fixes an issue that prevents from running Zephyr + TFM
without BL2 on MPS2 AN521.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When we wake-up of deep sleep power state, we want to disable it.
Otherwise, when the cpu will go next to idle mode during a
SYS_POWER_STATE_ACTIVE, it will go into deep sleep mode
instead of a sleep mode.
fixes: #26896
Signed-off-by: Julien D'Ascenzio <julien.dascenzio@paratronic.fr>
This STM32 serie redefines function relocate_vector_table()
It should take into account features:
SW_VECTOR_RELAY and SW_VECTOR_RELAY_CLIENT
fixes#28289
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Select the controller feature support for data length and LE 2M PHY
based on the SoC hardware capabilities instead of relying on SoC
family.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
0.5 Mhz with 100 ticks per sec leaves 5000 cycles per tick,
which broke some tests that assumed more work within 1 tick.
Set to 1 Mhz: balance multi-core simulation speed and tick duration.
Fixes#27943
Signed-off-by: Ruud Derwig <Ruud.Derwig@synopsys.com>
The commit aac9e2c5e3
("device: Revise how initialization status is being handled") highlights
an initialization priority issue between the clock and pinmux device.
Since this commit Zephyr is not booting anymore on LPC11U6x MCUs. The
clock driver gets a NULL pointer when calling device_get_binding() to
retrieve the pinmux device. It is because the pinmux device is not
initialized yet due to a lesser priority.
This patch fixes this issue by ensuring that Zephyr initializes the
pinmux device before the clock device.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Employ the nRF-specific timing calculations framework
(based on TIMER peripheral) only if the DWT is not present
on the SoC.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
nRF51 TIMER2 periperhal does not have the 32-bit
bitmode, so we need to fallback to the bitmode 16.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add timing functions and APIs. This is now used with some of the tests
we have for performance and metrics and will be used whereever timing
informations are needed, for example for tracing, profiling and other
operations where timing info is critical.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The dmamux requires HEAP size definition, so that k_malloc
is valid. The HEAP size config is defined in the common for
any stm32 soc instead of specific to dma Kconfig
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add devicetree support to specify bias-pull-up, bias-pull-down, and
drive-open-drain for pin configuration.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fixed 'line length exceeds 80 columns' warning by shortening the clock
controller device name from NPCX_CLOCK_CONTROL_NAME to
NPCX_CLK_CTRL_NAME.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
The general DMA driver doesn't use kmalloc anymore so it doesn't
need a memory pool. The DMAMUX_SMT32 driver still uses kmalloc,
so move the HEAP_MEM_POOL_SIZE config under DMAMUX_STM32.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
Typically we have ARC core configurations where Fast IRQs (FIRQ) are
enabled together with multiple register files and those we have covered
by testing. But FIRQ & single register bank we only happen to have on
the older EMSK v2.2.it might be a good idea to add a similar
configuration to nSIM "boards" so that we keep it tested regularly.
nsim_em7d_v22 configuration is similar with em_staterkit_em7d_v22,
both configed with FIRQ & single register bank.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
Assuming we stay on default Power Scale 1,
overdrive is required when System Core Clock frequency is higher
than 180MHz.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Most drivers make use of the HW semaphore (see `stm32_gpio.c`), but the
HSEM clock isn't currently setup on the MCU side. This means we rely on
the MPU to enable this clock, which is an unsafe bet: the OS running on
the MPU may not have support for HSEM, or it might enter sleep state,
which will disable the clock. As a consequence, firmwares loaded from
the MPU running this OS will block on the first `z_stm32_hsem_lock()`
call.
As it is required to run anything on the MCU core, we shouldn't assume
the HSEM clock is already active when booting and enable it in the SoC
init, the same way it is done for the STM32H7.
Signed-off-by: Arnaud Ferraris <arnaud.ferraris@collabora.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Replace npcx register base address type, uint32_t, with uintptr_t.
It is easier to know what type of base address and for linear
addresses treated as integral values.
This CL also modified IS_BIT_SET() macro function to fit MISRA code
guidelines.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Add gpio support for Nuvoton NPCX series. This CL includes:
1. Add GPIO device tree declarations.
2. Introduce wui_maps property in yaml file to present relationship
between Wake-Up
Input (WUI) and 8 IOs belong to the device.
3. Zephyr GPIO api implementation.
4. GPIO callback functions implementation with MIWU api functions.
5. Overlay file for gpio basic tests
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
The device Multi-Input Wake-Up Unit (MIWU) supports the embedded
controller (EC) to exit 'Sleep' or 'Deep Sleep' power state which allows
chip has better power consumption. Also, it provides signal conditioning
such as 'Level' and 'Edge' trigger type and grouping of external
interrupt sources of NVIC. The NPCX series has three identical MIWU
modules: MIWU0, MIWU1, MIWU2. Together, they support a total of over 140
internal and/or external wake-up sources.
In this CL, we use device tree files to present the relationship bewteen
MIWU and the other devices in different npcx series. For npcx7 series,
it include:
1. npcx7-miwus-int-map.dtsi: it presents relationship between MIWU group
and NVIC interrupt in npcx7. Please notice it isn't 1-to-1 mapping.
2. npcx7-miwus-wui-map.dtsi: it presents relationship between input of
MIWU and its source device such as gpio, timer, eSPI VWs and so on.
This CL also includes:
1. Add MIWU device tree declarations.
2. MIWU api function declarations and implementation to configure signal
conditions and callback function mechanism. They can be be classified
into two types. One is for GPIO which connects original gpio callback
implemetation and the other is for generic devices such as timer,
eSPI, and so on.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
To indicate that the CLOCK and POWER peripherals are present in those
SoCs, thus the corresponding nrfx drivers can be used.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Commit e80e655b01 introduced linker script
enforcement of Cortex-M vector table alignment. Update the i.MX RT boot
header to account for the possibility that the vector table may not be
placed at the address CONFIG_FLASH_BASE_ADDRESS +
CONFIG_ROM_START_OFFSET anymore.
For example, the RT1060 vector table has 176 entries and therefore must
be aligned to 0x400 bytes. If CONFIG_FLASH_BASE_ADDRESS=0x60000000 and
CONFIG_ROM_START_OFFSET=0x2200, the linker script will place the vector
table at 0x60002400 instead of 0x60002200.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Use new KConfig switches to configure debug support.
Correct ADC configuration where all ADC pins are in ADC mode.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Currently JTAG debug is enabled by default.
In some designs is desirable to disable JTAG functionality.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Add support for the Cortex-M1 ARM DesignStart FPGA SoC. This is not an
SoC in the traditional sense but more of a base to build an SoC upon.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Its possible to rename the executable we build via the Kconfig symbol
CONFIG_KERNEL_BIN_NAME. So we really should use ${KERNEL_ELF_NAME},
${KERNEL_BIN_NAME} and ${KERNEL_HEX_NAME} variables instead of hardcoded
zephyr.elf, zephyr.bin, and zephyr.elf.
This fixes an build issue with
tests/misc/test_build/buildsystem.kconfig.utf8_in_values on
up_squared_adsp and lpcxpresso11u68 platforms.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Skeleton board support for the npcx7m6fb evaluation board from Nuvoton
Technology. This CL also includes:
1. Add ecst python scripts to append the header used by NPCX ROM.
2. Add openocd configuration scripts for "west flash".
3. Add monitor FW binary file for programing/verifying embedded flash
in NPCX series.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Add pin controller support for Nuvoton NPCX series
Add pin-mux controller support for Nuvoton NPCX series.
This CL includes:
1. Add pin controller device tree declarations and introduce alt-cells
to select pads' functionality.
2. Add npcx7-alts-map.dtsi since the mapping between IO and controller
is irregular and vary in each chip series.
3. Add nuvoton,npcx-pinctrl-def.yaml and its declarations to change all
pads' functionality to GPIO by default.
4. Pinmux controller driver implementation.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Add clock controller support for Nuvoton NPCX series. This CL includes:
1. Add clock controller device tree declarations.
2. Introduce clock-cells in yaml file clock tree to get module's source
clock and turn off/on the its clock
3. Clock controller driver implementation.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Initial support for Nuvoton NPCX7M6FB SoC of NPCX series which is a chip
family of embedded controllers (EC) and targeted for a wide range of
portable applications. We implemented the SoC skeleton in
soc/arm/nuvoton_npcx since there're many chip families in Nuvoton and
aim to different markets such as PC, General MCU, and Audio. The
architectures and hardware modules are different between them. Hence, we
suggest using the company name plus with chip series for better
understanding.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This file is setting Kconfig options even when it is not the chosen
SoC. I noticed this because without this patch, CONFIG_SOC_GECKO_EMU=y
when building for an unrelated board with SYS_POWER_MANAGEMENT=y.
Hide any subtrees in this file when the EXX32 family isn't selected.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
unify how XIP is configured across architectures. Use imply instead of
setting defaults per architecture and imply XIP on riscv arch and remove
XIP configuration from individual defconfig files to match other
architectures.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
IEEE 802.15.4 is available for each board with Nordic SOC implementing
this protocol. Because of that protocol configuration shall be tied to
SOC instead of board.
Signed-off-by: Hubert Miś <hubert.mis@nordicsemi.no>
On CC13x2/CC26x2, power.c should be built when either system or device
power management is enabled. Currently it is only doing so for the
former.
Fixes#27392
Signed-off-by: Vincent Wan <vwan@ti.com>
Some parameters (e.g., tuning capacitors) can be configured in the
CMU_HFXOInit_TypeDef and CMU_LFXOInit_TypeDef structures before calling
CMU_HFXOInit() and CMU_LFXOInit() during clock initialisation.
Signed-off-by: Steven Lemaire <steven.lemaire@zii.aero>
This commit introduces support for multiple SOC_ROOT.
This means that additional SOC_ROOTs specified using -DSOC_ROOT as
argument to CMake will be forming a list together with ${ZEPHYR_BASE}.
This allows for greater flexibility, as developers can now specify
multiple out-of-tree SoCs and not worry about the SoC used for the
board they compile for.
Also it avoid code, such as:
if(BOARD STREQUAL my_board_using_out_of_tree_soc)
set(SOC_ROOT some/out/of/tree/soc/path)
endif()
in application CMakeLists.txt.
Finally, allowing multiple SOC_ROOTs prepares for specifying SOC_ROOTs
in Zephyr modules.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit is a cleanup of the SOC_DIR usage.
This cleanup is a preparation for supporting a list of SOC_ROOT instead
of just allowing one SOC_ROOT.
Supporting a list of SOC_ROOTs allows for placing of SOC in Zephyr
modules. It also aligns how BOARD_ROOT supports a list, and thus usage
of n_ROOT in Zephyr becomes more consistent.
This commit introduces the following changes:
- soc/xtensa/intel_apl_adsp/bootloader.cmake removed.
This file is not included elsewhere in the build system, and appears
to be leftover from #25133. Almost identical content is found in
`soc/xtensa/intel_apl_adsp/commonbootloader.cmake`
- Changed xtensa/intel_apl_adsp to named library. Using a named library
allow fetching library files based on library name without the need to
know build path (and thus removes the need for knowing `${SOC_DIR}`).
- Changed SOC_DIR/ARCH/SOC_FAMILY to use CMAKE_CURRENT_LIST_DIR for
configure time commands, as CMake code is already located inside this
path.
- Using generator expression for library files from other CMake targets.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Manage Dual core boot automatically whatever Option Bytes
configuration.
No more need of KConfig STM32H7_DUAL_CORE_BOOT to match
Option Bytes.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
This board doesn't have any known users and is not really maintained
anymore, so just remove it.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
This patch adds the iap.h header file which provides an entry function
for the IAP (In-Application Programming) interface. Note that the IAP
commands are located in the boot ROM code. Mostly they provide access
to the on-chip flash and EEPROM devices.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
This commit adds basic support for the clock controller used in
lpc11u6x MCUs.
Signed-off-by: Maxime Bittan <maxime.bittan@seagate.com>
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
This patch adds a pinmux driver allowing to configure the IOCON (I/O
control) registers found on the LPC11U6x MCUs.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
We cannot call into the power library API as it is currently
available in binary format which cannot be included
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add HSE,HSI,CSI,PLL as system clock options.
Also add correct configuration of the PLL.
New sysclk options:
- HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y
- HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y
- CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y
Existing sysclk options:
- PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
PLL clock options:
- More PLL source clocks:
Existing:
1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
New:
2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y
- PLL vco input range is auto-calculated based on PLL DIVM1
-> Example for sysclock 96MHz generated with PLL from HSI
CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2
Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h
instead to setup the correct latency.
Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
This adds a new config option for SAM0 targets that use the BOSSA
bootloader. If the CDC ACM driver is also enabled, then the
programmer can automatically reset the board into the bootloader for
programming.
Signed-off-by: Michael Hope <mlhx@google.com>
The optional SOC_CONTEXT carries processor state registers that need to
be initialized properly to avoid uninitialized memory read as processor
state.
In particular on the RV32M1 the extra soc context stores a state for
special loop instructions, and loading non zero values will have the
core assume it is in a loop.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
Saving an extended context for RV32M1 should be optional, but it was
broken due to the offset calculation not taking the according option
into account.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
x19 is callee saved register. z_arch_el3_plat_init being a callee,
it should save it before using it. However, at this point, stack
has not been setup. So, let's just use x20 instead which is not
being used caller yet. This bug was causing VBAR_EL1 corruption,
but since [10:0] bits are reserved, bug was hidden.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
The `TEXT_SECTION_OFFSET` symbol is used to specify the offset between
the beginning of the ROM area and the address of the first ROM section.
This commit renames `TEXT_SECTION_OFFSET` to `ROM_START_OFFSET` because
the first ROM section is not always the `.text` section.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
In case of dualcore, STM32H7, STM32W and STM32MP1,
protect concurrent register write access with HSEM.
Done for following drivers:
clock_control, counter, flash, gpio, interrupt_controller
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Various cleanups to the x86 early serial driver, mostly with the goal
of simplifying its deployment during board bringup (which is really
the only reason it exists in the first place):
+ Configure it =y by default. While there are surely constrained
environments that will want to disable it, this is a TINY driver,
and it serves a very important role for niche tasks. It should be
built always to make sure it works everywhere.
+ Decouple from devicetree as much as possible. This code HAS to work
during board bringup, often with configurations cribbed from other
machines, before proper configuration gets written. Experimentally,
devicetree errors tend to be easy to make, and without a working
console impossible to diagnose. Specify the device via integer
constants in soc.h (in the case of IOPORT access, we already had
such a symbol) so that the path from what the developer intends to
what the code executes is as short and obvious as possible.
Unfortunately I'm not allowed to remove devicetree entirely here,
but at least a developer adding a new platform will be able to
override it in an obvious way instead of banging blindly on the
other side of a DTS compiler.
+ Don't try to probe the PCI device by ID to "verify". While this
sounds like a good idea, in practice it's just an extra thing to get
wrong. If we bail on our early console because someone (yes, that's
me) got the bus/device/function right but typoed the VID/DID
numbers, we're doing no one any favors.
+ Remove the word-sized-I/O feature. This is a x86 driver for a PCI
device. No known PC hardware requires that UART register access be
done in dword units (in fact doing so would be a violation of the
PCI specifciation as I understand it). It looks to have been cut
and pasted from the ns16550 driver, remove.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
When building for nRF5340 PDK board, enable Kconfig option
for Erratum 19. Do not enable when building on nRF5340 DK.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add and mark PCIe highmem outbound memory as nGnRnE device memory
in Viper SoC MMU configuration.
Increase VA/PA bits to 36-bits to support the same.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
ZEPHYR_SDK_INSTALL_DIR will be set as an internal CMake variable when
using the Zephyr SDK.
The Zephyr SDK zephyr/host-tools.cmake will ensure to set the CMake
ZEPHYR_SDK_INSTALL_DIR variable to the environment setting, or the
install directory in case the CMake package was used.
Users not using the environment variable will experience the following
error:
```
Linking C executable zephyr/.../bootloader/bootloader.elf
FAILED: zephyr/.../bootloader/bootloader.elf
<path>/xtensa-zephyr-elf/bin/ld: cannot find -lhal
```
This commit ensures code build correctly both when setting the
environment variable ZEPHYR_SDK_INSTALL_DIR, and when using Zephyr SDK
CMake `find_package(Zephyr-sdk)`
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This patch introduces the support of low power modes
for the STM32WBxx from STMicroelectronics based on the lptim
Here, the power modes are sleep modes have lptimer as wakeup source.
The sleep modes are configured by the SYS_POWER_MANAGEMENT.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add initial support for nuvoton numicro m48x SoC series, basic
init and uart functionality are covered with gpio and clock
directly relies on HAL.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
This enables PWM and connects it to the main LED. Tested by running
samples/basic/blinky_pwm and /fade_led.
Signed-off-by: Michael Hope <mlhx@google.com>
The SAM0 Timer/Counter for Control Applications can act as a counter
or generator. Add a binding for the TCC in PWM mode and helper to
check the compat mode.
Signed-off-by: Michael Hope <mlhx@google.com>
Add reset interrupt handlers for all three types of reset
interrupts that iProc PCIe EP can receive - namely PERST,
INB PERST and FLR.
Signed-off-by: Shivaraj Shetty <shivaraj.shetty@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Change the SAM0 to match other boards by selecting the SAM0 specific
driver when a driver class is selected.
For example, automatically enable CONFIG_SPI_SAM0 when CONFIG_SPI is
enabled.
Signed-off-by: Michael Hope <mlhx@google.com>
Only boards with at least 64K Flash will activate MPU because:
MPU + UERSPACE + All switches implicity activated
(CONFIG_MPU_STACK_GUARD, CONFIG_ARM_STACK_PROTECTION ...)
will consume about 40K Flash
(value computed on nucleo_f767_zi on tests/arch/arm/arm_ramfunc/).
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
The PWM drivers has been refactored using the HAL LL API. Not only that,
but the set pin_set function is now faster, as channel output compare is
just initialized if needed.
NOTE: Has been tested using H743zi board for now.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Previously, DTS specification of physical RAM bounds did not
correspond to the actual bounds of system RAM as the first
megabyte was being skipped.
There were reasons for this - the first 1MB on PC-like systems
is a no-man's-land of reserved memory regions, but we need DTS
to accurately capture physical memory bounds.
Instead, we introduce a config option which can apply an offset
to the beginning of physical memory, and apply this to the "RAM"
region defined in the linker scripts.
This also fixes a problem where an extra megabyte was being
added to the size of system RAM.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Introduced interface for efficient logging from external logsystems:
Added handling of vaargs and automatic strdup to macros intended
to be used in logging interface function. Fast path to less then 4
arguments to speed up the execution. Made log_count_args external,
if external logsystem cannot count arguments.
Signed-off-by: Tomasz Konieczny <tomasz.konieczny@nordicsemi.no>
Those MCUs have 2KB RAM and 16KB FLASH memory, but they are still
powerful enough to run small configuration of Zephyr RTOS.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Added / Tested support for RNG on the STM32F767ZI nucleo board.
Updated the SoC defconfig to auto-enable the driver when
ENTROPY_GENERATOR is enabled, and updated the board README.
Signed-off-by: Bilal Wasim <bilalwasim676@gmail.com>
- Change default CPU Clock to 240MHz
(PLL is activated)
- I2C, UART will use sysclk from clock driver
- esp32_enable_peripheral replaced by
clock_control_on
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
- Support PLL for Higher Frequencies 80,160,240 MHz
- Support XTAL Frequencies 26MHz, 40MHz
- Clock Driver can't be disabled, because all of the other drivers
will depend on it to get their operating Frequency based on chosen
clock source (XTAL/PLL).
- Add needed references to BBPLL i2c bus ROM functions.
- Add `rtc` node to Device Tree.
- Since All Peripherals Frequency is depending on CPU_CLK Source,
`clock-source` property added to CPU node
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
This patch introduces the support of low power modes
for the STM32L4xx from STMicroelectronics based on the lptim
Here, the power modes are sleep modes with lptimer as wakeup.
Depending on the SYS_POWER_MANAGEMENT configuration.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
tested on mimxrt1060_evt
MEMORY_NOCACHE is needed
test on frdmk64f
special test slot need configure with
CONFIG_DMA_TEST_SLOT_START
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Remove Kconfig, linker script, and related bits associated with
CUSTOM_RODATA_LD, CUSTOM_RWDATA_LD, CUSTOM_SECTIONS_LD,
SOC_NOINIT_LD, SOC_RODATA_LD, and SOC_RWDATA_LD options that have been
deprecated since Zephyr 2.2.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This option controls whether additional BLE support is
enabled for the cc13xx_cc26xx platform in hal/ti and
subsys/bluetooth.
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
Introduce switch to allow board configuration for VCI pins to
remain HW-controled depending on the design.
Currently pins are always configured as GPIOs which is not always
desirable.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
The NXP's Kinetics K66F is able to run with max frequency of 180MHz.
To achieve this goal the SMC's PMPROT and PMCTRL registers need to be
adjusted.
On the contrary the K64F doesn't support HSRUN run mode.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This option enables support for High Speed RUN operation mode for
K66F. The K64F SoC doesn't support this mode.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Add the necessary clock configuration to support STM32L-based
SoCs. This change likely adds support for other STM32 SoCs as well
since the HSI48 clock is configured for all SoCs that support it
(except the STM32L4x) instead of just the STM32G4X.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
emsdp_em7d_esp is a board with secure just like em_starterkit_em7d,
but the secure feature not configed in defconfig file. we need to add
below configs in emsdp_em7d_esp_defconfig files:
CONFIG_ARC_HAS_SECURE=y
CONFIG_TRUSTED_EXECUTION_SECURE=y
when secure feature enabled, we use secure timer for system tick, so
we need to add below macro for secure timer:
#define IRQ_SEC_TIMER0 20
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
This commit fixes Cortex-M header inclusions from the deprecated paths.
The Cortex-M headers were relocated from `include/arch/arm/cortex_m` to
`include/arch/arm/aarch32/cortex_m` by the refactoring done in the
commit d048faacf2.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Now when we're finally ready to open QEMU port for ARC
we introduce the first ever platform it supports and in fact does
that quite well - Zephyr RTOS.
For now we only offer support of basic EM & HS code execution,
built-in timers, interrupt controller and set of very simple
peripherals: DW UART & optionally MMIO Virtio devices.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This is defining the SYS_CLOCK_TICKS_PER_SEC default value
depending on the LPTIM CLOCK frequency in case of LPTIMER,
to get a TICK value as a divider of the LPTIM clock source.
It gives a better result in formulas when converting
ticks to count unit.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This adds a helper function for reading LiteX 64-bit CSRs
to be used by LiteX drivers.
Signed-off-by: Jakub Cebulski <jcebulski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
emsdp is a FPGA based platform, can be loaded with different
configurations. Different configuration have different
interrupts:
* em5d, em7d and em11d have 111 interrupts
* em4 and em6 have 113 interrupts
* em7d_esp has 112 interrupts
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
UARTs and I2C controllers are accessed through MMIO and
these regions need to be added to MMU for proper access.
This also enable MMU for Apollo Lake by default since
serial console is now usable.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This file consists only of an array of per-CPU IOAPIC ID's that
overrides the weak symbol defined by the architecture.
The IOAPIC IDs are only used when targetting a startup IPI for the
auxiliary right now, but the IDs are the IDs and represent hardware
truth. They should be correct even if unused.
Using the wrong ones also breaks the tests/kernel/mp test, which calls
arch_start_cpu() when not in SMP mode as a deliberate unit test.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The APIC timer is not supported e.g. with SMP (which will be enabled
by default soon as well) so the sensible choice is to default to HPET.
Also, the default makes more sense to be on the SoC side, so move it
there from the board defaults.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The nodelabel references for the GPIO region MMU setup were incorrect.
The nodelabel names didn't match what is in the dts. Fix this otherwise
we get a compile error when enabling the functionality.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Several reviewers agreed that DT_HAS_NODE_STATUS_OKAY(...) was an
undesirable API for the following reasons:
- it's inconsistent with the rest of the DT_NODE_HAS_FOO names
- DT_NODE_HAS_FOO_BAR_BAZ(node) was agreed upon as a shorthand
for macros which are equivalent to
DT_NODE_HAS_FOO(node) && DT_NODE_HAS_BAR(node) &&
- DT_NODE_HAS_BAZ(node), and DT_HAS_NODE_STATUS_OKAY is an odd duck
- DT_NODE_HAS_STATUS(..., okay) was viewed as more readable anyway
- it is seen as a somewhat aesthetically challenged name
Replace all users with DT_NODE_HAS_STATUS(..., okay), which is
semantically equivalent.
This is mostly done with sed, but a few remaining cases were done by
hand, along with whitespace, docs, and comment changes. These special
cases include the Nordic SOC static assert files.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The Atmel SAM D21 SoC, according to the original Atmel datasheet
(Atmel-42181N), has 28 interrupt lines (0-27).
There have been mysterious changes in the number of interrupt lines and
on-chip peripherals in the recent Microchip datasheet releases, but
there is no explicit information available for this (e.g. PCN), so we
take the safest approach by assuming the lowest interrupt line number.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Make it possible for an application to set CONFIG_I2C=n if it wants.
The unconditional select was making this impossible due to resulting
unmet dependencies.
This is also in line with what some other SoC definitions do with I2C.
Fixes#25204
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
PSA level 1 requires secure boot. TF-M BL2 is the official
secure boot loader. It needs a BL2_HEADER_SIZE offset.
Align nonsecure address with TF-M's NS slot while TF-M BL2 enabled.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
Add infineon XMC4 series UART support. Driver supports
only poll mode using XMCLib.
Out of 4 available UART's on SoC, only UART1 is confgired
by default in UART mode until GPIO & pinctrl support.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Add infineon xmc series with XMC4500 support. XMC series comes with,
- CPU operates upto 120MHz
- 3 RAM (PSRAM1 - code, DSRAM1 - data and DSRAM2 - communiation)
- upto 1MB flash
init: clock control & gpio is not done, so SoC initialization directly
relies on HAL. Core operating clock is stored in no_init section, which
is kept under DSRAM1. Only DSRAM1 is used until clock support. Using
PSRAM1 and DSRAM1 needs adaptation in linker script - planned for next
revision.
Note: SystemInit cannot be consumed directly due to vector table +
HAL linker dependency.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Add initilizations for:
- Cortex-A72 L2 Controller configurations. This initialization to
be done when cluster is in quiscent state.
- 'ICC_SRE_EL3' init to allow GIC V3 ICC_SRE_ELx system interface.
This initialization can be done at 'EL3' only.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Swap this out and make the status a parameter.
Leave a couple of cases of DT_NODE_HAS_COMPAT().
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
These are redundantly checking a node's status twice.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Usually, we want to operate only on "available" device
nodes ("available" means "status is okay and a matching binding is
found"), but that's not true in all cases.
Sometimes we want to operate on special nodes without matching
bindings, such as those describing memory.
To handle the distinction, change various additional devicetree APIs
making it clear that they operate only on available device nodes,
adjusting gen_defines and devicetree.h implementation details
accordingly:
- emit macros for all existing nodes in gen_defines.py, regardless
of status or matching binding
- rename DT_NUM_INST to DT_NUM_INST_STATUS_OKAY
- rename DT_NODE_HAS_COMPAT to DT_NODE_HAS_COMPAT_STATUS_OKAY
- rename DT_INST_FOREACH to DT_INST_FOREACH_STATUS_OKAY
- rename DT_ANY_INST_ON_BUS to DT_ANY_INST_ON_BUS_STATUS_OKAY
- rewrite DT_HAS_NODE_STATUS_OKAY in terms of a new DT_NODE_HAS_STATUS
- resurrect DT_HAS_NODE in the form of DT_NODE_EXISTS
- remove DT_COMPAT_ON_BUS as a public API
- use the new default_prop_types edtlib parameter
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This commit adds basic support for nRF52820 SoC.
Changes affect introducing:
- architecuture files (dtsi)
- configuration of nrfx drivers
- adaptation of inclusions based on chosen SoC
Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
Changes:
- Added all required board files in /boards/arm/96b_aerocore2
- Modified pinmux for stm32f4
Most of the changes in this PR is based on reverse-engineering of the
PCB layout and following commits in the PX4 firmware repository for
the same board. The manufacturer does not provide and or generate
schematics and pinout tables for this board.
This PR includes almost all of the interfaces connected to the STM32
MCU, the only thing not included is the J9 and J8 headers that connect
to a 96Boards baseboard.
These headers are not vital to the functionality of the Aerocore2.
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
Add STM32F427. This is mainly aimed towards the stm32f427vi.
Changes:
- Add stm32f427 support based on previous work
done for the stm32f429.
- Rework currunt stm32f429 implimentation to now
be based on stm32f427.
- Introduce dedicated dtsi for the VI variant of both
stm32f427 and stm32f429. This is done to prevent stm32f4.dtsi
from being included twice.
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
The SAM V71 SoC configuration currently selects the `ARM_MPU` symbol
and this effectively forces MPU usage on the SoC.
This commit removes `ARM_MPU` selection from the SoC Kconfig since it
is intended to be selected by a board, and the `CPU_HAS_ARM_MPU` symbol
already indicates that the SoC supports ARM MPU.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The SAM E70 SoC configuration currently selects the `ARM_MPU` symbol
and this effectively forces MPU usage on the SoC.
This commit removes `ARM_MPU` selection from the SoC Kconfig since it
is intended to be selected by a board, and the `CPU_HAS_ARM_MPU` symbol
already indicates that the SoC supports ARM MPU.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Add initial support for Broadcom Viper SoC.
It has ARM Cortex-M7 and Cortex-A72 cores.
Signed-off-by: Arjun Jyothi <arjun.jyothi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Use MSI as PLL source. This enables to run system clock at 110MHz.
To achieve this, voltage regulator should be set to scale 0.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This patch defines the dma feature for the stm32wbXX
and the dmamux feature for the stm32wb55x
soc series from STMicroelectronics
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add support for ADC on H7 series. Note that ADC1 and ADC2 share the same
register set, so it is added as "adc1_2".
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
All pin configuration for ATMEL SAM SoC come from devicetree so we can
now remove the soc_pinmap.h header files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert i2s_sam_ssc driver to utilize devicetree. We replace Kconfig
options for specifying the DMA configuration (channel, DMA device name)
with getting that from devicetree. We also get pincfg from devicetree,
however we still have Kconfig sybmols to specify if the RF or RK pin is
enabled.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Due to a typo compiling the WWDG on the g4 family does not
work. This adds the correct include filename.
Signed-off-by: Richard Osterloh <richard.osterloh@gmail.com>
High Speed Flexcomm device that handles high speed SPI transfer are
mapped to the same High Frequency clock that the ARM core uses.
This allows for higher frequency SPI traffic.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Port the usage of the timeouts to the new timeout API, in order to be
able to deselect the legacy timeout option.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Convert to using DT_INST_LABEL() in the dma driver and convert dma users
to use the DMA property macros to get the dma controller name. We make
the assumption in the drivers that there is a single DMA controller
instance.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Some Kinetis SoCs have an instance of the the TPM module
that can be used for PWM control. As such, add the necessary
configurations to enable it on the SoCs that support it, as well as
enable the clock for the module to function.
In this case, the enablement is done only for the KW41Z SoCs,
but there are other SoCs that support it, f.i. KW38Z
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Enable I2S_STM32 in the soc common part, so it will no
longer be required in board default configuration.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Rename DT_HAS_NODE to DT_HAS_NODE_STATUS_OKAY so the semantics are
clear. As going forward DT_HAS_NODE will report if a NODE exists
regardless of its status.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert DT_CODE_PARTITION_{OFFSET,SIZE} to use new
DT_REG_ADDR/DT_REG_SIZE macros instead based on
DT_CHOSEN(zephyr_code_partition).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The riscv linker scripts utilize DT_FLASH_BASE_ADDRESS and
DT_FLASH_SIZE, as we want to phase out the old generator we need to
replace these defines with macros from devicetree.h.
We support two flash configurations at this point, either a QSPI flash
like on the hifive board or a SoC flash like on the rv32m1_vega. We
update the linker scripts to check the compat of the zephyr,flash node
and based on if its 'jedec,spi-nor' or 'soc-nv-flash' we determine how
to extract the "flash" base address and size.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As we phase out per instance Kconfig symbols convert to utilize
DT_NODELABEL for SPI and I2C instances instead.
Also updated comments to change from FLEXCOMM8 to HSLSPI.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove DT_ADC_{0..2}_NAME from dts_fixup.h, if this casues the
dts_fixup.h file to be empty we remove the file as well.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked sam_gmac driver to get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from soc_pinmap.h that are no longer needed due to
getting all that information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds the `devicetree.h` header inclusion in the Atmel SAM-
family SoC header files, as required by the ARM SoC conventions.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds the `devicetree.h` header inclusion in the Atmel SAM0-
family SoC header files, as required by the ARM SoC conventions.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Enable the driver for the Kinetis Digital-to-Analog (DAC) modules
present in the NXP Kinetis K6x SoC series.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Enable the driver for the Kinetis Digital-to-Analog (DAC32) module
present in the NXP Kinetis KE1xF SoC series.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Remove dts_fixup.h files that are needed anymore, remove defines that
are used, and replace defines with new DT macros.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move defines for _RAM_ADDR, _RAM_SIZE, _ROM_ADDR, and _ROM_ADDR into
the linker.ld and thus remove dts_fixup.h. We rework to use
DT_REG_ADDR and DT_REG_SIZE on DT_CHOSEN(zephyr_sram) and
DT_CHOSEN(zephyr_flash).
Also fixup use of _RAM_ADDR/_RAM_SIZE in newlib/libc-hooks.c.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove dts_fixup.h files that are not used (empty) or the defines aren't
used anymore and thus can be removed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert linker scripts and arc_mpu_regions.c setup to use new
devicetree.h macros to extract the base address and size of the various
memory regions (DDR, SRAM, FLASH, DCCM, ICCM). We also remove the
scaling up and down since DT_REG_SIZE() returns the value in bytes.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rework x86 linker scripts to use DT_REG_ADDR/DT_REG_SIZE on
DT_CHOSEN(zephyr_sram) and DT_CHOSEN(zephyr_flash). As part of this
we remove the dts_fixup.h. Using DT_REG_SIZE means we don't have to
adjust the sizes by 1024.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove dts_fixup.h files that are needed anymore, remove defines that
are used, and replace defines with new DT macros.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace DT_SNPS_ARCEM_0_CLOCK_FREQUENCY with a PATH based reference
to cpu@0 (DT_PATH(cpus, cpu_0)) and than getting the clock_frequency
property:
DT_SNPS_ARCEM_0_CLOCK_FREQUENCY ->
DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert from DT_MMIO_SRAM_10000000_BASE_ADDRESS to
DT_REG_ADDR(DT_NODELABEL(ddr0)) and similar for
DT_MMIO_SRAM_10000000_SIZE to DT_REG_SIZE().
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Complete STM32 conversion to new DT macros by removing
remaining occurences of DT_ST_STM32_ADC_FOO_LABEL.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
When we converted the GPIO driver to the new GPIO API we didn't update
the MMU mapping defines. Use the macros from devicetree.h and
nodelabel's to get the register base address and sizes for the GPIO
blocks.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Complete STM32 conversion to new DT macros by removing
remaining occurences of DT_ST_STM32_ADC_FOO_LABEL.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
During devicetree macro changes, LPSRAM_BOOT_VECTOR_ADDR
pointed to another macro which was renamed to a non-existent
one. Fix it so that SMP builds again.
Fixes#24720
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Rework the atom/linker.ld to match how ia32/linker.ld works with regards
to how PHYS_LOAD_ADDR & PHYS_RAM_ADDR are set based on CONFIG_XIP and
from which DT_PHYS_{RAM,LOAD}_ADDR defines. We update the minnowboard
dts and atom.dtsi files to keep in sync with this.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert ocram and sdram regions to use new macro DT_REG_ADDR() and
DT_REG_SIZE() with DT_NODELABEL to determine the various memories size
and base address.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use new DT_INST macros throughout. Removed per
instance Kconfig symbols and replaced with DT_NODELABEL references
where needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert the code for setting the clock IP source of the various IPs
present in the NXP KE1xF SoC series to the new DT API.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Convert driver to use the new device tree macro's instead of
dts_fixup.h based macros. This moves us closer to removing both
dts_fixup.h and per instance Kconfig symbols.
The pinmux_mchp_xec is also being updated since it's using DT
from GPIO.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Convert driver to use the new device tree macro's instead of
dts_fixup.h based macros. This moves us closer to removing both
dts_fixup.h and per instance Kconfig symbols.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Convert driver to use instance macro's instead of dts_fixup.h based
macros. This moves us closer to removing both dts_fixup.h and per
instance Kconfig symbols.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Replace DT_ARM_CORTEX_*_0_CLOCK_FREQUENCY with a PATH based reference
to cpu@0 (DT_PATH(cpus, cpu_0)) and than getting the clock_frequency
property:
DT_ARM_CORTEX_*_CLOCK_FREQUENCY ->
DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit renames the Kconfig `FLOAT` symbol to `FPU`, since this
symbol only indicates that the hardware Floating Point Unit (FPU) is
used and does not imply and/or indicate the general availability of
toolchain-level floating point support (i.e. this symbol is not
selected when building for an FPU-less platform that supports floating
point operations through the toolchain-provided software floating point
library).
Moreover, given that the symbol that indicates the availability of FPU
is named `CPU_HAS_FPU`, it only makes sense to use "FPU" in the name of
the symbol that enables the FPU.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Use DT_INST_FOREACH macro to combine code used for multiple instances.
Remove unnecessary Kconfig options and dts fixups for GPIO instances.
A side-effect to using DT_INST_FOREACH is that GPIO ports A0 and A3
are now enabled, whereas they were originally disabled by default as
an optimization.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Rename DT_L2_SRAM_* to just L2_SRAM_* and set it using new DT macros.
Do something similar for DT_LP_SRAM_* renamed to LP_SRAM_*
Updated the intel_gna driver as it used the DT_L2_SRAM_* defines.
This change also lets us remove dts_fixup.h on intel_s1000 and
intel_apl_adsp SoCs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked spi_sam driver to utilize new DT_INST macros as part of
this rework we also now get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Added ATMEL_SAM_DT_NUM_PINS macro which will return the number of pins
to initialize for "pinctrl-0" devicetree property.
Added ATMEL_SAM_DT_PINS macro which will create an array initializer
with all the pins associated with "pinctrl-0" devicetree property.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add wdt0 node labels for all watchdogs. Keep the existing wdt node
labels in place for backwards compatibility.
Add a wdt1 node to the nRF5340 application core .dtsi, but leave it
disabled. Leave the wdt node's label set to "WDT" on this core for
backwards compatibility also, in case any users are getting it with a
string literal instead of asking the devicetree. This can be changed
later after this round of watchdog changes has been shaken out and
tested more.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Convert the driver to use the new dt macros. As part of this change we
remove a bunch of defines that happened in dts_fixup.h that didn't
belong there. Some of these should be converted to devicetree
properties at some point.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The SAM E54 series SoCs include a single-precision FPU; therefore, the
`CPU_HAS_FPU` symbol should be selected.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The SAM E53 series SoCs include a single-precision FPU; therefore, the
`CPU_HAS_FPU` symbol should be selected.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The SAM E51 series SoCs include a single-precision FPU; therefore, the
`CPU_HAS_FPU` symbol should be selected.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The SAM D51 series SoCs include a single-precision FPU; therefore, the
`CPU_HAS_FPU` symbol should be selected.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The SAM D51, E51 and E53 SoC series Kconfig files were missing the
`ARM` architecture symbol selection.
This symbol must be selected at the SoC level; otherwise, build will
fail because the symbol is not selected by anything and other ARM-
specific configurations depend on it.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Replace DT_CPU_CLOCK_FREQUENCY with a PATH based reference to cpu@0
(DT_PATH(cpus, cpu_0)) and than getting the clock_frequency property:
DT_CPU_CLOCK_FREQUENCY -> DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
This lets us remove DT_CPU_CLOCK_FREQUENCY from dts_fixup.h.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Change DT_GPIO_GECKO_SWO_LOCATION to use new DT_INST and DT_PROP macros
and remove defining it in dts_fixup.h.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move the FPGA GPIO init to use the devicetree.h macros instead of
dts_fixup.h. This allows us to remove dts_fixup.h on mps2 based
platforms.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert old DT defines of the form DT_ARM_SCC_BASE_ADDRESS to
DT_REG_ADDR(DT_INST(0, arm_scc)). This allows us to remove dts_fixup.h
on musca boards.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use instance macro's instead of dts_fixup.h based
macros. This moves us closer to removing both dts_fixup.h and per
instance Kconfig symbols.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked adc_sam_afec driver to utilize new DT_INST macros as part of
this rework we also now get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use new DT_INST macros throughout. We also remove
defines in dts_fixup.h as they are no longer needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use new DT_INST macros throughout. We update one
sample app to use a nodelabel reference. We also remove defines in
dts_fixup.h as they are no longer needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a common header for SAM0 drivers to use to extract data from
devicetree. The initial set of macros are for get the MCLK A*MASK
register address for clock enablement and a set of macros for use with
DMA to get the channel and trigger source or 0xff if there is no dmas
property.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace DT_CPU_CLOCK_FREQUENCY with a PATH based reference to cpu@0
(DT_PATH(cpus, cpu_0)) and than getting the clock_frequency property:
DT_CPU_CLOCK_FREQUENCY -> DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
This lets us remove DT_CPU_CLOCK_FREQUENCY from dts_fixup.h
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In order for IO pins to work correctly after waking up from shutdown
mode, we need to unlatch them given they were automatically latched
when Power_shutdown() was invoked.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
The DT_I2S_* defines can be removed as the driver is now utilizing the
new dt macros that don't require these defines.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use new DT_INST macros throughout. This allows us to
also remove dts_fixup.h that are no longer used.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace macros of the form DT_CAVS_ICTL_x_IRQ with new dt form macro
DT_IRQN(DT_INST(x, intel_cavs_intc))
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace various drivers and soc code that use DT_CAVS_ICTL_BASE_ADDR
with DT_REG_ADDR(DT_NODELABEL(cavs0)).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked i2c_sam_twi driver to utilize new DT_INST macros as part of
this rework we also now get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked i2c_sam_twi driver to utilize new DT_INST macros as part of
this rework we also now get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use new DT_INST macros throughout. Removed per
instance Kconfig symbols and replaced with DT_NODELABEL references
where needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use new DT_INST macros throughout. We can remove
various defines from dts_fixup.h now as well.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use new DT_INST macros throughout. We remove the
aliases and use nodelabel instead in the soc_gpio.h to determine the
label for the specific gpio controller.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use new DT_INST macros throughout. This allows us to
also remove dts_fixup.h that are no longer used.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert from using dts_fixup.h based macros to DT_INST macro. This lets
us remove the dependancy on dts_fixup.h for this driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use DT_INST macros and remove related board per
instance Kconfig symbol usage. We also remove dts_fixup.h defines that
are no longer needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert from using dts_fixup.h based macros to DT_INST macro. This
lets us remove the dependancy on dts_fixup.h for this driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked usart_sam driver to utilize new DT_INST macros as part of
this rework we also now get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked uart_sam driver to utilize new DT_INST macros as part of this
rework we also now get pin ctrl/mux configuration information from the
device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a set of macros that will create a struct soc_gpio_pin
initialization based on data extracted from device tree. This should
allow replacing the static data in soc_pinmap.h with data coming from
devicetree instead.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert from using dts_fixup.h based macros to DT_INST macro. This lets
us remove the dependancy on dts_fixup.h for this driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We don't need to define DT_NUM_IRQ_PRIO_BITS or DT_NUM_MPU_REGIONS in
dts_fixup.h files anymore, so we can remove them.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
To remove the need to have DT_NUM_IRQ_PRIO_BITS defined in every
dts_fixup.h we can just handle the few variant cases in irq.h. This
allows us to remove DT_NUM_MPU_REGIONS from all the dts_fixup.h files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds the MCLK clock configuration symbol fix-up for the
GMAC peripheral.
The APB-agnostic clock configuration fix-up symbols map to the
SoC-specific APB, in order to accommodate different SoC variants with
the GMAC on different APBs.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Make use of DT_NODELABEL macros to get device instances
information to configure drivers I2C instances.
This allows to remove I2C related lines in fixup.h files
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Use compatible information to configure i2c stm32.
With this, driver version selection is done thanks to compatible
and it is not needed anymore to do this via Kconfig symbol
selection under soc/
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Replace CONFIG_ENTROPY_NAME with DT_CHOSEN_ZEPHYR_ENTROPY_LABEL. We now
set zephyr,entropy in the chosen node of the device tree to the entropy
device.
This allows us to remove CONFIG_ENTROPY_NAME from dts_fixup.h. Also
remove any other stale ENTROPY related defines in dts_fixup.h files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a helper macro that will go from a DT_DRV_INST number and return the
clock_ip_name value for that instance.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As prep for drivers being converted to utilize DT_INST and removal of
per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL
instead.
Also rename various node labels to match the SoC docs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
z_power_soc_deep_sleep() is called with interrupt locked already
so restoring BASEPRI is pointless here, as it would only allow
exceptions afterwards. The situation is complicated by the fact
that kernel/idle.c:idle() only locks interrupt without unlocking
which means the BASEBRI at entry of z_power_soc_deep_sleep() is
already set to allow exceptions only but not lower priority
interrupts like timer. So when, e.g. timer, interrupt fires,
the SoC would come out of deep sleep but the waking interrupts
are never delivered since they are masked, and idle() will try
to sleep again. And now it gets into a loop of going into deep
sleep briefly and waking up immediately and it goes on and on.
The solution is not to restore BASEPRI and simply leave it at
zero. This is a workaround as a proper fix would involve
invasion changes to the PM subsystem.
Also, _sys_pm_power_state_exit_post_ops() is not being called
when deep sleep is involved, so PRIMASK needs to be reset
after coming out of deep sleep.
Fixes#23274
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This moves enabling XTENSA_HAL to the SoC definitions.
As Xtensa SoCs are highly configurable, it is possible
that the generic Xtensa HAL provided in the tree is
not suitable. So only enable XTENSA_HAL only if
the generic version can be used.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Use the new devicetree API in a file which cross-checks dt reg base
addresses with values from the vendor HAL.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
When enabled, instead of erasing entire flash page at once, page will
be erased in defined time slices. Erasing single page stalls CPU
for significant time share (~80ms) and partial erase divides the
operation in to the shorter time periods, resuming CPU operation in
meantime and enabling better scheduling of time sensitive operations.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
To ease driver configuration, enable ENTROPY_STM32_RNG
only if device node matching driver compatible is enabled.
No more need to enable config symbol under soc/
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Convert stm32 entropy driver to configuration based on device tree.
Select HAS_DTS_ENTROPY symbols and configure CONFIG_ENTROPY_NAME
in fixup files.
Since rng node is not enabled (or available) on all boards, it could
happen that symbol ENTROPY_STM32_RNG is not enabled and hence
ENTROPY_HAS_DRIVER not selected which ends up with a symbol
ENTROPY_NAME defined throufg Kconfig selection. Thus, in fixup file,
CONFIG_ENTROPY_NAME is defined only if not already defined.
Additionally, update boards that used to configure entropy by default.
On these boards, enable rng device in device tree and remove Kconfig
related configuration (which should not be part of default
configuration).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Instead of using Kconfig options for setting the device name and IRQ
priority for the entropy_nrf5 driver, get these settings from the rng
node defined in DTS for a given SoC.
Provide also fixups for CONFIG_ENTROPY_NAME, until applications using
entropy drivers are converted to use DTS as well.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Convert driver to use DT_INST macros and remove related board per
instance Kconfig symbol usage.
Also update counter_basic_api test to use DT_INST and remove the
udoo_neo_full_m4.conf as its not longer needed since the per instance
Kconfig sybmols don't exist anymore.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use DT_INST macros and remove related board per
instance Kconfig symbol usage.
Additionally remove udoo_neo_full_m4.conf from gpio_basic_api test since
the Kconfig symbols don't need to be set anymore.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As prep for drivers being converted to utilize DT_INST and removal of
per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL
instead.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Make I2C and SPI drivers for nRF SoCs no longer dependent on Kconfig
options that enable instances (i.e. I2C_x and SPI_x). Now these drivers
enable hardware instances when corresponding nodes in devicetree are
enabled (have status "okay").
For I2C, SPI, and UART drivers, instead of using Kconfig dependencies
to prevent enabling of hardware instances that cannot be used together
(e.g. SPIM1 and TWIM1), a file that signals invalid configurations with
build assertions is added to compilation.
Also dependencies on HAS_HW_NRF_* options are removed from Kconfigs
of I2C, SPI, and UART drivers, as for hidden options that activate
proper type of driver such dependencies are not actually helpful.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Convert driver to utilize the new DT_INST macros completely and remove
associated Kconfig symbols that now come from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move to using DT_NODELABEL to get references to determine if specific
GPIO ports are enabled in the beetle SoC code.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Recent stm32 gpio driver changed removed the per port Kconfig symbols.
We had a type in flight issue in which the stm32l422xx got added and set
GPIO_STM32_PORTH. Just remove the Kconfig symbol as its not needed
anymore to fix build issues.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Use device node declaration instead.
Clean up GPIO_STM32_PORT* Kconfig symbols.
On some boards some gpio ports where disabled using Kconfig symbols.
Disable them now via device tree nodes in boards dts files.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add support for the STM32L422Xb SoC. Base stm32l422.dtsi on
stm32l412.dtsi to be able to add the crypto device later.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Add a YAML, DTS node and driver support to utilize data from devicetree
for register address and driver name.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a k_timeout_t type, and use it everywhere that kernel API
functions were accepting a millisecond timeout argument. Instead of
forcing milliseconds everywhere (which are often not integrally
representable as system ticks), do the conversion to ticks at the
point where the timeout is created. This avoids an extra unit
conversion in some application code, and allows us to express the
timeout in units other than milliseconds to achieve greater precision.
The existing K_MSEC() et. al. macros now return initializers for a
k_timeout_t.
The K_NO_WAIT and K_FOREVER constants have now become k_timeout_t
values, which means they cannot be operated on as integers.
Applications which have their own APIs that need to inspect these
vs. user-provided timeouts can now use a K_TIMEOUT_EQ() predicate to
test for equality.
Timer drivers, which receive an integer tick count in ther
z_clock_set_timeout() functions, now use the integer-valued
K_TICKS_FOREVER constant instead of K_FOREVER.
For the initial release, to preserve source compatibility, a
CONFIG_LEGACY_TIMEOUT_API kconfig is provided. When true, the
k_timeout_t will remain a compatible 32 bit value that will work with
any legacy Zephyr application.
Some subsystems present timeout (or timeout-like) values to their own
users as APIs that would re-use the kernel's own constants and
conventions. These will require some minor design work to adapt to
the new scheme (in most cases just using k_timeout_t directly in their
own API), and they have not been changed in this patch, instead
selecting CONFIG_LEGACY_TIMEOUT_API via kconfig. These subsystems
include: CAN Bus, the Microbit display driver, I2S, LoRa modem
drivers, the UART Async API, Video hardware drivers, the console
subsystem, and the network buffer abstraction.
k_sleep() now takes a k_timeout_t argument, with a k_msleep() variant
provided that works identically to the original API.
Most of the changes here are just type/configuration management and
documentation, but there are logic changes in mempool, where a loop
that used a timeout numerically has been reworked using a new
z_timeout_end_calc() predicate. Also in queue.c, a (when POLL was
enabled) a similar loop was needlessly used to try to retry the
k_poll() call after a spurious failure. But k_poll() does not fail
spuriously, so the loop was removed.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Kernel timeouts have always been a 32 bit integer despite the
existence of generation macros, and existing code has been
inconsistent about using them. Upcoming commits are going to make the
timeout arguments opaque, so fix things up to be rigorously correct.
Changes include:
+ Adding a K_TIMEOUT_EQ() macro for code that needs to compare timeout
values for equality (e.g. with K_FOREVER or K_NO_WAIT).
+ Adding a k_msleep() synonym for k_sleep() which can continue to take
integral arguments as k_sleep() moves away to timeout arguments.
+ Pervasively using the K_MSEC(), K_SECONDS(), et. al. macros to
generate timeout arguments.
+ Removing the usage of K_NO_WAIT as the final argument to
K_THREAD_DEFINE(). This is just a count of milliseconds and we need
to use a zero.
This patch include no logic changes and should not affect generated
code at all.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Replace all occurences of BUILD_ASSERT_MSG() with BUILD_ASSERT()
as a result of merging BUILD_ASSERT() and BUILD_ASSERT_MSG().
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
Fix typo where DT_REG_ADDR was used istead of DT_REG_SIZE in
linker script for i.MX RT socs and their ITCM and DTCM memories.
Signed-off-by: Arvid Rosén <arvid@softube.com>
This adds utility functions to irq.h in accordance with zephyr's
multi-level irq numbering schema. Functions that are added will
get the zephyr IRQs level and provide function to return the
interrupt number at a particular level.
Fixes issue #20338
Signed-off-by: Jaron Kelleher <jkelleher@fb.com>
Added properties to support the core interrupt controller on the NIOS2
cpu cores and enable that support for the NS16550 UART.
We rename some compatibles so that the cpu core compatibles is unique.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Indicate that the NXP Kinetis KE1xF SoC contains a Low Power Timer
(LPTMR) and default to enabling the corresponding driver if
CONFIG_COUNTER is enabled.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Added device tree nodes and associated headers for
defined uarts on the stm32g0 and stm32g07x 8x parts.
Tested with uart on stm32g071rb disco board with usart3 going to stlink.
Using shell.
Signed-off-by: Kieran Levin <ktl@frame.work>
This commit renames the `cortex_r` directory under the AArch32 to
`cortex_a_r`, in preparation for the AArch32 Cortex-A support.
The rationale for this renaming is that the Cortex-A and Cortex-R share
the same base design and the difference between them, other than the
MPU vs. MMU, is minimal.
Since most of the architecture port code and configurations will be
shared between the Cortex-A and Cortex-R architectures, it is
advantageous to have them together in the same directory.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This adds multi-processing support for Intel Apollo Lake ADSP.
Some of the start-up code is borrowed from ESP32.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The GCC 9.2 toolchain for intel_apl_adsp has builtin atomic
functions already so we can use that instead of the custom
one in arch. This allows the atomic function calls to be
inlined.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
EXCSAVE2 is used for level 2 exception save location.
Since we are using level 2 interrupts, use EXCSAVE7
instead as level 7 interrupts are not being used
by the SoC.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The DSP wall clock timer is a timer driven directly by
external oscillator and is external to the CPU core(s).
It provides a common and synchronized counter for all
CPU cores (which is useful for SMP), instead of
indepedently running local core timer (xtensa_timer).
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When power management is enabled, SYS_PM_STATE_LOCK is necessary
in order to prevent the power policy from automatically entering
certain sleep states.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
The shared irq support isn't needed in this driver. We just need to
deal with the fact that some SoCs have only a single interrupt line and
some have three interrupts. We can just ifdef that based on
DT_NUM_IRQS.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This was a simple missing macro, that prevented flash_shell to build
for stm32f4 based boards (which is weird, CI should have caught that
much earlier)
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Convert the driver to use DT_INST_ defines, update all dependent dts,
soc and board files.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
