ite: drivers/pinmux: modify pinmux driver

Modify the pinmux control method and add support the fun3
& fun4 alternation function.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
Tim Lin 2021-05-03 08:46:56 +08:00 committed by Anas Nashif
commit caa3328cc7
9 changed files with 412 additions and 78 deletions

View file

@ -13,20 +13,35 @@ static int it8xxx2_evb_pinmux_init(const struct device *dev)
{
ARG_UNUSED(dev);
const struct device *p = DEVICE_DT_GET(DT_NODELABEL(pinmux));
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmuxb), okay)
const struct device *portb = DEVICE_DT_GET(DT_NODELABEL(pinmuxb));
__ASSERT_NO_MSG(device_is_ready(p));
__ASSERT_NO_MSG(device_is_ready(portb));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmuxh), okay)
const struct device *porth = DEVICE_DT_GET(DT_NODELABEL(pinmuxh));
__ASSERT_NO_MSG(device_is_ready(porth));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
pinmux_pin_set(p, 0, IT8XXX2_PINMUX_IOF1);
pinmux_pin_set(p, 56, IT8XXX2_PINMUX_IOF1);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) */
/* SIN0 */
pinmux_pin_set(portb, 0, IT8XXX2_PINMUX_FUNC_3);
/* SOUT0 */
pinmux_pin_set(portb, 1, IT8XXX2_PINMUX_FUNC_3);
/* Pullup SIN0 to received data */
pinmux_pin_pullup(portb, 0, PINMUX_PULLUP_ENABLE);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
pinmux_pin_set(p, 3, IT8XXX2_PINMUX_IOF1);
pinmux_pin_set(p, 59, IT8XXX2_PINMUX_IOF1);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) */
/* SIN1 */
pinmux_pin_set(porth, 1, IT8XXX2_PINMUX_FUNC_4);
/* SOUT1 */
pinmux_pin_set(porth, 2, IT8XXX2_PINMUX_FUNC_4);
/* Pullup SIN1 to received data */
pinmux_pin_pullup(porth, 1, PINMUX_PULLUP_ENABLE);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) */
return 0;
}
SYS_INIT(it8xxx2_evb_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY);

View file

@ -16,11 +16,6 @@
#define DT_DRV_COMPAT ite_it8xxx2_gpio
#define GPCR_PORT_PIN_MODE_INPUT BIT(7)
#define GPCR_PORT_PIN_MODE_OUTPUT BIT(6)
#define GPCR_PORT_PIN_MODE_PULLUP BIT(2)
#define GPCR_PORT_PIN_MODE_PULLDOWN BIT(1)
/*
* Strcture gpio_ite_cfg is about the setting of gpio
* this config will be used at initial time

View file

@ -13,11 +13,22 @@
#include <drivers/pinmux.h>
#include <soc.h>
#define DT_DRV_COMPAT ite_it8xxx2_pinmux
#define PIN_REG_OFFSET 8
#define DT_DRV_COMPAT ite_it8xxx2_pinmux
#include <logging/log.h>
LOG_MODULE_REGISTER(pinmux_ite_it8xxx2, LOG_LEVEL_ERR);
struct pinmux_it8xxx2_config {
uintptr_t base;
/* gpio port control register (byte mapping to pin) */
uintptr_t reg_gpcr;
/* function 3 general control register */
uintptr_t func3_gcr[8];
/* function 4 general control register */
uintptr_t func4_gcr[8];
/* function 3 enable mask */
uint8_t func3_en_mask[8];
/* function 4 enable mask */
uint8_t func4_en_mask[8];
};
#define DEV_CFG(dev) \
@ -25,64 +36,140 @@ struct pinmux_it8xxx2_config {
(dev)->config)
static int pinmux_it8xxx2_set(const struct device *dev,
uint32_t pin, uint32_t func)
uint32_t pin, uint32_t func)
{
const struct pinmux_it8xxx2_config *config = DEV_CFG(dev);
uint32_t reg;
uint8_t val;
int g, i;
const struct pinmux_it8xxx2_config *pinmux_config = DEV_CFG(dev);
if (func > IT8XXX2_PINMUX_IOF1 || pin >= IT8XXX2_PINMUX_PINS) {
volatile uint8_t *reg_gpcr =
(uint8_t *)(pinmux_config->reg_gpcr + pin);
volatile uint8_t *reg_func3_gcr =
(uint8_t *)(pinmux_config->func3_gcr[pin]);
volatile uint8_t *reg_func4_gcr =
(uint8_t *)(pinmux_config->func4_gcr[pin]);
if (pin >= IT8XXX2_PINMUX_PINS) {
return -EINVAL;
}
g = pin / PIN_REG_OFFSET;
i = pin % PIN_REG_OFFSET;
reg = config->base + g;
val = sys_read8(reg);
if (func == IT8XXX2_PINMUX_IOF1) {
sys_write8((val | IT8XXX2_PINMUX_IOF1 << i), reg);
} else {
sys_write8((val & ~(IT8XXX2_PINMUX_IOF1 << i)), reg);
/* Common settings for alternate function. */
*reg_gpcr &= ~(GPCR_PORT_PIN_MODE_INPUT |
GPCR_PORT_PIN_MODE_OUTPUT);
switch (func) {
case IT8XXX2_PINMUX_FUNC_1:
/* Func1: Alternate function has been set above. */
break;
case IT8XXX2_PINMUX_FUNC_2:
/* Func2: WUI function: turn the pin into an input */
*reg_gpcr |= GPCR_PORT_PIN_MODE_INPUT;
break;
case IT8XXX2_PINMUX_FUNC_3:
/*
* Func3: In addition to the alternate setting above,
* Func3 also need to set the general control.
*/
*reg_func3_gcr |= pinmux_config->func3_en_mask[pin];
break;
case IT8XXX2_PINMUX_FUNC_4:
/*
* Func4: In addition to the alternate setting above,
* Func4 also need to set the general control.
*/
*reg_func4_gcr |= pinmux_config->func4_en_mask[pin];
break;
default:
LOG_ERR("This function is not supported");
return -EINVAL;
}
return 0;
}
static int pinmux_it8xxx2_get(const struct device *dev,
uint32_t pin, uint32_t *func)
uint32_t pin, uint32_t *func)
{
const struct pinmux_it8xxx2_config *config = DEV_CFG(dev);
uint32_t reg;
uint8_t val;
int g, i;
const struct pinmux_it8xxx2_config *pinmux_config = DEV_CFG(dev);
volatile uint8_t *reg_gpcr =
(uint8_t *)(pinmux_config->reg_gpcr + pin);
if (pin >= IT8XXX2_PINMUX_PINS || func == NULL) {
return -EINVAL;
}
g = pin / PIN_REG_OFFSET;
i = pin % PIN_REG_OFFSET;
reg = config->base + g;
val = sys_read8(reg);
*func = (val & (IT8XXX2_PINMUX_IOF1 << pin)) ?
IT8XXX2_PINMUX_IOF1 : IT8XXX2_PINMUX_IOF0;
*func = (*reg_gpcr & (GPCR_PORT_PIN_MODE_INPUT |
GPCR_PORT_PIN_MODE_OUTPUT)) == GPCR_PORT_PIN_MODE_INPUT ?
IT8XXX2_PINMUX_FUNC_2 : IT8XXX2_PINMUX_FUNC_1;
/* TODO: IT8XXX2_PINMUX_FUNC_3 & IT8XXX2_PINMUX_FUNC_4 */
return 0;
}
static int pinmux_it8xxx2_pullup(const struct device *dev,
uint32_t pin, uint8_t func)
uint32_t pin, uint8_t func)
{
return -ENOTSUP;
const struct pinmux_it8xxx2_config *pinmux_config = DEV_CFG(dev);
volatile uint8_t *reg_gpcr =
(uint8_t *)(pinmux_config->reg_gpcr + pin);
if (func == PINMUX_PULLUP_ENABLE) {
*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_PULLUP) &
~GPCR_PORT_PIN_MODE_PULLDOWN;
} else if (func == PINMUX_PULLUP_DISABLE) {
*reg_gpcr &= ~(GPCR_PORT_PIN_MODE_PULLUP |
GPCR_PORT_PIN_MODE_PULLDOWN);
} else {
return -EINVAL;
}
return 0;
}
static int pinmux_it8xxx2_input(const struct device *dev,
uint32_t pin, uint8_t func)
uint32_t pin, uint8_t func)
{
return -ENOTSUP;
const struct pinmux_it8xxx2_config *pinmux_config = DEV_CFG(dev);
volatile uint8_t *reg_gpcr =
(uint8_t *)(pinmux_config->reg_gpcr + pin);
*reg_gpcr &= ~(GPCR_PORT_PIN_MODE_INPUT |
GPCR_PORT_PIN_MODE_OUTPUT);
if (func == PINMUX_INPUT_ENABLED) {
*reg_gpcr |= GPCR_PORT_PIN_MODE_INPUT;
} else if (func == PINMUX_OUTPUT_ENABLED) {
*reg_gpcr |= GPCR_PORT_PIN_MODE_OUTPUT;
} else {
return -EINVAL;
}
return 0;
}
static int pinmux_it8xxx2_init(const struct device *dev)
{
ARG_UNUSED(dev);
/*
* The default value of LPCRSTEN is bit2:1 = 10b(GPD2) in GCR.
* If LPC reset is enabled on GPB7, we have to clear bit2:1
* to 00b.
*/
IT8XXX2_GPIO_GCR &= ~(BIT(1) | BIT(2));
/*
* TODO: If SMBUS3 swaps from H group to F group, we have to
* set SMB3PSEL = 1 in PMER3 register.
*/
/*
* TODO: If UART2 swaps from bit2:1 to bit6:5 in H group, we
* have to set UART1PSEL = 1 in UART1PMR register.
*/
return 0;
}
@ -93,11 +180,20 @@ static const struct pinmux_driver_api pinmux_it8xxx2_driver_api = {
.input = pinmux_it8xxx2_input,
};
static const struct pinmux_it8xxx2_config pinmux_it8xxx2_0_config = {
.base = DT_INST_REG_ADDR(0),
};
#define PINMUX_ITE_INIT(inst) \
static const struct pinmux_it8xxx2_config pinmux_it8xxx2_cfg_##inst = { \
.reg_gpcr = DT_INST_REG_ADDR(inst), \
.func3_gcr = DT_INST_PROP(inst, func3_gcr), \
.func3_en_mask = DT_INST_PROP(inst, func3_en_mask), \
.func4_gcr = DT_INST_PROP(inst, func4_gcr), \
.func4_en_mask = DT_INST_PROP(inst, func4_en_mask), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, \
&pinmux_it8xxx2_init, \
NULL, NULL, &pinmux_it8xxx2_cfg_##inst, \
PRE_KERNEL_1, \
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
&pinmux_it8xxx2_driver_api);
DEVICE_DT_INST_DEFINE(0, &pinmux_it8xxx2_init, NULL,
NULL, &pinmux_it8xxx2_0_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&pinmux_it8xxx2_driver_api);
DT_INST_FOREACH_STATUS_OKAY(PINMUX_ITE_INIT)

View file

@ -10,3 +10,19 @@ include: base.yaml
properties:
reg:
required: true
func3_gcr:
type: array
required: true
func3_en_mask:
type: array
required: true
func4_gcr:
type: array
required: true
func4_en_mask:
type: array
required: true

View file

@ -8,6 +8,7 @@
#include <mem.h>
#include <dt-bindings/interrupt-controller/ite-intc.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/pinctrl/it8xxx2-pinctrl.h>
/ {
#address-cells = <1>;
@ -42,9 +43,174 @@
write-block-size = <4>;
};
};
pinmux: pinmux@f016f0 {
pinmuxa: pinmux@f01610 {
compatible = "ite,it8xxx2-pinmux";
reg = <0x00f016f0 0x0010>;
reg = <0x00f01610 0x0008>;
label = "PINMUXA";
func3_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
0xf02032 0xf02032 0xf016f0 0xf016f0>;
func3_en_mask = <0 0 0 0
0x02 0x02 0x10 0x0C >;
func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
NO_FUNC NO_FUNC NO_FUNC NO_FUNC >;
func4_en_mask = <0 0 0 0
0 0 0 0 >;
};
pinmuxb: pinmux@f01618 {
compatible = "ite,it8xxx2-pinmux";
reg = <0x00f01618 0x0008>;
label = "PINMUXB";
func3_gcr = <0xf016f5 0xf016f5 NO_FUNC NO_FUNC
NO_FUNC NO_FUNC NO_FUNC 0xf01600>;
func3_en_mask = <0x01 0x02 0 0
0 0 0 0x02 >;
func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
NO_FUNC NO_FUNC NO_FUNC 0xf016f1>;
func4_en_mask = <0 0 0 0
0 0 0 0x40 >;
};
pinmuxc: pinmux@f01620 {
compatible = "ite,it8xxx2-pinmux";
reg = <0x00f01620 0x0008>;
label = "PINMUXC";
func3_gcr = <NO_FUNC NO_FUNC NO_FUNC 0xf016f0
NO_FUNC 0xf016f0 NO_FUNC 0xf016f3>;
func3_en_mask = <0 0 0 0x10
0 0x10 0 0x02 >;
func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
NO_FUNC NO_FUNC NO_FUNC 0xf016f6>;
func4_en_mask = <0 0 0 0
0 0 0 0x80 >;
};
pinmuxd: pinmux@f01628 {
compatible = "ite,it8xxx2-pinmux";
reg = <0x00f01628 0x0008>;
label = "PINMUXD";
func3_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
NO_FUNC 0xf016f0 NO_FUNC NO_FUNC>;
func3_en_mask = <0 0 0 0
0 0x02 0 0 >;
func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
func4_en_mask = <0 0 0 0
0 0 0 0 >;
};
pinmuxe: pinmux@f01630 {
compatible = "ite,it8xxx2-pinmux";
reg = <0x00f01630 0x0008>;
label = "PINMUXE";
func3_gcr = <0xf02032 NO_FUNC NO_FUNC NO_FUNC
NO_FUNC 0xf016f0 NO_FUNC 0xf02032>;
func3_en_mask = <0x01 0 0 0
0 0x08 0 0x01 >;
func4_gcr = <0xf016f3 NO_FUNC NO_FUNC NO_FUNC
NO_FUNC NO_FUNC NO_FUNC NO_FUNC >;
func4_en_mask = <0x01 0 0 0
0 0 0 0 >;
};
pinmuxf: pinmux@f01638 {
compatible = "ite,it8xxx2-pinmux";
reg = <0x00f01638 0x0008>;
label = "PINMUXF";
func3_gcr = <NO_FUNC NO_FUNC 0xf016f0 0xf016f0
NO_FUNC NO_FUNC 0xf016f1 0xf016f1>;
func3_en_mask = <0 0 0x02 0x02
0 0 0x10 0x10 >;
func4_gcr = <NO_FUNC NO_FUNC 0xf016f1 0xf016f1
NO_FUNC NO_FUNC NO_FUNC NO_FUNC >;
func4_en_mask = <0 0 0x20 0x20
0 0 0 0 >;
};
pinmuxg: pinmux@f01640 {
compatible = "ite,it8xxx2-pinmux";
reg = <0x00f01640 0x0008>;
label = "PINMUXG";
func3_gcr = <0xf016f0 0xf016f0 0xf016f0 NO_FUNC
NO_FUNC NO_FUNC 0xf016f0 NO_FUNC>;
func3_en_mask = <0x20 0x08 0x10 0
0 0 0x02 0 >;
func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
func4_en_mask = <0 0 0 0
0 0 0 0 >;
};
pinmuxh: pinmux@f01648 {
compatible = "ite,it8xxx2-pinmux";
reg = <0x00f01648 0x0008>;
label = "PINMUXH";
func3_gcr = <NO_FUNC 0xf016f1 0xf016f1 NO_FUNC
NO_FUNC 0xf016f5 0xf016f5 NO_FUNC>;
func3_en_mask = <0 0x20 0x20 0
0 0x04 0x08 0 >;
func4_gcr = <NO_FUNC 0xf016f5 0xf016f5 NO_FUNC
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
func4_en_mask = <0 0x04 0x08 0
0 0 0 0 >;
};
pinmuxi: pinmux@f01650 {
compatible = "ite,it8xxx2-pinmux";
reg = <0x00f01650 0x0008>;
label = "PINMUXI";
func3_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
NO_FUNC 0xf016f0 0xf016f0 0xf016f0>;
func3_en_mask = <0 0 0 0
0 0x08 0x08 0x08 >;
func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
NO_FUNC NO_FUNC NO_FUNC NO_FUNC >;
func4_en_mask = <0 0 0 0
0 0 0 0 >;
};
pinmuxj: pinmux@f01658 {
compatible = "ite,it8xxx2-pinmux";
reg = <0x00f01658 0x0008>;
label = "PINMUXJ";
func3_gcr = <0xf016f4 NO_FUNC 0xf016f4 0xf016f4
0xf016f0 0xf016f0 NO_FUNC NO_FUNC>;
func3_en_mask = <0x01 0 0x01 0x02
0x02 0x03 0 0 >;
func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
func4_en_mask = <0 0 0 0
0 0 0 0 >;
};
pinmuxk: pinmux@f01690 {
compatible = "ite,it8xxx2-pinmux";
reg = <0x00f01690 0x0008>;
label = "PINMUXK";
func3_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
func3_en_mask = <0 0 0 0
0 0 0 0 >;
func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
func4_en_mask = <0 0 0 0
0 0 0 0 >;
};
pinmuxl: pinmux@f01698 {
compatible = "ite,it8xxx2-pinmux";
reg = <0x00f01698 0x0008>;
label = "PINMUXL";
func3_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
func3_en_mask = <0 0 0 0
0 0 0 0 >;
func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
func4_en_mask = <0 0 0 0
0 0 0 0 >;
};
pinmuxm: pinmux@f016a0 {
compatible = "ite,it8xxx2-pinmux";
reg = <0x00f016a0 0x0008>;
label = "PINMUXM";
func3_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
func3_en_mask = <0 0 0 0
0 0 0 0 >;
func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
func4_en_mask = <0 0 0 0
0 0 0 0 >;
};
sram0: memory@80100000 {
compatible = "mmio-sram";

View file

@ -0,0 +1,11 @@
/*
* Copyright (c) 2021 ITE Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IT8XXX2_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IT8XXX2_PINCTRL_H_
#define NO_FUNC 0
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IT8XXX2_PINCTRL_H_ */

View file

@ -1,4 +1,4 @@
/*
/*
* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*/
@ -689,6 +689,11 @@
#define GPDMRJ ECREG(EC_REG_BASE_ADDR + 0x166A)
#define GPDMRM ECREG(EC_REG_BASE_ADDR + 0x166D)
#define GPCR_PORT_PIN_MODE_INPUT BIT(7)
#define GPCR_PORT_PIN_MODE_OUTPUT BIT(6)
#define GPCR_PORT_PIN_MODE_PULLUP BIT(2)
#define GPCR_PORT_PIN_MODE_PULLDOWN BIT(1)
/**
*
* (17XXh) PS/2 Interface Register
@ -1610,6 +1615,14 @@
#define CE_RNG ECREG(EC_REG_BASE_ADDR + 0x3C20)
/* --- GPIO --- */
#define IT8XXX2_GPIO_BASE 0x00F01600
#define IT8XXX2_GPIO2_BASE 0x00F03E00
#define IT8XXX2_GPIO_GCR ECREG(IT8XXX2_GPIO_BASE + 0x00)
#define IT8XXX2_GPIO_GRC1 ECREG(IT8XXX2_GPIO_BASE + 0xF0)
#define IT8XXX2_GPIO_GRC21 ECREG(IT8XXX2_GPIO_BASE + 0xE6)
/* Analog to Digital Converter (ADC) */
#define IT83XX_ADC_BASE 0x00f01900
@ -1676,6 +1689,16 @@
#define CGC_OFFSET_SMBB ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x08)
#define CGC_OFFSET_SMBA ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x04)
#define IT8XXX2_ECPM_AUTOCG ECREG(IT83XX_ECPM_BASE + 0x04)
#define IT8XXX2_ECPM_CGCTRL3R ECREG(IT83XX_ECPM_BASE + 0x05)
#define IT8XXX2_ECPM_PLLFREQR ECREG(IT83XX_ECPM_BASE + 0x06)
#define IT8XXX2_ECPM_PLLCSS ECREG(IT83XX_ECPM_BASE + 0x08)
#define IT8XXX2_ECPM_SCDCR0 ECREG(IT83XX_ECPM_BASE + 0x0c)
#define IT8XXX2_ECPM_SCDCR1 ECREG(IT83XX_ECPM_BASE + 0x0d)
#define IT8XXX2_ECPM_SCDCR2 ECREG(IT83XX_ECPM_BASE + 0x0e)
#define IT8XXX2_ECPM_SCDCR3 ECREG(IT83XX_ECPM_BASE + 0x0f)
#define IT8XXX2_ECPM_SCDCR4 ECREG(IT83XX_ECPM_BASE + 0x10)
/*
* The count number of the counter for 25 ms register.
* The 25 ms register is calculated by (count number *1.024 kHz).

View file

@ -15,28 +15,37 @@ static int ite_it8xxx2_init(const struct device *arg)
ARG_UNUSED(arg);
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
/* uart1 board init */
CGCTRL3R &= ~(BIT(2));
AUTOCG &= ~(BIT(6));
RSTDMMC |= BIT(3); /* Set EC side control */
RSTC4 = BIT(1); /* W-One to reset controller */
GPCRB0 = 0x00; /* tx pin init */
GPCRB1 = 0x00; /* rx pin init */
GPCRF3 = 0x00; /* rts pin init */
GPCRD5 = 0x00; /* cts pin init */
/* UART1 board init */
/* bit2: clocks to UART1 modules are not gated. */
IT8XXX2_ECPM_CGCTRL3R &= ~BIT(2);
IT8XXX2_ECPM_AUTOCG &= ~BIT(6);
/* bit3: UART1 belongs to the EC side. */
IT83XX_GCTRL_RSTDMMC |= BIT(3);
/* reset UART before config it */
IT83XX_GCTRL_RSTC4 = BIT(1);
/* switch UART1 on without hardware flow control */
IT8XXX2_GPIO_GRC1 |= BIT(0);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
/* uart2 board init */
GCR21 &= ~(BIT(0) | BIT(1)); /* setting voltage 3.3v */
CGCTRL3R &= ~(BIT(2));
AUTOCG &= ~(BIT(5));
RSTDMMC |= BIT(2); /* Set EC side control */
RSTC4 = BIT(2); /* W-One to reset controller */
GPCRH1 = 0x00; /* tx pin init */
GPCRH2 = 0x00; /* rx pin init */
GPCRE5 = 0x00; /* rts pin init */
GPCRI7 = 0x00; /* cts pin init */
/* UART2 board init */
/* setting voltage 3.3v */
IT8XXX2_GPIO_GRC21 &= ~(BIT(0) | BIT(1));
/* bit2: clocks to UART2 modules are not gated. */
IT8XXX2_ECPM_CGCTRL3R &= ~BIT(2);
IT8XXX2_ECPM_AUTOCG &= ~BIT(5);
/* bit3: UART2 belongs to the EC side. */
IT83XX_GCTRL_RSTDMMC |= BIT(2);
/* reset UART before config it */
IT83XX_GCTRL_RSTC4 = BIT(2);
/* switch UART2 on without hardware flow control */
IT8XXX2_GPIO_GRC1 |= BIT(2);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) */
return 0;
}

View file

@ -21,8 +21,11 @@
(*((volatile unsigned char *)(reg)))
/* PINMUX config */
#define IT8XXX2_PINMUX_IOF0 0x00
#define IT8XXX2_PINMUX_IOF1 0x01
#define IT8XXX2_PINMUX_PINS 128
#define IT8XXX2_PINMUX_FUNC_1 PINMUX_FUNC_A
#define IT8XXX2_PINMUX_FUNC_2 PINMUX_FUNC_B
#define IT8XXX2_PINMUX_FUNC_3 PINMUX_FUNC_C
#define IT8XXX2_PINMUX_FUNC_4 PINMUX_FUNC_D
#define IT8XXX2_PINMUX_PINS 8
#endif /* __RISCV_ITE_SOC_H_ */