driver: clock: npcx: add apb4 clock support for npcx9 series.
Add apb4 clock support for npcx9 and later series. Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
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3 changed files with 50 additions and 12 deletions
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@ -68,3 +68,23 @@ config CLOCK_NPCX_APB3_PRESCALER
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12.5MHz <= APB3_CLK <= 50MHz.
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- The frequency of APB3_CLK must be an integer division (including 1)
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of the frequency of the Core clock.
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APB3 prescaler, allowed values: From 1 to 10.
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config CLOCK_NPCX_APB4_PRESCALER
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int "APB4 prescaler"
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default 4
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range 1 10
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depends on SOC_SERIES_NPCX9
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help
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This sets the APB4 prescaler which changes the frequency of APB4_CLK.
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APB4_CLK frequency = OSC_CLK / APB4_PRE. The APB4 prescaler allowed
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value is from 1 to 10. Please notice only npcx9 and later series
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support this feature.
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The generated frequency of APB4_CLK should comply with the following
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requirements:
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- The frequency of APB4_CLK must be set to:
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8MHz <= APB4_CLK <= 100MHz.
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- The frequency of APB4_CLK must be an integer division (including 1)
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of the frequency of the Core clock.
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APB4 prescaler, allowed values: From 1 to 10.
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@ -79,6 +79,11 @@ static int npcx_clock_control_get_subsys_rate(const struct device *dev,
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case NPCX_CLOCK_BUS_APB3:
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*rate = NPCX_APB_CLOCK(3);
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break;
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#ifdef CONFIG_CLOCK_NPCX_APB4_PRESCALER
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case NPCX_CLOCK_BUS_APB4:
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*rate = NPCX_APB_CLOCK(4);
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break;
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#endif
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case NPCX_CLOCK_BUS_AHB6:
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*rate = CORE_CLK/(AHB6DIV_VAL + 1);
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break;
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@ -139,29 +144,34 @@ static struct clock_control_driver_api npcx_clock_control_api = {
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};
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/* valid clock frequency check */
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BUILD_ASSERT(CORE_CLK <= 100000000 &&
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CORE_CLK >= 4000000 &&
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BUILD_ASSERT(CORE_CLK <= MHZ(100) && CORE_CLK >= MHZ(4) &&
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OSC_CLK % CORE_CLK == 0 &&
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OSC_CLK / CORE_CLK <= 10,
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"Invalid CORE_CLK setting");
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BUILD_ASSERT(CORE_CLK / (FIUDIV_VAL + 1) <= 50000000 &&
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CORE_CLK / (FIUDIV_VAL + 1) >= 4000000,
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BUILD_ASSERT(CORE_CLK / (FIUDIV_VAL + 1) <= MHZ(50) &&
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CORE_CLK / (FIUDIV_VAL + 1) >= MHZ(4),
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"Invalid FIUCLK setting");
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BUILD_ASSERT(CORE_CLK / (AHB6DIV_VAL + 1) <= 50000000 &&
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CORE_CLK / (AHB6DIV_VAL + 1) >= 4000000,
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BUILD_ASSERT(CORE_CLK / (AHB6DIV_VAL + 1) <= MHZ(50) &&
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CORE_CLK / (AHB6DIV_VAL + 1) >= MHZ(4),
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"Invalid AHB6_CLK setting");
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BUILD_ASSERT(APBSRC_CLK / (APB1DIV_VAL + 1) <= 50000000 &&
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APBSRC_CLK / (APB1DIV_VAL + 1) >= 4000000 &&
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BUILD_ASSERT(APBSRC_CLK / (APB1DIV_VAL + 1) <= MHZ(50) &&
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APBSRC_CLK / (APB1DIV_VAL + 1) >= MHZ(4) &&
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(APB1DIV_VAL + 1) % (FPRED_VAL + 1) == 0,
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"Invalid APB1_CLK setting");
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BUILD_ASSERT(APBSRC_CLK / (APB2DIV_VAL + 1) <= 50000000 &&
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APBSRC_CLK / (APB2DIV_VAL + 1) >= 8000000 &&
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BUILD_ASSERT(APBSRC_CLK / (APB2DIV_VAL + 1) <= MHZ(50) &&
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APBSRC_CLK / (APB2DIV_VAL + 1) >= MHZ(8) &&
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(APB2DIV_VAL + 1) % (FPRED_VAL + 1) == 0,
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"Invalid APB2_CLK setting");
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BUILD_ASSERT(APBSRC_CLK / (APB3DIV_VAL + 1) <= 50000000 &&
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APBSRC_CLK / (APB3DIV_VAL + 1) >= 12500000 &&
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BUILD_ASSERT(APBSRC_CLK / (APB3DIV_VAL + 1) <= MHZ(50) &&
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APBSRC_CLK / (APB3DIV_VAL + 1) >= KHZ(12500) &&
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(APB3DIV_VAL + 1) % (FPRED_VAL + 1) == 0,
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"Invalid APB3_CLK setting");
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#ifdef CONFIG_CLOCK_NPCX_APB4_PRESCALER
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BUILD_ASSERT(APBSRC_CLK / (APB4DIV_VAL + 1) <= MHZ(100) &&
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APBSRC_CLK / (APB4DIV_VAL + 1) >= MHZ(8) &&
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(APB4DIV_VAL + 1) % (FPRED_VAL + 1) == 0,
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"Invalid APB4_CLK setting");
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#endif
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static int npcx_clock_control_init(const struct device *dev)
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{
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@ -194,7 +204,11 @@ static int npcx_clock_control_init(const struct device *dev)
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inst_cdcg->HFCGP = ((FPRED_VAL << 4) | AHB6DIV_VAL);
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inst_cdcg->HFCBCD = (FIUDIV_VAL << 4);
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inst_cdcg->HFCBCD1 = (APB1DIV_VAL | (APB2DIV_VAL << 4));
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#ifdef CONFIG_CLOCK_NPCX_APB4_PRESCALER
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inst_cdcg->HFCBCD2 = (APB3DIV_VAL | (APB4DIV_VAL << 4));
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#else
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inst_cdcg->HFCBCD2 = APB3DIV_VAL;
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#endif
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/*
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* Power-down (turn off clock) the modules initially for better
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@ -60,6 +60,10 @@ struct npcx_clk_cfg {
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#define APB2DIV_VAL (CONFIG_CLOCK_NPCX_APB2_PRESCALER - 1)
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/* APB3 clock divider, default value (APB3 clock = OSC_CLK/2) */
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#define APB3DIV_VAL (CONFIG_CLOCK_NPCX_APB3_PRESCALER - 1)
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/* APB4 clock divider, default value (APB4 clock = OSC_CLK/6) */
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#ifdef CONFIG_CLOCK_NPCX_APB4_PRESCALER
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#define APB4DIV_VAL (CONFIG_CLOCK_NPCX_APB4_PRESCALER - 1)
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#endif
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/* AHB6 clock */
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#if (CORE_CLK > 50000000)
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