soc: arm: gigadevice: add support for GD32F3X0 SoCs
Add support for GigaDevice GD32F3X0 series. Signed-off-by: HaiLong Yang <cameledyang@pm.me>
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9 changed files with 104 additions and 0 deletions
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@ -106,12 +106,19 @@ typedef uint32_t pinctrl_soc_pin_t;
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#ifdef CONFIG_PINCTRL_GD32_AF
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/** Maximum 2MHz */
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#define GD32_OSPEED_2MHZ 0U
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#ifdef CONFIG_SOC_SERIES_GD32F3X0
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/** Maximum 10MHz */
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#define GD32_OSPEED_10MHZ 1U
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/** Maximum 50MHz */
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#define GD32_OSPEED_50MHZ 3U
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#else
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/** Maximum 25MHz */
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#define GD32_OSPEED_25MHZ 1U
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/** Maximum 50MHz */
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#define GD32_OSPEED_50MHZ 2U
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/** Maximum 200MHz */
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#define GD32_OSPEED_200MHZ 3U
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#endif /* CONFIG_SOC_SERIES_GD32F3X0 */
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#else
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/** Maximum 10MHz */
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#define GD32_OSPEED_10MHZ 0U
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soc/arm/gigadevice/gd32f3x0/CMakeLists.txt
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soc/arm/gigadevice/gd32f3x0/CMakeLists.txt
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@ -0,0 +1,5 @@
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# Copyright (c) 2021 BrainCo Inc.
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(.)
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zephyr_sources(soc.c)
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soc/arm/gigadevice/gd32f3x0/Kconfig.defconfig.gd32f350
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soc/arm/gigadevice/gd32f3x0/Kconfig.defconfig.gd32f350
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@ -0,0 +1,11 @@
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# Copyright (c) 2021 BrainCo Inc.
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# SPDX-License-Identifier: Apache-2.0
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config SOC
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default "gd32f350"
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
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config NUM_IRQS
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default 68
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soc/arm/gigadevice/gd32f3x0/Kconfig.defconfig.series
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soc/arm/gigadevice/gd32f3x0/Kconfig.defconfig.series
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@ -0,0 +1,11 @@
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# Copyright (c) 2021 BrainCo Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_GD32F3X0
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source "soc/arm/gigadevice/gd32f3x0/Kconfig.defconfig.gd32*"
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config SOC_SERIES
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default "gd32f3x0"
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endif # SOC_SERIES_GD32F3X0
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soc/arm/gigadevice/gd32f3x0/Kconfig.series
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soc/arm/gigadevice/gd32f3x0/Kconfig.series
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@ -0,0 +1,12 @@
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# Copyright (c) 2021 BrainCo Inc.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_GD32F3X0
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bool "GigaDevice GD32F3X0 series Cortex-M4F MCU"
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select ARM
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select CPU_HAS_FPU
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select CPU_CORTEX_M4
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select SOC_FAMILY_GD32_ARM
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select GD32_HAS_AF_PINMUX
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help
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Enable support for GigaDevice GD32F3X0 MCU series
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soc/arm/gigadevice/gd32f3x0/Kconfig.soc
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soc/arm/gigadevice/gd32f3x0/Kconfig.soc
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@ -0,0 +1,10 @@
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# Copyright (c) 2021 BrainCo Inc.
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "GigaDevice GD32F3X0 MCU Selection"
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depends on SOC_SERIES_GD32F3X0
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config SOC_GD32F350
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bool "gd32f350"
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endchoice
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soc/arm/gigadevice/gd32f3x0/linker.ld
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soc/arm/gigadevice/gd32f3x0/linker.ld
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@ -0,0 +1,6 @@
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/*
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* Copyright (c) 2021 BrainCo Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>
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soc/arm/gigadevice/gd32f3x0/soc.c
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soc/arm/gigadevice/gd32f3x0/soc.c
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@ -0,0 +1,26 @@
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/*
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* Copyright (c) Copyright (c) 2021 BrainCo Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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static int gd32f3x0_init(const struct device *dev)
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{
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uint32_t key;
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ARG_UNUSED(dev);
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key = irq_lock();
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SystemInit();
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NMI_INIT();
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irq_unlock(key);
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return 0;
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}
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SYS_INIT(gd32f3x0_init, PRE_KERNEL_1, 0);
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soc/arm/gigadevice/gd32f3x0/soc.h
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soc/arm/gigadevice/gd32f3x0/soc.h
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@ -0,0 +1,16 @@
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/*
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* Copyright (c) 2021 BrainCo Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC_ARM_GIGADEVICE_GD32F3X0_SOC_H_
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#define _SOC_ARM_GIGADEVICE_GD32F3X0_SOC_H_
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#ifndef _ASMLANGUAGE
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#include <devicetree.h>
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#include <gd32f3x0.h>
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#endif /* _ASMLANGUAGE */
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#endif /* _SOC_ARM_GIGADEVICE_GD32F3X0_SOC_H_ */
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