soc: arm: gigadevice: add support for GD32F3X0 SoCs

Add support for GigaDevice GD32F3X0 series.

Signed-off-by: HaiLong Yang <cameledyang@pm.me>
This commit is contained in:
HaiLong Yang 2021-11-10 11:13:50 +08:00 committed by Christopher Friedt
commit b863420013
9 changed files with 104 additions and 0 deletions

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@ -106,12 +106,19 @@ typedef uint32_t pinctrl_soc_pin_t;
#ifdef CONFIG_PINCTRL_GD32_AF
/** Maximum 2MHz */
#define GD32_OSPEED_2MHZ 0U
#ifdef CONFIG_SOC_SERIES_GD32F3X0
/** Maximum 10MHz */
#define GD32_OSPEED_10MHZ 1U
/** Maximum 50MHz */
#define GD32_OSPEED_50MHZ 3U
#else
/** Maximum 25MHz */
#define GD32_OSPEED_25MHZ 1U
/** Maximum 50MHz */
#define GD32_OSPEED_50MHZ 2U
/** Maximum 200MHz */
#define GD32_OSPEED_200MHZ 3U
#endif /* CONFIG_SOC_SERIES_GD32F3X0 */
#else
/** Maximum 10MHz */
#define GD32_OSPEED_10MHZ 0U

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@ -0,0 +1,5 @@
# Copyright (c) 2021 BrainCo Inc.
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)
zephyr_sources(soc.c)

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@ -0,0 +1,11 @@
# Copyright (c) 2021 BrainCo Inc.
# SPDX-License-Identifier: Apache-2.0
config SOC
default "gd32f350"
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config NUM_IRQS
default 68

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@ -0,0 +1,11 @@
# Copyright (c) 2021 BrainCo Inc.
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_GD32F3X0
source "soc/arm/gigadevice/gd32f3x0/Kconfig.defconfig.gd32*"
config SOC_SERIES
default "gd32f3x0"
endif # SOC_SERIES_GD32F3X0

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@ -0,0 +1,12 @@
# Copyright (c) 2021 BrainCo Inc.
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_GD32F3X0
bool "GigaDevice GD32F3X0 series Cortex-M4F MCU"
select ARM
select CPU_HAS_FPU
select CPU_CORTEX_M4
select SOC_FAMILY_GD32_ARM
select GD32_HAS_AF_PINMUX
help
Enable support for GigaDevice GD32F3X0 MCU series

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@ -0,0 +1,10 @@
# Copyright (c) 2021 BrainCo Inc.
# SPDX-License-Identifier: Apache-2.0
choice
prompt "GigaDevice GD32F3X0 MCU Selection"
depends on SOC_SERIES_GD32F3X0
config SOC_GD32F350
bool "gd32f350"
endchoice

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@ -0,0 +1,6 @@
/*
* Copyright (c) 2021 BrainCo Inc.
* SPDX-License-Identifier: Apache-2.0
*/
#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>

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@ -0,0 +1,26 @@
/*
* Copyright (c) Copyright (c) 2021 BrainCo Inc.
* SPDX-License-Identifier: Apache-2.0
*/
#include <device.h>
#include <init.h>
#include <soc.h>
static int gd32f3x0_init(const struct device *dev)
{
uint32_t key;
ARG_UNUSED(dev);
key = irq_lock();
SystemInit();
NMI_INIT();
irq_unlock(key);
return 0;
}
SYS_INIT(gd32f3x0_init, PRE_KERNEL_1, 0);

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@ -0,0 +1,16 @@
/*
* Copyright (c) 2021 BrainCo Inc.
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_ARM_GIGADEVICE_GD32F3X0_SOC_H_
#define _SOC_ARM_GIGADEVICE_GD32F3X0_SOC_H_
#ifndef _ASMLANGUAGE
#include <devicetree.h>
#include <gd32f3x0.h>
#endif /* _ASMLANGUAGE */
#endif /* _SOC_ARM_GIGADEVICE_GD32F3X0_SOC_H_ */