arch/riscv: Add IPI support
Use CLINT to send interrupts to another CPU. SMP support is kinda incomplete without it. This patch only enables it for riscv-privilege platforms - specifically, "virt" one. Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
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3 changed files with 59 additions and 0 deletions
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@ -109,6 +109,7 @@ config RISCV
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select ARCH_HAS_THREAD_LOCAL_STORAGE
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select USE_SWITCH
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select USE_SWITCH_SUPPORTED
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select SCHED_IPI_SUPPORTED if SMP
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imply XIP
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help
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RISCV architecture
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@ -4,7 +4,9 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <init.h>
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#include <kernel.h>
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#include <ksched.h>
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volatile struct {
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arch_cpustart_t fn;
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@ -35,6 +37,61 @@ void z_riscv_secondary_cpu_init(int cpu_num)
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#endif
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#ifdef CONFIG_PMP_STACK_GUARD
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z_riscv_configure_interrupt_stack_guard();
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#endif
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#ifdef CONFIG_SMP
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irq_enable(RISCV_MACHINE_SOFT_IRQ);
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#endif
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riscv_cpu_init[cpu_num].fn(riscv_cpu_init[cpu_num].arg);
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}
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#ifdef CONFIG_SMP
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static uintptr_t *get_hart_msip(int hart_id)
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{
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#ifdef CONFIG_64BIT
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return (uintptr_t *)(uint64_t)(RISCV_MSIP_BASE + (hart_id * 4));
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#else
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return (uintptr_t *)(RISCV_MSIP_BASE + (hart_id * 4));
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#endif
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}
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void arch_sched_ipi(void)
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{
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unsigned int key;
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uint32_t i;
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uint8_t id;
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key = arch_irq_lock();
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id = _current_cpu->id;
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for (i = 0U; i < CONFIG_MP_NUM_CPUS; i++) {
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if (i != id) {
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volatile uint32_t *r = (uint32_t *)get_hart_msip(i);
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*r = 1U;
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}
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}
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arch_irq_unlock(key);
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}
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static void sched_ipi_handler(const void *unused)
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{
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ARG_UNUSED(unused);
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volatile uint32_t *r = (uint32_t *)get_hart_msip(_current_cpu->id);
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*r = 0U;
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z_sched_ipi();
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}
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static int riscv_smp_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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IRQ_CONNECT(RISCV_MACHINE_SOFT_IRQ, 0, sched_ipi_handler, NULL, 0);
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irq_enable(RISCV_MACHINE_SOFT_IRQ);
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return 0;
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}
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SYS_INIT(riscv_smp_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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#endif /* CONFIG_SMP */
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@ -12,5 +12,6 @@
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#define SIFIVE_SYSCON_TEST 0x00100000
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#define RISCV_MTIME_BASE 0x0200BFF8
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#define RISCV_MTIMECMP_BASE 0x02004000
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#define RISCV_MSIP_BASE 0x02000000
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#endif
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