soc: riscv: privilege: add neorv32 processor suppport
Add support for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
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8
dts/bindings/cpu/neorv32-cpu.yaml
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dts/bindings/cpu/neorv32-cpu.yaml
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# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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description: NEORV32 RISC-V CPU
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compatible: "neorv32-cpu"
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include: cpu.yaml
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67
dts/riscv/neorv32.dtsi
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67
dts/riscv/neorv32.dtsi
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/*
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* Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <skeleton.dtsi>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "neorv32-cpu";
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reg = <0>;
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device_type = "cpu";
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intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#address-cells = <1>;
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#interrupt-cells = <1>;
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firq: firq {
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interrupt-map-mask = <0x0 0xffffffff>;
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interrupt-map = <
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0 0 &intc 0 16
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0 1 &intc 0 17
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0 2 &intc 0 18
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0 3 &intc 0 19
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0 4 &intc 0 20
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0 5 &intc 0 21
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0 6 &intc 0 22
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0 7 &intc 0 23
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0 8 &intc 0 24
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0 9 &intc 0 25
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0 10 &intc 0 26
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0 11 &intc 0 27
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0 12 &intc 0 28
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0 13 &intc 0 29
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0 14 &intc 0 30
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0 15 &intc 0 31
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>;
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#interrupt-cells = <1>;
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};
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};
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};
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&firq>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sysinfo: syscon@ffffffe0 {
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compatible = "neorv-sysinfo", "syscon";
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status = "okay";
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reg = <0xffffffe0 32>;
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label = "SYSINFO";
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};
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};
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};
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8
soc/riscv/riscv-privilege/neorv32/CMakeLists.txt
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soc/riscv/riscv-privilege/neorv32/CMakeLists.txt
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# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(
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reset.S
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soc_irq.S
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soc.c
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)
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24
soc/riscv/riscv-privilege/neorv32/Kconfig.defconfig.series
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soc/riscv/riscv-privilege/neorv32/Kconfig.defconfig.series
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# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_NEORV32
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config SOC_SERIES
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default "neorv32"
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if RISCV_MACHINE_TIMER
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config NUM_IRQS
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default 32
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config RISCV_HAS_CPU_IDLE
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default y
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config RISCV_GP
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default y
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config SYSCON
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default y
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endif # SOC_SERIES_NEORV32
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21
soc/riscv/riscv-privilege/neorv32/Kconfig.series
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soc/riscv/riscv-privilege/neorv32/Kconfig.series
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# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_NEORV32
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bool "NEORV32 Processor"
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select RISCV
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select SOC_FAMILY_RISCV_PRIVILEGE
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help
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Enable support for the NEORV32 Processor (SoC).
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The NEORV32 CPU implementation must have the following RISC-V ISA
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extensions enabled in order to support Zephyr:
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- M (Integer Multiplication and Division)
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- Zicsr (Control and Status Register (CSR) Instructions)
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The following NEORV32 CPU ISA extensions are not currently supported
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by Zephyr and can safely be disabled:
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- A (Atomic Instructions)
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- E (Embedded, only 16 integer registers)
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- Zbb (Basic Bit Manipulation)
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- Zfinx (Floating Point in Integer Registers)
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32
soc/riscv/riscv-privilege/neorv32/Kconfig.soc
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soc/riscv/riscv-privilege/neorv32/Kconfig.soc
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# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "NEORV32 Version"
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depends on SOC_SERIES_NEORV32
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config SOC_NEORV32_V1_6_1
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bool "v1.6.1"
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# NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO
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select ATOMIC_OPERATIONS_C
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endchoice
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if SOC_SERIES_NEORV32
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config SOC_NEORV32_VERSION
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hex
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default 0x01060100 if SOC_NEORV32_V1_6_1
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help
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The targeted NEORV32 version as BCD-coded number. The format is
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identical to that of the NEORV32 Machine implementation ID (mimpid)
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register.
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config SOC_NEORV32_ISA_C
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bool "RISC-V ISA Extension \"C\""
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select COMPRESSED_ISA
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help
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Enable this if the NEORV32 CPU implementation supports the RISC-V ISA
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"C" extension (Compressed Instructions).
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endif # SOC_SERIES_NEORV32
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23
soc/riscv/riscv-privilege/neorv32/linker.ld
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soc/riscv/riscv-privilege/neorv32/linker.ld
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/*
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* Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <linker/linker-tool.h>
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MEMORY
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{
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IO (rw) : ORIGIN = 0xFFFFFE00, LENGTH = 512
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}
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SECTIONS
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{
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SECTION_PROLOGUE(io, (NOLOAD),)
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{
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PROVIDE(__io_start = ORIGIN(IO));
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PROVIDE(__io_end = ORIGIN(IO) + LENGTH(IO));
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} GROUP_LINK_IN(IO)
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}
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#include <arch/riscv/common/linker.ld>
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73
soc/riscv/riscv-privilege/neorv32/reset.S
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soc/riscv/riscv-privilege/neorv32/reset.S
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/*
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* Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <toolchain.h>
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/* exports */
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GTEXT(__reset)
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/* imports */
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GTEXT(__initialize)
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SECTION_FUNC(reset, __reset)
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/* Zerorize zero register */
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lui x0, 0
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/* Disable insterrupts */
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csrw mstatus, x0
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csrw mie, x0
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#ifdef CONFIG_USERSPACE
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/* Disable counter access outside M-mode */
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csrw mcounteren, x0
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#endif /* CONFIG_USERSPACE */
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/* Allow mcycle and minstret counters to increment */
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li x11, ~5
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csrw mcountinhibit, x11
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/* Zerorize counters */
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csrw mcycle, x0
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csrw mcycleh, x0
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csrw minstret, x0
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csrw minstreth, x0
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/*
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* Simplify dummy machine trap code by not having to decode
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* instruction width.
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*/
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.option push
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.option norvc
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/*
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* Temporarily setup a dummy machine trap vector to catch (and ignore)
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* Store Access faults due to unimplemented peripherals.
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*/
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csrr x6, mtvec
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la x7, __dummy_trap_handler
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csrw mtvec, x7
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/* Attempt to zerorize all IO peripheral registers */
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la x8, __io_start
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la x9, __io_end
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1: sw x0, 0(x8)
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addi x8, x8, 4
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bne x8, x9, 1b
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/* Restore previous machine trap vector */
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csrw mtvec, x6
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.option pop
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/* Jump to __initialize */
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call __initialize
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.balign 4
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SECTION_FUNC(reset, __dummy_trap_handler)
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csrr x5, mepc
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addi x5, x5, 4
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csrw mepc, x5
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mret
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17
soc/riscv/riscv-privilege/neorv32/soc.c
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soc/riscv/riscv-privilege/neorv32/soc.c
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/*
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* Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <irq.h>
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#include <soc.h>
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#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
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void soc_interrupt_init(void)
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{
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(void)irq_lock();
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__asm__ volatile ("csrwi mie, 0\n");
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}
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#endif
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63
soc/riscv/riscv-privilege/neorv32/soc.h
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soc/riscv/riscv-privilege/neorv32/soc.h
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/*
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* Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef RISCV_NEORV32_SOC_H
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#define RISCV_NEORV32_SOC_H
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#include <soc_common.h>
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#include <devicetree.h>
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/* Machine System Timer (MTIME) registers */
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#define RISCV_MTIME_BASE 0xffffff90U
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#define RISCV_MTIMECMP_BASE 0xffffff98U
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/* System information (SYSINFO) register offsets */
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#define NEORV32_SYSINFO_CLK 0x00U
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#define NEORV32_SYSINFO_CPU 0x04U
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#define NEORV32_SYSINFO_FEATURES 0x08U
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#define NEORV32_SYSINFO_CACHE 0x0cU
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#define NEORV32_SYSINFO_ISPACE_BASE 0xf0U
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#define NEORV32_SYSINFO_IMEM_SIZE 0xf4U
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#define NEORV32_SYSINFO_DSPACE_BASE 0xf8U
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#define NEORV32_SYSINFO_DMEM_SIZE 0xfcU
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/* System information (SYSINFO) CPU register bits */
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#define NEORV32_SYSINFO_CPU_ZICSR BIT(0)
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#define NEORV32_SYSINFO_CPU_ZIFENCEI BIT(1)
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#define NEORV32_SYSINFO_CPU_ZMMUL BIT(2)
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#define NEORV32_SYSINFO_CPU_ZBB BIT(3)
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#define NEORV32_SYSINFO_CPU_ZFINX BIT(5)
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#define NEORV32_SYSINFO_CPU_ZXSCNT BIT(6)
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#define NEORV32_SYSINFO_CPU_ZXNOCNT BIT(7)
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#define NEORV32_SYSINFO_CPU_PMP BIT(8)
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#define NEORV32_SYSINFO_CPU_HPM BIT(9)
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#define NEORV32_SYSINFO_CPU_DEBUGMODE BIT(10)
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#define NEORV32_SYSINFO_CPU_FASTMUL BIT(30)
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#define NEORV32_SYSINFO_CPU_FASTSHIFT BIT(31)
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/* System information (SYSINFO) FEATURES register bits */
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#define NEORV32_SYSINFO_FEATURES_BOOTLOADER BIT(0)
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#define NEORV32_SYSINFO_FEATURES_MEM_EXT BIT(1)
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#define NEORV32_SYSINFO_FEATURES_MEM_INT_IMEM BIT(2)
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#define NEORV32_SYSINFO_FEATURES_MEM_INT_DMEM BIT(3)
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#define NEORV32_SYSINFO_FEATURES_MEM_EXT_ENDIAN BIT(4)
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#define NEORV32_SYSINFO_FEATURES_ICACHE BIT(5)
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#define NEORV32_SYSINFO_FEATURES_OCD BIT(14)
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#define NEORV32_SYSINFO_FEATURES_HW_RESET BIT(15)
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#define NEORV32_SYSINFO_FEATURES_IO_GPIO BIT(16)
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#define NEORV32_SYSINFO_FEATURES_IO_MTIME BIT(17)
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#define NEORV32_SYSINFO_FEATURES_IO_UART0 BIT(18)
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#define NEORV32_SYSINFO_FEATURES_IO_SPI BIT(19)
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#define NEORV32_SYSINFO_FEATURES_IO_TWI BIT(20)
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#define NEORV32_SYSINFO_FEATURES_IO_PWM BIT(21)
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#define NEORV32_SYSINFO_FEATURES_IO_WDT BIT(22)
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#define NEORV32_SYSINFO_FEATURES_IO_CFS BIT(23)
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#define NEORV32_SYSINFO_FEATURES_IO_TRNG BIT(24)
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#define NEORV32_SYSINFO_FEATURES_IO_SLINK BIT(25)
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#define NEORV32_SYSINFO_FEATURES_IO_UART1 BIT(26)
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#define NEORV32_SYSINFO_FEATURES_IO_NEOLED BIT(27)
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#endif /* RISCV_NEORV32_SOC_H */
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28
soc/riscv/riscv-privilege/neorv32/soc_irq.S
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soc/riscv/riscv-privilege/neorv32/soc_irq.S
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/*
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* Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <toolchain.h>
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GTEXT(__soc_handle_irq)
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/*
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* SOC-specific function to handle pending IRQ number generating the interrupt.
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* Exception number is given as parameter via register a0.
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*/
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SECTION_FUNC(exception.other, __soc_handle_irq)
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/*
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* The the MIP CSR on the NEORV32 is read-only and can thus not be used for
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* clearing a pending IRQ. Instead we disable the IRQ in the MIE CSR and
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* re-enable it (if it was enabled when clearing).
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*/
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li t1, 1
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sll t0, t1, a0
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csrrc t2, mie, t0
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and t1, t2, t0
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csrrs t2, mie, t1
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/* Return */
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jalr x0, ra
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