arm: mps3_an547: Add SoC support for the AN547 on MPS3

The AN547 is a Soft Macro Model implementation of the SSE-300 subsystem
with Ethos-U55 and Cortex-M55 components targeting the MPS3 board.

The SoC support is based on the AN521 MPS2+ support that already exists
in Zephyr.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2021-02-13 14:42:46 -06:00 committed by Kumar Gala
commit 52d15d21bc
9 changed files with 151 additions and 0 deletions

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description: GPIO controller on ARM MPS3 FPGA
compatible: "arm,mps3-fpgaio-gpio"
include: [gpio-controller.yaml, base.yaml]
properties:
reg:
required: true
ngpios:
required: true
"#gpio-cells":
const: 1
gpio-cells:
- pin

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# Copyright (c) 2021 Linaro Limited
# SPDX-License-Identifier: Apache-2.0
zephyr_sources(
soc.c
)

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# Copyright (c) 2018-2021 Linaro Limited
# SPDX-License-Identifier: Apache-2.0
if SOC_MPS3_AN547
config SOC
default "mps3_an547"
config NUM_IRQS
default 128
endif

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# Copyright (c) 2021 Linaro Limited
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_MPS3
config SOC_SERIES
default "mps3"
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 25000000
source "soc/arm/arm/mps3/Kconfig.defconfig.mps3*"
endif # SOC_SERIES_MPS3

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# Copyright (c) 2021 Linaro Limited
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_MPS3
bool "Arm MPS3 MCU Series"
select ARM
select SOC_FAMILY_ARM
select GPIO_MMIO32 if GPIO
help
Enable support for ARM MPS3 MCU Series

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# Copyright (c) 2017-2021 Linaro Limited
# SPDX-License-Identifier: Apache-2.0
choice
prompt "Arm MPS3 SoCs"
depends on SOC_SERIES_MPS3
config SOC_MPS3_AN547
bool "Arm Cortex-M55 SSE-300 on MPS3 (AN547)"
select CPU_CORTEX_M55
select CPU_HAS_ARM_SAU
select CPU_HAS_ARM_MPU
endchoice

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/* linker.ld - Linker command/script file */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>

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soc/arm/arm/mps3/soc.c Normal file
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/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arch/cpu.h>
#include <drivers/gpio/gpio_mmio32.h>
#include <init.h>
#include <soc.h>
#include <linker/linker-defs.h>
/* Setup GPIO drivers for accessing FPGAIO registers */
#define FPGAIO_NODE(n) DT_INST(n, arm_mps3_fpgaio_gpio)
#define FPGAIO_INIT(n) \
GPIO_MMIO32_INIT(fpgaio_##n, DT_LABEL(FPGAIO_NODE(n)), \
DT_REG_ADDR(FPGAIO_NODE(n)), \
BIT_MASK(DT_PROP(FPGAIO_NODE(n), ngpios)))
/* We expect there to be 3 arm,mps3-fpgaio-gpio devices:
* led0, button, and misc
*/
FPGAIO_INIT(0);
FPGAIO_INIT(1);
FPGAIO_INIT(2);
/**
* @brief Perform basic hardware initialization at boot.
*
* @return 0
*/
static int arm_mps3_init(const struct device *arg)
{
ARG_UNUSED(arg);
/*
* Install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
return 0;
}
SYS_INIT(arm_mps3_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

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soc/arm/arm/mps3/soc.h Normal file
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/*
* Copyright (c) 2017-2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_H_
#define _SOC_H_
#define __MPU_PRESENT 1
#if defined(CONFIG_SOC_MPS3_AN547)
#define __SAUREGION_PRESENT 1U /* SAU regions present */
#define __FPU_PRESENT CONFIG_CPU_HAS_FPU
#define __DSP_PRESENT 1U /* DSP extension present */
#define __MVE_PRESENT 1U /* MVE extensions present */
#define __MVE_FP 1U /* MVE floating point present */
#endif
#include <devicetree.h>
#endif /* _SOC_H_ */