soc: x86: add Lakemont SoC

This adds a very basic SoC configuration for Intel Lakemont SoC.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2021-02-08 14:25:47 -08:00 committed by Anas Nashif
commit 78837c769a
8 changed files with 123 additions and 0 deletions

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@ -48,6 +48,19 @@ config CPU_APOLLO_LAKE
help
This option signifies the use of a CPU from the Apollo Lake family.
config CPU_LAKEMONT
bool
select CPU_HAS_FPU
select ARCH_HAS_STACK_PROTECTION if X86_MMU
select ARCH_HAS_USERSPACE if X86_MMU
select X86_CPU_HAS_MMX
select X86_CPU_HAS_SSE
select X86_CPU_HAS_SSE2
select X86_CPU_HAS_SSE3
select X86_CPU_HAS_SSSE3
help
This option signifies the use of a CPU from the Lakemont family.
#
# Configuration common to both IA32 and Intel64 sub-architectures.
#

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@ -0,0 +1,8 @@
# Copyright (c) 2021 Intel Corp.
# SPDX-License-Identifier: Apache-2.0
description: Intel Lakemont CPU
compatible: "intel,lakemont"
include: cpu.yaml

42
dts/x86/lakemont.dtsi Normal file
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@ -0,0 +1,42 @@
/*
* Copyright (c) 2021 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/intel-ioapic.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "intel,lakemont";
d-cache-line-size = <64>;
reg = <0>;
};
};
intc: ioapic@fec00000 {
compatible = "intel,ioapic";
reg = <0xfec00000 0x1000>;
interrupt-controller;
#interrupt-cells = <3>;
};
/*
* Platforms with Lakemont SoC can have different hardware
* configurations. So RAM and peripherals need to be
* defined in the board configuration's DTS.
*/
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
};
};

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@ -0,0 +1,5 @@
# Copyright (c) 2021 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
zephyr_cc_option(-march=pentium)

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@ -0,0 +1,23 @@
# Copyright (c) 2021 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
if SOC_LAKEMONT
config SOC
default "lakemont"
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768
# Can be enabled once UART is defined in board
# configuration.
config X86_VERY_EARLY_CONSOLE
default n
# Target platforms are usually not PC-compatible
# (e.g. without BIOS, ACPI, etc.).
config X86_PC_COMPATIBLE
default n
endif

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@ -0,0 +1,14 @@
# Copyright (c) 2021 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
config SOC_LAKEMONT
bool "Intel Lakemont SoC"
select X86
select CPU_LAKEMONT
select X86_MMU if FPU
select X86_SSE if FPU
select X86_SSE2 if FPU
select X86_SSE3 if FPU
select X86_SSSE3 if FPU
select ARCH_HAS_USERSPACE

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@ -0,0 +1,8 @@
/*
* Copyright (c) 2011-2014, Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arch/x86/memory.ld>
#include <arch/x86/ia32/linker.ld>

10
soc/x86/lakemont/soc.h Normal file
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@ -0,0 +1,10 @@
/*
* Copyright (c) 2021 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __SOC_H_
#define __SOC_H_
#endif /* __SOC_H_ */