soc: x86: add Lakemont SoC
This adds a very basic SoC configuration for Intel Lakemont SoC. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
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@ -48,6 +48,19 @@ config CPU_APOLLO_LAKE
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help
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This option signifies the use of a CPU from the Apollo Lake family.
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config CPU_LAKEMONT
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bool
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select CPU_HAS_FPU
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select ARCH_HAS_STACK_PROTECTION if X86_MMU
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select ARCH_HAS_USERSPACE if X86_MMU
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select X86_CPU_HAS_MMX
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select X86_CPU_HAS_SSE
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select X86_CPU_HAS_SSE2
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select X86_CPU_HAS_SSE3
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select X86_CPU_HAS_SSSE3
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help
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This option signifies the use of a CPU from the Lakemont family.
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#
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# Configuration common to both IA32 and Intel64 sub-architectures.
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#
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8
dts/bindings/cpu/intel,lakemont.yml
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dts/bindings/cpu/intel,lakemont.yml
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# Copyright (c) 2021 Intel Corp.
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# SPDX-License-Identifier: Apache-2.0
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description: Intel Lakemont CPU
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compatible: "intel,lakemont"
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include: cpu.yaml
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dts/x86/lakemont.dtsi
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dts/x86/lakemont.dtsi
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@ -0,0 +1,42 @@
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/*
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* Copyright (c) 2021 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/intel-ioapic.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "intel,lakemont";
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d-cache-line-size = <64>;
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reg = <0>;
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};
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};
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intc: ioapic@fec00000 {
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compatible = "intel,ioapic";
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reg = <0xfec00000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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/*
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* Platforms with Lakemont SoC can have different hardware
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* configurations. So RAM and peripherals need to be
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* defined in the board configuration's DTS.
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*/
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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};
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};
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5
soc/x86/lakemont/CMakeLists.txt
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soc/x86/lakemont/CMakeLists.txt
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# Copyright (c) 2021 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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zephyr_cc_option(-march=pentium)
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soc/x86/lakemont/Kconfig.defconfig
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soc/x86/lakemont/Kconfig.defconfig
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# Copyright (c) 2021 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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if SOC_LAKEMONT
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config SOC
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default "lakemont"
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 32768
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# Can be enabled once UART is defined in board
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# configuration.
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config X86_VERY_EARLY_CONSOLE
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default n
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# Target platforms are usually not PC-compatible
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# (e.g. without BIOS, ACPI, etc.).
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config X86_PC_COMPATIBLE
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default n
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endif
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soc/x86/lakemont/Kconfig.soc
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soc/x86/lakemont/Kconfig.soc
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@ -0,0 +1,14 @@
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# Copyright (c) 2021 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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config SOC_LAKEMONT
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bool "Intel Lakemont SoC"
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select X86
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select CPU_LAKEMONT
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select X86_MMU if FPU
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select X86_SSE if FPU
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select X86_SSE2 if FPU
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select X86_SSE3 if FPU
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select X86_SSSE3 if FPU
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select ARCH_HAS_USERSPACE
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soc/x86/lakemont/linker.ld
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soc/x86/lakemont/linker.ld
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/*
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* Copyright (c) 2011-2014, Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arch/x86/memory.ld>
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#include <arch/x86/ia32/linker.ld>
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soc/x86/lakemont/soc.h
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10
soc/x86/lakemont/soc.h
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/*
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* Copyright (c) 2021 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __SOC_H_
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#define __SOC_H_
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#endif /* __SOC_H_ */
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