drivers: pinctrl: add SiFive pinctrl driver
Add a pinctrl driver used in FE310-based boards. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
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@ -13,3 +13,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_STM32 pinctrl_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_KINETIS pinctrl_kinetis.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_XEC pinctrl_mchp_xec.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCUX_RT pinctrl_mcux_rt.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_SIFIVE pinctrl_sifive.c)
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@ -38,5 +38,6 @@ source "drivers/pinctrl/Kconfig.stm32"
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source "drivers/pinctrl/Kconfig.kinetis"
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source "drivers/pinctrl/Kconfig.xec"
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source "drivers/pinctrl/Kconfig.mcux"
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source "drivers/pinctrl/Kconfig.sifive"
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endif # PINCTRL
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drivers/pinctrl/Kconfig.sifive
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drivers/pinctrl/Kconfig.sifive
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@ -0,0 +1,11 @@
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# Copyright (c) 2022 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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DT_COMPAT_SIFIVE_PINCTRL := sifive,pinctrl
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config PINCTRL_SIFIVE
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bool "SiFive Freedom SoC pinmux driver"
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depends on SOC_SERIES_RISCV_SIFIVE_FREEDOM
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default $(dt_compat_enabled,$(DT_COMPAT_SIFIVE_PINCTRL))
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help
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Enable driver for the SiFive Freedom SoC pinctrl driver
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52
drivers/pinctrl/pinctrl_sifive.c
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drivers/pinctrl/pinctrl_sifive.c
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/*
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* Copyright (c) 2022 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT sifive_pinctrl
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#include <devicetree.h>
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#include <drivers/pinctrl.h>
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#include <soc.h>
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#define PINCTRL_BASE_ADDR DT_INST_REG_ADDR(0)
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#define PINCTRL_IOF_EN (PINCTRL_BASE_ADDR + 0x0)
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#define PINCTRL_IOF_SEL (PINCTRL_BASE_ADDR + 0x4)
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static int pinctrl_sifive_set(uint32_t pin, uint32_t func)
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{
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uint32_t val;
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if (func > SIFIVE_PINMUX_IOF1 || pin >= SIFIVE_PINMUX_PINS) {
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return -EINVAL;
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}
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val = sys_read32(PINCTRL_IOF_SEL);
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if (func == SIFIVE_PINMUX_IOF1) {
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val |= (SIFIVE_PINMUX_IOF1 << pin);
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} else {
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val &= ~(SIFIVE_PINMUX_IOF1 << pin);
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}
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sys_write32(val, PINCTRL_IOF_SEL);
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/* Enable IO function for this pin */
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val = sys_read32(PINCTRL_IOF_EN);
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val |= BIT(pin);
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sys_write32(val, PINCTRL_IOF_EN);
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return 0;
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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ARG_UNUSED(reg);
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int i;
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for (i = 0; i < pin_cnt; i++) {
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pinctrl_sifive_set(pins[i].pin, pins[i].iof);
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}
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return 0;
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}
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dts/bindings/pinctrl/sifive,pinctrl.yaml
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dts/bindings/pinctrl/sifive,pinctrl.yaml
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# Copyright (c) 2022 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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description: |
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SiFive FE310 IO Function (iof) binding covers the IOF_EN/IOF_SEL registers
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that are a subset of the GPIO controller. You can use this node to set the
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value of IOF_EN/IOF_SEL registers to control pin settings.
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Device pin configuration should be placed in the child nodes of this node.
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Populate the 'pinmux' field with a pair consisting of a pin number and its IO
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function. The available IO functions are:
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- SIFIVE_PINMUX_IOF0
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- SIFIVE_PINMUX_IOF1
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For example, setting pins 16 and 17 both to IOF0 would look like this:
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#include <dt-bindings/pinctrl/sifive-pinctrl.h>
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&pinctrl {
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uart0_rx_default: uart0_rx_default {
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pinmux = <16 SIFIVE_PINMUX_IOF0>;
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};
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uart0_tx_default: uart0_tx_default {
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pinmux = <17 SIFIVE_PINMUX_IOF0>;
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};
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};
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compatible: "sifive,pinctrl"
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include: base.yaml
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properties:
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reg:
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required: true
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child-binding:
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description: |
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This binding gives a base representation of the SiFive FE310 pins
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configuration.
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properties:
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pinmux:
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required: true
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type: array
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description: |
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SiFive FE310 pin's configuration (pin, IO function).
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soc/riscv/riscv-privilege/sifive-freedom/pinctrl_soc.h
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soc/riscv/riscv-privilege/sifive-freedom/pinctrl_soc.h
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/*
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* Copyright (c) 2022 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_RISCV_RISCV_PRIVILEGE_SIFIVE_FREEDOM_PINCTRL_H_
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#define ZEPHYR_SOC_RISCV_RISCV_PRIVILEGE_SIFIVE_FREEDOM_PINCTRL_H_
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#include <zephyr/types.h>
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typedef struct pinctrl_soc_pin_t {
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uint8_t pin;
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uint8_t iof;
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} pinctrl_soc_pin_t;
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#define SIFIVE_DT_PIN(node_id) \
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{ \
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.pin = DT_PROP_BY_IDX(node_id, pinmux, 0), \
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.iof = DT_PROP_BY_IDX(node_id, pinmux, 1) \
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},
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#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
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SIFIVE_DT_PIN(DT_PROP_BY_IDX(node_id, prop, idx))
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
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{ DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) }
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#endif /* ZEPHYR_SOC_RISCV_RISCV_PRIVILEGE_SIFIVE_FREEDOM_PINCTRL_H_ */
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