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x86: Cleanup linker scripts to use new DTS macros

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Rework x86 linker scripts to use DT_REG_ADDR/DT_REG_SIZE on
DT_CHOSEN(zephyr_sram) and DT_CHOSEN(zephyr_flash).  As part of this
we remove the dts_fixup.h.  Using DT_REG_SIZE means we don't have to
adjust the sizes by 1024.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-04-29 10:11:28 -05:00 • committed by Kumar Gala
commit 3dd2f610b0
8 changed files with 21 additions and 58 deletions
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4
include/arch/x86/ia32/linker.ld
View file

@ -359,11 +359,11 @@ SECTIONS
__data_ram_end = .;
/* All unused memory also owned by the kernel for heaps */
__kernel_ram_end = PHYS_RAM_ADDR + KB(DT_RAM_SIZE);
__kernel_ram_end = PHYS_RAM_ADDR + PHYS_RAM_SIZE;
__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;
_image_ram_end = .;
_image_ram_all = (PHYS_RAM_ADDR + KB(DT_RAM_SIZE)) - _image_ram_start;
_image_ram_all = (PHYS_RAM_ADDR + PHYS_RAM_SIZE) - _image_ram_start;
_end = .; /* end of image */

2
include/arch/x86/intel64/linker.ld
View file

@ -188,7 +188,7 @@ SECTIONS
_end = .;
/* All unused memory also owned by the kernel for heaps */
__kernel_ram_end = PHYS_RAM_ADDR + KB(DT_RAM_SIZE);
__kernel_ram_end = PHYS_RAM_ADDR + PHYS_RAM_SIZE;
__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;
#include <linker/debug-sections.ld>

14
soc/x86/apollo_lake/dts_fixup.h
View file

@ -1,14 +0,0 @@
/*
* Copyright (c) 2018-2019 Intel Corporation Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* SoC level DTS fixup file */
#define DT_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
#define DT_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS
#define DT_RAM_SIZE CONFIG_SRAM_SIZE
#define DT_ROM_SIZE CONFIG_FLASH_SIZE
/* End of SoC Level DTS fixup file */

7
soc/x86/apollo_lake/linker.ld
View file

@ -8,12 +8,13 @@
#include <autoconf.h>
#include <devicetree.h>
#define PHYS_LOAD_ADDR DT_PHYS_RAM_ADDR
#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
#define PHYS_RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
#define PHYS_RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
#define PHYS_LOAD_ADDR PHYS_RAM_ADDR
MEMORY
{
RAM (wx) : ORIGIN = DT_PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K
RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = PHYS_RAM_SIZE
/*
* It doesn't matter where this region goes as it is stripped from the

9
soc/x86/atom/dts_fixup.h
View file

@ -1,9 +0,0 @@
/* SPDX-License-Identifier: Apache-2.0 */
/* SoC level DTS fixup file */
#define DT_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
#define DT_RAM_SIZE CONFIG_SRAM_SIZE
/* End of SoC Level DTS fixup file */

15
soc/x86/atom/linker.ld
View file

@ -17,22 +17,21 @@
/* physical address where the kernel is loaded */
/* physical address of RAM */
#define PHYS_RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
#define PHYS_RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
#ifdef CONFIG_XIP
#define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR
#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
#define PHYS_LOAD_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
#else /* !CONFIG_XIP */
#define PHYS_LOAD_ADDR DT_PHYS_RAM_ADDR
#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
#define PHYS_LOAD_ADDR PHYS_RAM_ADDR
#endif /* CONFIG_XIP */
MEMORY
{
#ifdef CONFIG_XIP
ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_ROM_SIZE*1K
RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K
#else /* !CONFIG_XIP */
RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_RAM_SIZE*1K
ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
#endif /* CONFIG_XIP */
RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = PHYS_RAM_SIZE
/*
* It doesn't matter where this region goes as it is stripped from the

13
soc/x86/ia32/dts_fixup.h
View file

@ -1,13 +0,0 @@
/* SPDX-License-Identifier: Apache-2.0 */
/* SoC level DTS fixup file */
#define DT_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
#define DT_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS
#define DT_RAM_SIZE CONFIG_SRAM_SIZE
#define DT_ROM_SIZE CONFIG_FLASH_SIZE
/* End of SoC Level DTS fixup file */

15
soc/x86/ia32/linker.ld
View file

@ -19,22 +19,21 @@
/* physical address where the kernel is loaded */
/* physical address of RAM */
#define PHYS_RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
#define PHYS_RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
#ifdef CONFIG_XIP
#define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR
#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
#define PHYS_LOAD_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
#else /* !CONFIG_XIP */
#define PHYS_LOAD_ADDR DT_PHYS_RAM_ADDR
#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
#define PHYS_LOAD_ADDR PHYS_RAM_ADDR
#endif /* CONFIG_XIP */
MEMORY
{
#ifdef CONFIG_XIP
ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_ROM_SIZE*1K
RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K
#else /* !CONFIG_XIP */
RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K
ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
#endif /* CONFIG_XIP */
RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = PHYS_RAM_SIZE
/*
* It doesn't matter where this region goes as it is stripped from the