arch: arm: cortex_m: Rework DT_NUM_IRQ_PRIO_BITS
To remove the need to have DT_NUM_IRQ_PRIO_BITS defined in every dts_fixup.h we can just handle the few variant cases in irq.h. This allows us to remove DT_NUM_MPU_REGIONS from all the dts_fixup.h files. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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7 changed files with 38 additions and 9 deletions
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@ -88,10 +88,10 @@ void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
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* affecting performance (can still be useful on systems with a
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* reduced set of priorities, like Cortex-M0/M0+).
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*/
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__ASSERT(prio <= (BIT(DT_NUM_IRQ_PRIO_BITS) - 1),
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__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
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"invalid priority %d! values must be less than %lu\n",
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prio - _IRQ_PRIO_OFFSET,
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BIT(DT_NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
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BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
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NVIC_SetPriority((IRQn_Type)irq, prio);
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}
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@ -16,10 +16,13 @@
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#include <soc.h>
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#include <arch/arm/aarch32/cortex_m/nvic.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* CP10 Access Bits */
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#define CPACR_CP10_Pos 20U
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#define CPACR_CP10_Msk (3UL << CPACR_CP10_Pos)
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@ -84,12 +87,12 @@ typedef enum {
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#ifndef __MPU_PRESENT
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#define __MPU_PRESENT 0U
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#endif
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#define __NVIC_PRIO_BITS DT_NUM_IRQ_PRIO_BITS
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#define __NVIC_PRIO_BITS NUM_IRQ_PRIO_BITS
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#define __Vendor_SysTickConfig 0 /* Default to standard SysTick */
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#endif /* __NVIC_PRIO_BITS */
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#if __NVIC_PRIO_BITS != DT_NUM_IRQ_PRIO_BITS
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#error "DT_NUM_IRQ_PRIO_BITS and __NVIC_PRIO_BITS are not set to the same value"
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#if __NVIC_PRIO_BITS != NUM_IRQ_PRIO_BITS
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#error "NUM_IRQ_PRIO_BITS and __NVIC_PRIO_BITS are not set to the same value"
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#endif
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#ifdef __cplusplus
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24
include/arch/arm/aarch32/cortex_m/nvic.h
Normal file
24
include/arch/arm/aarch32/cortex_m/nvic.h
Normal file
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@ -0,0 +1,24 @@
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/*
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* Copyright (c) 2020, Linaro Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_NVIC_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_NVIC_H_
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#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)
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/* The order here is on purpose since ARMv8-M SoCs may define
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* CONFIG_ARMV6_M_ARMV8_M_BASELINE or CONFIG_ARMV7_M_ARMV8_M_MAINLINE
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* so we want to check for ARMv8-M first.
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*/
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#define NVIC_NODEID DT_INST(0, arm_v8m_nvic)
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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#define NVIC_NODEID DT_INST(0, arm_v7m_nvic)
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#elif defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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#define NVIC_NODEID DT_INST(0, arm_v6m_nvic)
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#endif
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#define NUM_IRQ_PRIO_BITS DT_PROP(NVIC_NODEID, arm_num_irq_priority_bits)
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_NVIC_H_ */
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@ -17,8 +17,10 @@
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#include <devicetree.h>
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#include <arch/arm/aarch32/cortex_m/nvic.h>
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/* for assembler, only works with constants */
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#define Z_EXC_PRIO(pri) (((pri) << (8 - DT_NUM_IRQ_PRIO_BITS)) & 0xff)
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#define Z_EXC_PRIO(pri) (((pri) << (8 - NUM_IRQ_PRIO_BITS)) & 0xff)
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/*
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* In architecture variants with non-programmable fault exceptions
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@ -280,6 +280,6 @@ typedef enum IRQn {
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*/
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#define __MPU_PRESENT 1
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#define __NVIC_PRIO_BITS DT_NUM_IRQ_PRIO_BITS
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#define __NVIC_PRIO_BITS NUM_IRQ_PRIO_BITS
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#endif
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@ -23,7 +23,7 @@ typedef enum {
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#define __CM4_REV 0
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#define __MPU_PRESENT 1
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#define __NVIC_PRIO_BITS DT_NUM_IRQ_PRIO_BITS
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#define __NVIC_PRIO_BITS NUM_IRQ_PRIO_BITS
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#define __Vendor_SysTickConfig 0
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#define __FPU_PRESENT 1
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@ -35,7 +35,7 @@ typedef enum {
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#define __CM4_REV 0
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#define __MPU_PRESENT 0 /* Zephyr has no MPU support */
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#define __NVIC_PRIO_BITS DT_NUM_IRQ_PRIO_BITS
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#define __NVIC_PRIO_BITS NUM_IRQ_PRIO_BITS
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#define __Vendor_SysTickConfig 0 /* Default to standard SysTick */
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#endif /* TI_SIMPLELINK_CC32XX_SOC_H_ */
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