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arch: arm: cortex_m: Rework DT_NUM_IRQ_PRIO_BITS

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To remove the need to have DT_NUM_IRQ_PRIO_BITS defined in every
dts_fixup.h we can just handle the few variant cases in irq.h.  This
allows us to remove DT_NUM_MPU_REGIONS from all the dts_fixup.h files.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-04-15 11:27:43 -05:00 • committed by Ioannis Glaropoulos
commit 5648df39ac
7 changed files with 38 additions and 9 deletions
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4
arch/arm/core/aarch32/irq_manage.c
View file

@ -88,10 +88,10 @@ void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
* affecting performance (can still be useful on systems with a
* reduced set of priorities, like Cortex-M0/M0+).
*/
__ASSERT(prio <= (BIT(DT_NUM_IRQ_PRIO_BITS) - 1),
__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
"invalid priority %d! values must be less than %lu\n",
prio - _IRQ_PRIO_OFFSET,
BIT(DT_NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
NVIC_SetPriority((IRQn_Type)irq, prio);
}

9
include/arch/arm/aarch32/cortex_m/cmsis.h
View file

@ -16,10 +16,13 @@
#include <soc.h>
#include <arch/arm/aarch32/cortex_m/nvic.h>
#ifdef __cplusplus
extern "C" {
#endif
/* CP10 Access Bits */
#define CPACR_CP10_Pos 20U
#define CPACR_CP10_Msk (3UL << CPACR_CP10_Pos)
@ -84,12 +87,12 @@ typedef enum {
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#endif
#define __NVIC_PRIO_BITS DT_NUM_IRQ_PRIO_BITS
#define __NVIC_PRIO_BITS NUM_IRQ_PRIO_BITS
#define __Vendor_SysTickConfig 0 /* Default to standard SysTick */
#endif /* __NVIC_PRIO_BITS */
#if __NVIC_PRIO_BITS != DT_NUM_IRQ_PRIO_BITS
#error "DT_NUM_IRQ_PRIO_BITS and __NVIC_PRIO_BITS are not set to the same value"
#if __NVIC_PRIO_BITS != NUM_IRQ_PRIO_BITS
#error "NUM_IRQ_PRIO_BITS and __NVIC_PRIO_BITS are not set to the same value"
#endif
#ifdef __cplusplus

24
include/arch/arm/aarch32/cortex_m/nvic.h Normal file
View file

@ -0,0 +1,24 @@
/*
* Copyright (c) 2020, Linaro Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_NVIC_H_
#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_NVIC_H_
#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)
/* The order here is on purpose since ARMv8-M SoCs may define
* CONFIG_ARMV6_M_ARMV8_M_BASELINE or CONFIG_ARMV7_M_ARMV8_M_MAINLINE
* so we want to check for ARMv8-M first.
*/
#define NVIC_NODEID DT_INST(0, arm_v8m_nvic)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
#define NVIC_NODEID DT_INST(0, arm_v7m_nvic)
#elif defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#define NVIC_NODEID DT_INST(0, arm_v6m_nvic)
#endif
#define NUM_IRQ_PRIO_BITS DT_PROP(NVIC_NODEID, arm_num_irq_priority_bits)
#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_NVIC_H_ */

4
include/arch/arm/aarch32/exc.h
View file

@ -17,8 +17,10 @@
#include <devicetree.h>
#include <arch/arm/aarch32/cortex_m/nvic.h>
/* for assembler, only works with constants */
#define Z_EXC_PRIO(pri) (((pri) << (8 - DT_NUM_IRQ_PRIO_BITS)) & 0xff)
#define Z_EXC_PRIO(pri) (((pri) << (8 - NUM_IRQ_PRIO_BITS)) & 0xff)
/*
* In architecture variants with non-programmable fault exceptions

2
soc/arm/bcm_vk/valkyrie/soc.h
View file

@ -280,6 +280,6 @@ typedef enum IRQn {
*/
#define __MPU_PRESENT 1
#define __NVIC_PRIO_BITS DT_NUM_IRQ_PRIO_BITS
#define __NVIC_PRIO_BITS NUM_IRQ_PRIO_BITS
#endif

2
soc/arm/ti_simplelink/cc13x2_cc26x2/soc.h
View file

@ -23,7 +23,7 @@ typedef enum {
#define __CM4_REV 0
#define __MPU_PRESENT 1
#define __NVIC_PRIO_BITS DT_NUM_IRQ_PRIO_BITS
#define __NVIC_PRIO_BITS NUM_IRQ_PRIO_BITS
#define __Vendor_SysTickConfig 0
#define __FPU_PRESENT 1

2
soc/arm/ti_simplelink/cc32xx/soc.h
View file

@ -35,7 +35,7 @@ typedef enum {
#define __CM4_REV 0
#define __MPU_PRESENT 0 /* Zephyr has no MPU support */
#define __NVIC_PRIO_BITS DT_NUM_IRQ_PRIO_BITS
#define __NVIC_PRIO_BITS NUM_IRQ_PRIO_BITS
#define __Vendor_SysTickConfig 0 /* Default to standard SysTick */
#endif /* TI_SIMPLELINK_CC32XX_SOC_H_ */