Commit graph

4579 commits

Author SHA1 Message Date
Michael Hope 6a29195aa0 boards: add ch32v003evt 2024-05-17 19:44:48 +02:00
Michael Hope e678dbb20f drivers: add ch32v00x pinctrl support 2024-05-17 19:39:24 +02:00
Michael Hope 0c2809c708 soc: update the interrupt handling 2024-05-17 19:38:17 +02:00
Michael Hope 89c5f6b301 soc: add clock configuration 2024-05-17 19:38:17 +02:00
Michael Hope c2b93829cc soc: depend on the HAL 2024-05-17 19:38:17 +02:00
Michael Hope c2671eb05f soc: add wch_ch32v003 stubs 2024-05-17 19:36:40 +02:00
Rafał Kuźnia 9cba85bb8d soc: nrf54h: use word accesses to SPI_DW peripheral
The nRF54H20 EXMIF peripheral requires word accesses. Doing accesses of
byte or half-word sizes results in bus fault.

Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
2024-05-17 16:18:56 +01:00
Jerzy Kasenberg 82ca880fb9 drivers: clock_control: Smartbond: Add runtime frequency support
RC32K and RCX low power clocks require runtime calibration to work
correctly.
Frequency of those clock can differ from chip to chip, one constant
value from Kconfig may not be best when low power clock (sourced
from RCX or RC32K) is used for system tick.

This code modifies global z_clock_hw_cycles_per_sec variable that
is used when TIMER_READS_ITS_FREQUENCY_AT_RUNTIME is enabled
in Kconfig.

Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
2024-05-17 09:29:58 +02:00
Mahesh Mahadevan 8824fa8bdd soc: rw6xx: Add power management support
Add support for Power modes 1 and 2.
The wakeup from power mode 2 is from the os timer.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2024-05-16 18:53:51 -04:00
Mahesh Mahadevan 1192c9be6b soc: nxp: Enable support for OS Timer on RW platform
The OS Timer will be used as the System Timer.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2024-05-16 18:53:51 -04:00
Alberto Escolar Piedras 7ab8e39519 soc: Add SOC_COMPATIBLE_NRF54L* options
In preparation for simulated nRF54L targets,
let's add kconfig options aking to the ones
we have for the nRF52 and 53 devices.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2024-05-16 15:19:08 +01:00
Jérémy LOCHE - MAKEEN Energy 724be84957 nxp: imx7d-6sx: add rom_start relocation
Add the Kconfig options and use the aliased
addresses for the bootcode regions of the IMX7D
and IMX6SX SOCs to allow the Linux rproc
framework to load the irq-vectors into
the correct memory areas.

Activating this option might enlarge the bin
file if the zephyr,flash and rom_start chosen
region addresses are not matching.

It is up to the user to enable this feature
based on code location choices (OCRAM, DDR, TCM...).

Signed-off-by: Jérémy LOCHE - MAKEEN Energy <jlh@makeenenergy.com>
2024-05-16 15:52:20 +02:00
Evgeniy Paltsev 39971ad447 ARC: nSIM: hs5x: align sys clock with other SMP nSIM configs
Align SYS_CLOCK_HW_CYCLES_PER_SEC with other SMP nSIM
configurations and set it to 1000000.

This significantly reduce verification time on HS5x platforms.

Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2024-05-16 15:51:34 +02:00
Mahesh Mahadevan c68a8818c4 soc: n94x: Add USBHS support
Add support for USBHS controller

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2024-05-16 09:17:18 +02:00
Rafal Dyla 13aa26eac2 manifest: Adding nRF Services library
Adding nRF Services library to the hal-nordic repo

Signed-off-by: Rafal Dyla <rafal.dyla@nordicsemi.no>
2024-05-15 09:25:30 +01:00
Declan Snyder 79025c5524 soc: nxp: rw: Support ADC and DAC
Add DT node entries to RW for DAC and ADC.

Support the SOC required initialization of the DAC and ADC on RW.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-05-14 18:23:22 -04:00
Daniel DeGrasse 53ceae5f58 soc: nxp: rw: use correct mask for FLEXSPI clock setup divider
Mask for FLEXSPI clock divider was being used when setting the FLEXSPI
clock selector value. Correct this to use the mask for the selector
instead of the divider.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-05-14 18:21:57 -04:00
Jerzy Kasenberg f2e3d3f951 soc: smartbond: Move PM_DEVICE dependency to soc
For DA1469x if PM config is selected PM_DEVICE must also
be selected for GPIO to work when device enters/exists
deep sleep.

Previously GPIO and regulator drivers selected PM_DEVICE
when PM was enabled.
Now it is moved to SOC instead.

PM_DEVICE selection in GPIO could result in circular dependency
for mcux if MEMC_MCUX_FLEXSPI (which is already dependent on PM_DEVICE)
was to be additionally dependent on GPIO.

Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
2024-05-14 17:05:03 +02:00
Trung Hieu Le 3cb5e4ed54 boards: nxp: rt1170_evk: Add XMCD bootheader
Currently, only DCD bootheader was supported to configure the SDRAM.

On IMX RT1170, XMCD can be used as an alternative boot header to DCD.
XMCD is more advanced than DCD and enhances SDRAM access speed.
This is benefit for SDRAM access application.

Signed-off-by: Trung Hieu Le <trunghieu.le@nxp.com>
2024-05-14 15:54:20 +02:00
Marcin Szymczyk 41b856f8dd soc: nordic: add vpr_launcher in sysbuild
`SB_CONFIG_VPR_LAUNCHER` can now be used in building a VPR target,
to enable automatic building of image that will launch the VPR.

Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2024-05-14 13:24:45 +02:00
Daniel DeGrasse 84b8e92445 soc: nxp: imxrt: clock imxrt1042 SOC at 528 MHz
iMXRT1042 SOC should be clocked at 528 MHz maximum. Correct the clock
setup to use the system PLL.

Fixes #70755

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-05-13 16:37:17 -04:00
Daniel DeGrasse 9668b35ce7 soc: nxp: imxrt: allow configuring system pll on iMXRT10xx series
Allow configuration of the system pll on the iMXRT10xx series parts, via
a fractional pll node under the CCM module.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-05-13 16:37:17 -04:00
Nicolas Pitre 57305971d1 kernel: mmu: abstract access to page frame flags and address
Introduce z_page_frame_set() and z_page_frame_clear() to manipulate
flags. Obtain the virtual address using the existing
z_page_frame_to_virt(). This will make changes to the page frame
structure easier.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2024-05-13 16:04:40 -04:00
Tim Lin d371a89c3f ITE: soc: Add the variant of it82002bw
Add the variant of it82002bw

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2024-05-13 11:39:10 +02:00
Tim Lin 682a4c936a ITE: soc: Add the variant of it81302dx
Add the variant of it81302dx

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2024-05-13 11:39:10 +02:00
Tim Lin f89934451f ITE: soc: Add the variant of it81202dx
Add the variant of it81202dx

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2024-05-13 11:39:10 +02:00
Tim Lin dc44966f02 ITE: soc: Kconfig: Cleanup it8xxx2 Kconfig
The ILM_MAX_SIZE of different chip variants can be declared in the
Kconfig of the respective variant.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2024-05-13 11:39:10 +02:00
Grzegorz Swiderski 70edbd1cf5 soc: nordic: Add system for validating DT headers against MDK
Hardware-specific properties should stay in sync with the definitions
provided by MDK. Existing measures for this include:

  * The `validate_base_addresses.c` file included in every build;
  * The `nordic-nrf-ficr-nrf54h20.h` header generated from SVD.

If there's information that cannot be extracted from SVD, it may have to
be validated against C types. Add `validate_binding_headers.c` for this
purpose, which automagically includes all `dt-bindings` headers included
by DTS in a given build.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
2024-05-13 10:36:37 +03:00
Dino Li f76f2928f1 espi/it8xxx2: enable EC to accept port 81 cycle
This allows EC to accept 2 bytes of port 80 data written from the Host.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2024-05-10 20:25:13 -04:00
Phi Bang Nguyen f621407d50 modules: mcux: Drop HAS_MCUX_CSI config
The HAS_MCUX_CSI (as well as all the HAS_MCUX_XXX) config was obsolete
and has been replaced by the DT_HAS_NXP_IMX_CSI_ENABLED (i.e.
DT_HAS_XXX_ENABLED). Drop it as well as all the dependencies on it.

Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
2024-05-10 18:09:44 -04:00
Phi Bang Nguyen 1e9448b404 soc: nxp: imxrt11xx: Enable clock for LPCI2C6
Enable clock for LPCI2C6. This is needed to control some
peripherals such as camera sensor.

Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
2024-05-10 18:06:47 -04:00
cyliang tw de58070fa4 drivers: pinctrl: support digital-path-disable for Numaker
Add new property digital-path-disable for Nuvoton numaker pinctrl driver.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2024-05-10 18:06:15 -04:00
Luis Ubieda 3dc91dda7d boards: nxp: Fix usage of DT_CHOSEN() macro to get chosen Zephyr Flash
Used multiple places in the tree. The idea is to determine if this node
corresponds to a specific node (e.g: flexspi) so that specific
configurations can get done. Without the fix, the macro expansions were
defaulting to false.

Signed-off-by: Luis Ubieda <luisf@croxel.com>
2024-05-10 18:05:03 -04:00
Tomasz Moń 3502b71386 soc: nordic: nrf54h20: Add default ARM MPU regions
Commit 149df6b61b ("soc: nordic: nrf54h20: Disable USBHS core cache")
inadvertedly removed default MPU regions defined in arm_mpu_regions.c.
Without the SRAM_0 region defined all builds with asserts enabled result
in failed assertion even before the kernel inits. The failed assertion
is the very last step of arch_kernel_init() when MPU areas are marked
for dynamic regions. Because the failure occurs so early, the device
appears completely dead.

Fix the issue by bringing the default regions to nrf54h20 custom
regions file.

Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
2024-05-10 14:39:44 -05:00
Jamie McCrae 37c49f2af9 soc: nuvoton: npcx: npcx9: Move non-soc Kconfig to right file
Moves a non-SoC Kconfig to the normal Kconfig file, as this symbol
has nothing to do with the SoC selection itself

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2024-05-10 11:49:31 +03:00
Grzegorz Swiderski f7d6880fce soc: nordic: Extend address validation for nRF54H20
Add `CHECK_DT_REG()` entries for a few additional peripheral types:
BELLBOARD, CCM, GRTC, HSFLL, UICR, and VPR.

For peripheral instances outside of the Global Domain, such as DPPIC020,
use domain-specific defines like NRF_RADIOCORE_DPPIC020 when validating.
These are always defined by the MDK, while NRF_DPPIC020 isn't guaranteed
to exist in those cases. Revise existing macro checks accordingly.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
2024-05-09 12:41:17 -04:00
Grzegorz Swiderski 8212215779 soc: nordic: nrf54h20: Use KERNEL_INIT_PRIORITY_DEFAULT
Make the SoC initialization priority configurable.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
2024-05-09 12:41:17 -04:00
Grzegorz Swiderski 8e63e0657b soc: nordic: nrf54h20: Make HSFLL trims optional
If no HSFLL needs trimming, then `trim_hsfll()` should be compiled out.
This makes it easier to reuse the rest of `soc.c` out of tree.

Furthermore, some HSFLL instances can be trimmed before booting Zephyr,
so the FICR client properties in the DT binding should not be required.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
2024-05-09 12:41:17 -04:00
Sebastian Głąb 2f17c46fb1 drivers: wdt: nrf: Add WDT instances that exist in nrf54h20
Add WDT instances no. 010, 011, 131, 132.

Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
2024-05-09 15:44:40 +02:00
Richard Wheatley 32b69f53aa soc: ambiq: Add Clocks per tick
Define System clocks per tick

Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
2024-05-08 12:41:14 +02:00
Richard Wheatley 87070aae79 soc: ambiq: apollo4x
Added Power Management to Ambiq apollo4p SOCs

Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
2024-05-08 12:41:14 +02:00
Richard Wheatley 05371a41f6 soc: ambiq: apollo4x: Kconfig Update Selections
Add Selections to match HAL updates

Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
2024-05-08 12:41:14 +02:00
Sylvio Alves 3f07d4b6ab soc: espressif: add misssing external xtal kconfig entry
External XTAL usage is missing a Bootstrap Cycle configuration
in Kconfig, causing build to failure when CONFIG_RTC_CLK_SRC_EXT_CRYS
is selected.

Fixes #72190

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-05-07 21:21:46 -04:00
Hao Luo d71c97f072 drivers: pinctrl: Add pinctrl driver for Apollo3 SoCs
This commit adds pinctrl support for Apollo3 SoCs.

Signed-off-by: Hao Luo <hluo@ambiq.com>
2024-05-07 18:57:19 +02:00
Hao Luo 7b115fea81 soc: arm: ambiq: apollo3: Add support for Apollo3 Blue SoC
Add all required parts (new SoC family/series, device tree) for
the Ambiq Apollo3 Blue SoC.

Signed-off-by: Hao Luo <hluo@ambiq.com>
2024-05-07 18:57:19 +02:00
Hao Luo a0b07212e9 soc: arm: ambiq: apollo3: Add support for Apollo3 Blue Plus SoC
Add all required parts (new SoC family/series, device tree) for
the Ambiq Apollo3 Blue Plus SoC.

Signed-off-by: Hao Luo <hluo@ambiq.com>
2024-05-07 18:57:19 +02:00
Tomasz Moń 149df6b61b soc: nordic: nrf54h20: Disable USBHS core cache
Configure USBHS core registers as non-cachable to prevent D-Cache from
inhibiting volatile accesses to the USBHS core registers.

Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
2024-05-07 13:50:58 +01:00
Rafał Kuźnia fe98eb767c soc: nrf54h: Enable SPI DW HSSI register layout
The nRF54H20 implements a variant of the SPI DW peripheral that
has slightly different register layout. Enable it in the defconfig.

Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
2024-05-07 09:52:53 +01:00
Angelo Dureghello 5341f4a8ad soc: st: set soc-level phy priority
Introducing MDIO and PHY support for stm32, phy driver gets
error (-116) if it tries to read phy chip id, since MDIO IP is
part of ETH IP, and eth hw module is still not initialized.

Forcing a priority that allows possibly connected PHY chip to be
detected properly at initial boot.

Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
2024-05-07 09:41:46 +02:00
Kai Vehmanen 2dd648698f soc/intel_adsp: ipc: initialize semaphore in driver init
The ipc driver device data (struct intel_adsp_ipc_data) contains a
semaphore. Upon device init, the device data is zeroed out. This is safe
for other fields, but the semaphore should be properly initialized
before use.

This lack of initialization leads to a system crash when CONFIG_POLL is
enabled (e.g. to enable CONFIG_SHELL), IPC driver handles an interrupt
and executes k_sem_give() on a uninitialized semaphore object. This will
eventually lead to null dereference in z_handle_obj_poll_events().

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-05-06 22:51:06 +01:00