ITE: drivers/i2c: add the compatibility of GPIO F2/F3 for i2c3
The default I2C channel 3 is used by alternate function of GPIO H1/H2 Krabby uses GPIO F2/F3 as I2C channel 3, so we need to add the compatibility of the GPIO F2/F3. TEST=test on it8xxx2_evb: zmake configure -b zephyr/projects/it8xxx2_evb/ Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
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5 changed files with 29 additions and 27 deletions
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@ -148,22 +148,6 @@ enum i2c_reset_cause {
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#define I2C_LINE_SDA_HIGH BIT(1)
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#define I2C_LINE_IDLE (I2C_LINE_SCL_HIGH | I2C_LINE_SDA_HIGH)
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struct i2c_pin {
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volatile uint8_t *mirror_clk;
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volatile uint8_t *mirror_data;
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uint8_t clk_mask;
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uint8_t data_mask;
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};
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static const struct i2c_pin i2c_pin_regs[] = {
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{ &GPDMRB, &GPDMRB, 0x08, 0x10},
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{ &GPDMRC, &GPDMRC, 0x02, 0x04},
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{ &GPDMRF, &GPDMRF, 0x40, 0x80},
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{ &GPDMRH, &GPDMRH, 0x02, 0x04},
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{ &GPDMRE, &GPDMRE, 0x01, 0x80},
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{ &GPDMRA, &GPDMRA, 0x10, 0x20},
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};
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static int i2c_parsing_return_value(const struct device *dev)
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{
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struct i2c_it8xxx2_data *data = DEV_DATA(dev);
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@ -201,12 +185,11 @@ static int i2c_get_line_levels(const struct device *dev)
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return IT83XX_SMB_SMBPCTL(base) & 0x03;
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}
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if (*i2c_pin_regs[config->port].mirror_clk &
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i2c_pin_regs[config->port].clk_mask) {
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if (IT83XX_I2C_TOS(base) & IT8XXX2_I2C_SCL_IN) {
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pin_sts |= I2C_LINE_SCL_HIGH;
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}
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if (*i2c_pin_regs[config->port].mirror_data &
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i2c_pin_regs[config->port].data_mask) {
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if (IT83XX_I2C_TOS(base) & IT8XXX2_I2C_SDA_IN) {
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pin_sts |= I2C_LINE_SDA_HIGH;
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}
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@ -905,8 +888,6 @@ static int i2c_it8xxx2_init(const struct device *dev)
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break;
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case DT_REG_ADDR(DT_NODELABEL(i2c3)):
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offset = CGC_OFFSET_SMBD;
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/* Enable SMBus D channel */
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GCR2 |= SMB3E;
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break;
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case DT_REG_ADDR(DT_NODELABEL(i2c4)):
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offset = CGC_OFFSET_SMBE;
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@ -162,10 +162,18 @@ static int pinmux_it8xxx2_init(const struct device *dev)
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IT8XXX2_GPIO_GCR &= ~(BIT(1) | BIT(2));
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/*
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* TODO: If SMBUS3 swaps from H group to F group, we have to
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* If SMBUS3 swaps from H group to F group, we have to
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* set SMB3PSEL = 1 in PMER3 register.
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*/
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if (DEVICE_DT_GET(DT_PHANDLE(DT_NODELABEL(i2c3), gpio_dev)) ==
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DEVICE_DT_GET(DT_NODELABEL(gpiof))) {
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struct gctrl_it8xxx2_regs *const gctrl_base =
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(struct gctrl_it8xxx2_regs *)
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DT_REG_ADDR(DT_NODELABEL(gctrl));
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gctrl_base->GCTRL_PMER3 |= IT8XXX2_GCTRL_SMB3PSEL;
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}
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/*
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* TODO: If UART2 swaps from bit2:1 to bit6:5 in H group, we
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* have to set UART1PSEL = 1 in UART1PMR register.
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@ -95,12 +95,18 @@
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pinctrl_i2c_data2: i2c_data2 {
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pinctrls = <&pinmuxf 7 IT8XXX2_PINMUX_FUNC_1>;
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};
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pinctrl_i2c_clk3: i2c_clk3 {
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pinctrl_i2c_clk3_gph1: i2c_clk3_gph1 {
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pinctrls = <&pinmuxh 1 IT8XXX2_PINMUX_FUNC_3>;
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};
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pinctrl_i2c_data3: i2c_data3 {
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pinctrl_i2c_data3_gph2: i2c_data3_gph2 {
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pinctrls = <&pinmuxh 2 IT8XXX2_PINMUX_FUNC_3>;
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};
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pinctrl_i2c_clk3_gpf2: i2c_clk3_gpf2 {
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pinctrls = <&pinmuxf 2 IT8XXX2_PINMUX_FUNC_4>;
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};
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pinctrl_i2c_data3_gpf3: i2c_data3_gpf3 {
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pinctrls = <&pinmuxf 3 IT8XXX2_PINMUX_FUNC_4>;
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};
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pinctrl_i2c_clk4: i2c_clk4 {
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pinctrls = <&pinmuxe 0 IT8XXX2_PINMUX_FUNC_3>;
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};
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@ -707,8 +707,8 @@
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label = "I2C_3";
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port-num = <3>;
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gpio-dev = <&gpioh>;
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pinctrl-0 = <&pinctrl_i2c_clk3 /* GPH1 */
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&pinctrl_i2c_data3>; /* GPH2 */
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pinctrl-0 = <&pinctrl_i2c_clk3_gph1 /* GPH1 */
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&pinctrl_i2c_data3_gph2>; /* GPH2 */
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};
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i2c4: i2c@f03500 {
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compatible = "ite,it8xxx2-i2c";
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@ -1652,6 +1652,11 @@ enum chip_pll_mode {
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#define IT83XX_I2C_RAMH2A(base) ECREG(base+0x50)
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#define IT83XX_I2C_CMD_ADDH2(base) ECREG(base+0x52)
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/* SMBus/I2C register fields */
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/* 0x07: Time Out Status */
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#define IT8XXX2_I2C_SCL_IN BIT(2)
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#define IT8XXX2_I2C_SDA_IN BIT(0)
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/* --- General Control (GCTRL) --- */
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#define IT83XX_GCTRL_BASE 0x00F02000
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@ -1847,6 +1852,8 @@ struct gctrl_it8xxx2_regs {
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#define IT8XXX2_GCTRL_LRSIWR BIT(2)
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#define IT8XXX2_GCTRL_LRSIPWRSWTR BIT(1)
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#define IT8XXX2_GCTRL_LRSIPGWR BIT(0)
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/* 0x46: Pin Multi-function Enable 3 */
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#define IT8XXX2_GCTRL_SMB3PSEL BIT(6)
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/* 0x4B: ETWD and UART Control */
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#define IT8XXX2_GCTRL_ETWD_HW_RST_EN BIT(0)
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/* Accept Port 80h Cycle */
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