soc: intel_s1000: use CAVS DSP wall clock timer for SMP
The DSP wall clock timer is a timer driven directly by external oscillator and is external to the CPU core(s). It provides a common and synchronized counter for all CPU cores (which is useful for SMP), instead of indepedently running local core timer (xtensa_timer). Signed-off-by: Daniel Leung <daniel.leung@intel.com>
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3 changed files with 39 additions and 8 deletions
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@ -1,7 +1,6 @@
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_MAIN_STACK_SIZE=2048
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=400000000
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CONFIG_SOC_INTEL_S1000=y
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CONFIG_BOARD_INTEL_S1000_CRB=y
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@ -19,4 +19,8 @@ config XTENSA_KERNEL_CPU_PTR_SR
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config SPI_DW_FIFO_DEPTH
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default 32
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 400000000 if XTENSA_TIMER
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default 38400000 if CAVS_TIMER
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endif
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@ -39,6 +39,8 @@
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#define CAVS_L2_AGG_INT_LEVEL4 DT_CAVS_ICTL_2_IRQ
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#define CAVS_L2_AGG_INT_LEVEL5 DT_CAVS_ICTL_3_IRQ
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#define CAVS_ICTL_INT_CPU_OFFSET(x) (0x40 * x)
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#define IOAPIC_EDGE 0
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#define IOAPIC_HIGH 0
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@ -100,6 +102,13 @@ struct soc_mclk_control_regs {
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#define SOC_NUM_LPGPDMAC 3
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#define SOC_NUM_CHANNELS_IN_DMAC 8
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/* DSP Wall Clock Timers (0 and 1) */
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#define DSP_WCT_IRQ(x) \
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SOC_AGGREGATE_IRQ(0, (23 + x), CAVS_L2_AGG_INT_LEVEL2)
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#define DSP_WCT_CS_TA(x) BIT(x)
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#define DSP_WCT_CS_TT(x) BIT(4 + x)
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/* SOC Resource Allocation Registers */
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#define SOC_RESOURCE_ALLOC_REG_BASE 0x00071A60
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/* bit field definition for LP GPDMA ownership register */
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@ -147,20 +156,39 @@ struct soc_dmic_shim_regs {
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struct soc_dsp_shim_regs {
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u32_t reserved[8];
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u64_t walclk;
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u64_t dspwctcs;
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u64_t dspwct0c;
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u64_t dspwct1c;
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u32_t reserved1[14];
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union {
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struct {
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u32_t walclk32_lo;
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u32_t walclk32_hi;
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};
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u64_t walclk;
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};
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u32_t dspwctcs;
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u32_t reserved1[1];
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union {
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struct {
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u32_t dspwct0c32_lo;
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u32_t dspwct0c32_hi;
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};
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u64_t dspwct0c;
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};
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union {
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struct {
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u32_t dspwct1c32_lo;
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u32_t dspwct1c32_hi;
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};
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u64_t dspwct1c;
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};
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u32_t reserved2[14];
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u32_t clkctl;
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u32_t clksts;
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u32_t reserved2[4];
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u32_t reserved3[4];
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u16_t pwrctl;
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u16_t pwrsts;
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u32_t lpsctl;
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u32_t lpsdmas0;
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u32_t lpsdmas1;
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u32_t reserved3[22];
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u32_t reserved4[22];
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};
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/* Global Control registers */
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