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soc: npcx: add support for npcx9 series in ecst.py script.

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This CL adds the support for npcx9m3f and npcx9m6f chips in ecst.py
script which generates the NPCX firmware header.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit is contained in:
Mulin Chao 2021-05-17 23:39:43 -07:00 • committed by Anas Nashif
commit d2cd3ed765
2 changed files with 6 additions and 2 deletions
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2
soc/arm/nuvoton_npcx/Kconfig
View file

@ -24,6 +24,8 @@ config NPCX_HEADER_CHIP
string
default "npcx7m6" if SOC_NPCX7M6FB || SOC_NPCX7M6FC
default "npcx7m7" if SOC_NPCX7M7FC
default "npcx9m3" if SOC_NPCX9M3F
default "npcx9m6" if SOC_NPCX9M6F
choice
prompt "Clock rate to use for SPI flash"

6
soc/arm/nuvoton_npcx/common/ecst/ecst_args.py
View file

@ -45,9 +45,11 @@ FW_CRC_START_OFFSET_DEFAULT = 0x0
POINTER_OFFSET_DEFAULT = 0x0
# Chips: convert from name to index.
CHIPS_INFO = {'npcx7m5': {'ram_address': 0x100A8000, 'ram_size': 0x20000},
CHIPS_INFO = {'npcx7m5': {'ram_address': 0x100a8000, 'ram_size': 0x20000},
'npcx7m6': {'ram_address': 0x10090000, 'ram_size': 0x40000},
'npcx7m7': {'ram_address': 0x10070000, 'ram_size': 0x60000}}
'npcx7m7': {'ram_address': 0x10070000, 'ram_size': 0x60000},
'npcx9m3': {'ram_address': 0x10080000, 'ram_size': 0x50000},
'npcx9m6': {'ram_address': 0x10090000, 'ram_size': 0x40000}}
DEFAULT_CHIP = 'npcx7m6'
# RAM related values