soc: npcx: add support for npcx9 series in ecst.py script.
This CL adds the support for npcx9m3f and npcx9m6f chips in ecst.py script which generates the NPCX firmware header. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
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2 changed files with 6 additions and 2 deletions
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@ -24,6 +24,8 @@ config NPCX_HEADER_CHIP
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string
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default "npcx7m6" if SOC_NPCX7M6FB || SOC_NPCX7M6FC
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default "npcx7m7" if SOC_NPCX7M7FC
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default "npcx9m3" if SOC_NPCX9M3F
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default "npcx9m6" if SOC_NPCX9M6F
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choice
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prompt "Clock rate to use for SPI flash"
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@ -45,9 +45,11 @@ FW_CRC_START_OFFSET_DEFAULT = 0x0
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POINTER_OFFSET_DEFAULT = 0x0
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# Chips: convert from name to index.
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CHIPS_INFO = {'npcx7m5': {'ram_address': 0x100A8000, 'ram_size': 0x20000},
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CHIPS_INFO = {'npcx7m5': {'ram_address': 0x100a8000, 'ram_size': 0x20000},
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'npcx7m6': {'ram_address': 0x10090000, 'ram_size': 0x40000},
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'npcx7m7': {'ram_address': 0x10070000, 'ram_size': 0x60000}}
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'npcx7m7': {'ram_address': 0x10070000, 'ram_size': 0x60000},
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'npcx9m3': {'ram_address': 0x10080000, 'ram_size': 0x50000},
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'npcx9m6': {'ram_address': 0x10090000, 'ram_size': 0x40000}}
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DEFAULT_CHIP = 'npcx7m6'
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# RAM related values
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