soc: arm: stm32h7: enable ART flash cache accelerator
Enable Instruction cache accelerator for Cortex M4 first 1MB of Flash. As per Reference Manual: no need for cache coherency management Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
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@ -67,6 +67,11 @@ static int stm32h7_m4_init(const struct device *arg)
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{
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uint32_t key;
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/* Enable ART Flash cache accelerator */
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_ART);
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LL_ART_SetBaseAddress(DT_REG_ADDR(DT_CHOSEN(zephyr_flash)));
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LL_ART_Enable();
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key = irq_lock();
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/* Install default handler that simply resets the CPU
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