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soc: arm: stm32h7: enable ART flash cache accelerator

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Enable Instruction cache accelerator for Cortex M4
first 1MB of Flash.
As per Reference Manual: no need for cache coherency management

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
This commit is contained in:
Alexandre Bourdiol 2021-06-15 18:05:25 +02:00 • committed by Anas Nashif
commit 1335228f58
1 changed files with 5 additions and 0 deletions
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5
soc/arm/st_stm32/stm32h7/soc_m4.c
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@ -67,6 +67,11 @@ static int stm32h7_m4_init(const struct device *arg)
{
uint32_t key;
/* Enable ART Flash cache accelerator */
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_ART);
LL_ART_SetBaseAddress(DT_REG_ADDR(DT_CHOSEN(zephyr_flash)));
LL_ART_Enable();
key = irq_lock();
/* Install default handler that simply resets the CPU