intc: esp32c3: use source as interrupt value
Using IRQ as source for interrupt values can fail when installing irq_connect_dynamic, as IRQ can previously be enabled. This updates the logic to use source map and allows default irq_enable() and irq_disable() to call esp32c3 interrupt allocator implementation. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
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4aad6d0d66
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30c45b0dae
2 changed files with 24 additions and 36 deletions
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@ -17,6 +17,9 @@
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#include <zephyr.h>
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#include <drivers/interrupt_controller/intc_esp32c3.h>
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#include <sw_isr_table.h>
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#include <riscv/interrupt.h>
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#define ESP32C3_INTC_DEFAULT_PRIO 15
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#include <logging/log.h>
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LOG_MODULE_REGISTER(intc_esp32c3, CONFIG_LOG_DEFAULT_LEVEL);
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@ -40,17 +43,6 @@ LOG_MODULE_REGISTER(intc_esp32c3, CONFIG_LOG_DEFAULT_LEVEL);
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static uint32_t esp_intr_enabled_mask[2] = {0, 0};
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static void esp_intr_default_isr(const void *arg)
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{
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ARG_UNUSED(arg);
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ulong_t mcause;
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__asm__ volatile("csrr %0, mcause" : "=r" (mcause));
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mcause &= SOC_MCAUSE_EXP_MASK;
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INTC_LOG("Spurious interrupt, mcause: %ld, source %d", mcause, soc_intr_get_next_source());
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}
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static uint32_t esp_intr_find_irq_for_source(uint32_t source)
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{
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/* in general case, each 2 sources goes routed to
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@ -80,15 +72,7 @@ void esp_intr_initialize(void)
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}
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for (int i = 0; i < ETS_MAX_INTR_SOURCE; i++) {
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esp_rom_intr_matrix_set(0,
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i,
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ESP32C3_INTC_DISABLED_SLOT);
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irq_connect_dynamic(i,
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ESP32C3_INTC_DEFAULT_PRIORITY,
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esp_intr_default_isr,
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NULL,
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0);
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esp_rom_intr_matrix_set(0, i, ESP32C3_INTC_DISABLED_SLOT);
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}
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/* set global esp32c3's INTC masking level */
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@ -113,9 +97,6 @@ int esp_intr_alloc(int source,
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}
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uint32_t key = irq_lock();
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uint32_t irq = esp_intr_find_irq_for_source(source);
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esp_rom_intr_matrix_set(0, source, irq);
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irq_connect_dynamic(source,
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ESP32C3_INTC_DEFAULT_PRIORITY,
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@ -133,7 +114,7 @@ int esp_intr_alloc(int source,
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esp_intr_enabled_mask[0], esp_intr_enabled_mask[1]);
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irq_unlock(key);
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irq_enable(irq);
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irq_enable(source);
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return 0;
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}
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@ -146,7 +127,7 @@ int esp_intr_disable(int source)
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uint32_t key = irq_lock();
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esp_rom_intr_matrix_set(source,
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esp_rom_intr_matrix_set(0,
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source,
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ESP32C3_INTC_DISABLED_SLOT);
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@ -173,7 +154,6 @@ int esp_intr_enable(int source)
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uint32_t key = irq_lock();
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uint32_t irq = esp_intr_find_irq_for_source(source);
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irq_disable(irq);
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esp_rom_intr_matrix_set(0, source, irq);
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if (source < 32) {
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@ -185,7 +165,10 @@ int esp_intr_enable(int source)
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INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X",
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esp_intr_enabled_mask[0], esp_intr_enabled_mask[1]);
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irq_enable(irq);
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esprv_intc_int_set_priority(irq, ESP32C3_INTC_DEFAULT_PRIO);
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esprv_intc_int_set_type(irq, INTR_TYPE_LEVEL);
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esprv_intc_int_enable(1 << irq);
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irq_unlock(key);
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return 0;
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@ -21,27 +21,32 @@
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#include <toolchain/gcc.h>
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#include <soc.h>
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#define ESP32C3_INTC_DEFAULT_PRIO 15
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#define ESP32C3_INTSTATUS_SLOT1_THRESHOLD 32
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void arch_irq_enable(unsigned int irq)
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{
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uint32_t key = irq_lock();
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esprv_intc_int_set_priority(irq, ESP32C3_INTC_DEFAULT_PRIO);
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esprv_intc_int_set_type(irq, INTR_TYPE_LEVEL);
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esprv_intc_int_enable(1 << irq);
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irq_unlock(key);
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esp_intr_enable(irq);
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}
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void arch_irq_disable(unsigned int irq)
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{
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esprv_intc_int_disable(1 << irq);
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esp_intr_disable(irq);
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}
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int arch_irq_is_enabled(unsigned int irq)
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{
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return (REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG) & (1 << irq));
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bool res = false;
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uint32_t key = irq_lock();
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if (irq < 32) {
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res = esp_intr_get_enabled_intmask(0) & BIT(irq);
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} else {
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res = esp_intr_get_enabled_intmask(1) & BIT(irq - 32);
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}
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irq_unlock(key);
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return res;
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}
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uint32_t soc_intr_get_next_source(void)
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