ITE: drivers/peci: Add PECI driver module of ITE IT8xxx2
Added the PECI driver tested with the samples/drivers/peci. Signed-off-by: BJ Chen <bj.chen@ite.com.tw>
This commit is contained in:
parent
dcddfb567f
commit
59cd9fd551
11 changed files with 455 additions and 31 deletions
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@ -15,6 +15,7 @@
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aliases {
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i2c-0 = &i2c0;
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peci-0 = &peci0;
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};
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chosen {
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@ -3,4 +3,5 @@
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_PECI_XEC peci_mchp_xec.c)
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zephyr_library_sources_ifdef(CONFIG_PECI_ITE_IT8XXX2 peci_ite_it8xxx2.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE peci_handlers.c)
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@ -11,6 +11,7 @@ menuconfig PECI
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if PECI
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source "drivers/peci/Kconfig.xec"
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source "drivers/peci/Kconfig.it8xxx2"
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module = PECI
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module-str = peci
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10
drivers/peci/Kconfig.it8xxx2
Normal file
10
drivers/peci/Kconfig.it8xxx2
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@ -0,0 +1,10 @@
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# ITE IT8XXX2 PECI configuration options
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# Copyright (c) 2022 ITE Tech. Inc.
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# SPDX-License-Identifier: Apache-2.0
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config PECI_ITE_IT8XXX2
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bool "ITE IT8XXX2 PECI driver"
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depends on SOC_IT8XXX2
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help
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Enable the ITE IT8XXX2 PECI IO driver.
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355
drivers/peci/peci_ite_it8xxx2.c
Normal file
355
drivers/peci/peci_ite_it8xxx2.c
Normal file
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@ -0,0 +1,355 @@
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/*
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* Copyright (c) 2022 ITE Corporation. All Rights Reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ite_peci_it8xxx2
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#include <drivers/gpio.h>
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#include <drivers/pinmux.h>
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#include <drivers/peci.h>
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#include <kernel.h>
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#include <errno.h>
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#include <device.h>
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#include <drivers/peci.h>
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#include <soc.h>
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#include <soc_dt.h>
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#include <logging/log.h>
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#include <sys/util.h>
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LOG_MODULE_REGISTER(peci_ite_it8xxx2, CONFIG_PECI_LOG_LEVEL);
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BUILD_ASSERT(IS_ENABLED(CONFIG_PECI_INTERRUPT_DRIVEN),
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"Please enable the option CONFIG_PECI_INTERRUPT_DRIVEN");
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/*
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* This driver is single-instance. If the devicetree contains multiple
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* instances, this will fail and the driver needs to be revisited.
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*/
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BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1,
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"Unsupported PECI Instance");
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/* The following constants decribes the bitrate of it8xxx2 PECI,
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* for the frequency are 2000KHz, 1000KHz, and 1600KHz. (Unit: KHz)
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*/
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#define PECI_IT8XXX2_BITRATE_2MHZ 2000
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#define PECI_IT8XXX2_BITRATE_1MHZ 1000
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#define PECI_IT8XXX2_BITRATE_1P6MHZ 1600
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/* The following masks are designed for the PECI bitrate settings,
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* for the bits[7:3] are not related to this features.
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*/
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#define PECI_IT8XXX2_BITRATE_BITS_MASK 0x07
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#define PECI_IT8XXX2_BITRATE_2MHZ_BITS 0x00
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#define PECI_IT8XXX2_BITRATE_1MHZ_BITS 0x01
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#define PECI_IT8XXX2_BITRATE_1P6MHZ_BITS 0x04
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/* The Transaction Timeout */
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#define PECI_TIMEOUT_MS 30
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/* PECI interface 0 */
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#define PECI0 0
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/* HOSTAR (F02C00h) */
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#define HOBY BIT(0)
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#define FINISH BIT(1)
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#define RD_FCS_ERR BIT(2)
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#define WR_FCS_ERR BIT(3)
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#define EXTERR BIT(5)
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#define BUS_ER BIT(6)
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#define TEMPERR BIT(7)
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#define HOSTAR_RST_ANYBIT \
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(TEMPERR|BUS_ER|EXTERR|WR_FCS_ERR|RD_FCS_ERR|FINISH)
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/* HOCTLR (F02C01h) */
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#define START BIT(0)
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#define AWFCS_EN BIT(1)
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#define CONTROL BIT(2)
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#define PECIHEN BIT(3)
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#define FCSERR_ABT BIT(4)
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#define FIFOCLR BIT(5)
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/*
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* TODO: The Voltage Configuration
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* Related DTSi and registers settings should be fulfilled
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* in the future.
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*/
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/* PADCTLR (F02C0Eh) */
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#define PECI_DVIE 0x04
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enum peci_vtts {
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HOVTTS0P85V = 0x00,
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HOVTTS0P90V = 0x01,
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HOVTTS0P95V = 0x02,
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HOVTTS1P00V = 0x03,
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HOVTTS1P05V = 0x08,
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HOVTTS1P10V = 0x09,
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HOVTTS1P15V = 0x0A,
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HOVTTS1P20V = 0x0B,
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HOVTTS1P25V = 0x10,
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};
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/* The following definitions are inclusive of the config/data
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* and related properties of the PECI device.
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*/
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struct peci_alts_cfg {
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const struct device *pinctrls;
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uint8_t pin;
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uint8_t alt_fun;
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};
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struct peci_it8xxx2_config {
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uintptr_t base_addr;
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uint8_t irq_no;
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const struct peci_alts_cfg *alts_list;
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};
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struct peci_it8xxx2_data {
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struct peci_msg *msgs;
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struct k_sem device_sync_sem;
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uint32_t bitrate;
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};
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static const struct peci_alts_cfg
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peci_alt_inst[DT_INST_NUM_PINCTRLS_BY_IDX(0, 0)] =
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IT8XXX2_DT_ALT_ITEMS_LIST(0);
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static const struct peci_it8xxx2_config peci_it8xxx2_config0 = {
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.base_addr = DT_INST_REG_ADDR(0),
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.irq_no = DT_INST_IRQN(0),
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.alts_list = peci_alt_inst,
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};
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static struct peci_it8xxx2_data peci_it8xxx2_data0;
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/* ITE IT8XXX2 PECI Functions */
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static void peci_it8xxx2_init_vtts(struct peci_it8xxx2_regs *reg_base,
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enum peci_vtts vol_opt)
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{
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reg_base->PADCTLR = (reg_base->PADCTLR & PECI_DVIE) | vol_opt;
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}
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static void peci_it8xxx2_rst_status(struct peci_it8xxx2_regs *reg_base)
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{
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reg_base->HOSTAR = HOSTAR_RST_ANYBIT;
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}
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static int peci_it8xxx2_check_host_busy(struct peci_it8xxx2_regs *reg_base)
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{
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return (reg_base->HOSTAR & HOBY) ? (-EBUSY) : 0;
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}
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static int peci_it8xxx2_check_host_finish(const struct device *dev)
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{
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struct peci_it8xxx2_data *data = dev->data;
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const struct peci_it8xxx2_config *config = dev->config;
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struct peci_it8xxx2_regs *const peci_regs =
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(struct peci_it8xxx2_regs *)config->base_addr;
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int ret = k_sem_take(&data->device_sync_sem, K_MSEC(PECI_TIMEOUT_MS));
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if (ret == -EAGAIN) {
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LOG_ERR("%s: Timeout", __func__);
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return -ETIMEDOUT;
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}
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if (peci_regs->HOSTAR != FINISH) {
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LOG_ERR("[PECI] Error: HOSTAR=0x%02X\r\n", peci_regs->HOSTAR);
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return -EIO;
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}
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return 0;
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}
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static int peci_it8xxx2_configure(const struct device *dev, uint32_t bitrate)
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{
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struct peci_it8xxx2_data *data = dev->data;
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const struct peci_it8xxx2_config *config = dev->config;
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struct peci_it8xxx2_regs *const peci_regs =
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(struct peci_it8xxx2_regs *)config->base_addr;
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uint8_t hoctl2r_to_write;
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data->bitrate = bitrate;
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hoctl2r_to_write =
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(peci_regs->HOCTL2R) & (~(PECI_IT8XXX2_BITRATE_BITS_MASK));
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switch (bitrate) {
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case PECI_IT8XXX2_BITRATE_2MHZ:
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break;
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case PECI_IT8XXX2_BITRATE_1MHZ:
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hoctl2r_to_write |= PECI_IT8XXX2_BITRATE_1MHZ_BITS;
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break;
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case PECI_IT8XXX2_BITRATE_1P6MHZ:
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hoctl2r_to_write |= PECI_IT8XXX2_BITRATE_1P6MHZ_BITS;
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break;
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default:
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LOG_ERR("[PECI] Error: Specified Bitrate Not Supported\r\n");
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hoctl2r_to_write |= PECI_IT8XXX2_BITRATE_1MHZ_BITS;
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data->bitrate = PECI_IT8XXX2_BITRATE_1MHZ;
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peci_regs->HOCTL2R = hoctl2r_to_write;
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return -ENOTSUP;
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}
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peci_regs->HOCTL2R = hoctl2r_to_write;
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return 0;
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}
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static int peci_it8xxx2_enable(const struct device *dev)
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{
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const struct peci_it8xxx2_config *config = dev->config;
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struct peci_it8xxx2_regs *const peci_regs =
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(struct peci_it8xxx2_regs *)config->base_addr;
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peci_regs->HOCTLR |= (FIFOCLR|FCSERR_ABT|PECIHEN|CONTROL);
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return 0;
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}
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static int peci_it8xxx2_disable(const struct device *dev)
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{
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const struct peci_it8xxx2_config *config = dev->config;
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struct peci_it8xxx2_regs *const peci_regs =
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(struct peci_it8xxx2_regs *)config->base_addr;
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peci_regs->HOCTLR &= ~(PECIHEN);
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return 0;
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}
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static void peci_it8xxx2_rst_module(const struct device *dev)
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{
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const struct peci_it8xxx2_config *config = dev->config;
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struct peci_it8xxx2_regs *const peci_regs =
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(struct peci_it8xxx2_regs *)config->base_addr;
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LOG_ERR("[PECI] Module Reset for Status Error.\r\n");
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/* Reset IT8XXX2 PECI Module Thoroughly */
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IT83XX_GCTRL_RSTC4 |= RPECI;
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/*
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* Due to the fact that we've checked if the peci_enable()
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* called before calling the peci_transfer(), so the peci
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* were definitely enabled before the error occurred.
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* Here is the recovery mechanism for recovering the PECI
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* bus when the errors occur.
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*/
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peci_regs->PADCTLR |= PECI_DVIE;
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peci_it8xxx2_init_vtts(peci_regs, HOVTTS0P95V);
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peci_it8xxx2_configure(dev, PECI_IT8XXX2_BITRATE_1MHZ);
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peci_it8xxx2_enable(dev);
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LOG_ERR("[PECI] Reinitialization Finished.\r\n");
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}
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static int peci_it8xxx2_transfer(const struct device *dev, struct peci_msg *msg)
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{
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const struct peci_it8xxx2_config *config = dev->config;
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struct peci_it8xxx2_regs *const peci_regs =
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(struct peci_it8xxx2_regs *)config->base_addr;
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struct peci_buf *peci_rx_buf = &msg->rx_buffer;
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struct peci_buf *peci_tx_buf = &msg->tx_buffer;
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int cnt, ret_code;
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ret_code = 0;
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if (!(peci_regs->HOCTLR & PECIHEN)) {
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LOG_ERR("[PECI] Please call the peci_enable() first.\r\n");
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return -ECONNREFUSED;
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}
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if (peci_it8xxx2_check_host_busy(peci_regs) != 0) {
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return -EBUSY;
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}
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peci_regs->HOTRADDR = msg->addr;
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peci_regs->HOWRLR = peci_tx_buf->len;
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peci_regs->HORDLR = peci_rx_buf->len;
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peci_regs->HOCMDR = msg->cmd_code;
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if (msg->cmd_code != PECI_CMD_PING) {
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for (cnt = 0; cnt < (peci_tx_buf->len - 1); cnt++) {
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peci_regs->HOWRDR = peci_tx_buf->buf[cnt];
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}
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}
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/* Host Available */
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irq_enable(config->irq_no);
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peci_regs->HOCTLR |= START;
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ret_code = peci_it8xxx2_check_host_finish(dev);
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if (!ret_code) {
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/* Host Transactions Finished, Fetch Data from the regs */
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if (peci_rx_buf->len) {
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for (cnt = 0; cnt < (peci_rx_buf->len); cnt++) {
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peci_rx_buf->buf[cnt] = peci_regs->HORDDR;
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}
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}
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peci_it8xxx2_rst_status(peci_regs);
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} else {
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/* Host Transactions Failure */
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peci_it8xxx2_rst_module(dev);
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}
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return (ret_code);
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}
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static void peci_it8xxx2_isr(const struct device *dev)
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{
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struct peci_it8xxx2_data *data = dev->data;
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const struct peci_it8xxx2_config *config = dev->config;
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irq_disable(config->irq_no);
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k_sem_give(&data->device_sync_sem);
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}
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static const struct peci_driver_api peci_it8xxx2_driver_api = {
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.config = peci_it8xxx2_configure,
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.enable = peci_it8xxx2_enable,
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.disable = peci_it8xxx2_disable,
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.transfer = peci_it8xxx2_transfer,
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};
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static int peci_it8xxx2_init(const struct device *dev)
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{
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struct peci_it8xxx2_data *data = dev->data;
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const struct peci_it8xxx2_config *config = dev->config;
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struct peci_it8xxx2_regs *const peci_regs =
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(struct peci_it8xxx2_regs *)config->base_addr;
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/* Initialize Semaphore */
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k_sem_init(&data->device_sync_sem, 0, 1);
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/* Configure the GPF6 to Alternative Function 3: PECI */
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pinmux_pin_set(config->alts_list[PECI0].pinctrls,
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config->alts_list[PECI0].pin,
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config->alts_list[PECI0].alt_fun);
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peci_regs->PADCTLR |= PECI_DVIE;
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peci_it8xxx2_init_vtts(peci_regs, HOVTTS0P95V);
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peci_it8xxx2_configure(dev, PECI_IT8XXX2_BITRATE_1MHZ);
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/* Interrupt Assignment */
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IRQ_CONNECT(DT_INST_IRQN(0),
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0,
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peci_it8xxx2_isr,
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DEVICE_DT_INST_GET(0),
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0);
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return 0;
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}
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DEVICE_DT_INST_DEFINE(0,
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&peci_it8xxx2_init,
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NULL,
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&peci_it8xxx2_data0,
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&peci_it8xxx2_config0,
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POST_KERNEL, CONFIG_PECI_INIT_PRIORITY,
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&peci_it8xxx2_driver_api);
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14
dts/bindings/peci/ite,it8xxx2-peci.yaml
Normal file
14
dts/bindings/peci/ite,it8xxx2-peci.yaml
Normal file
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# Copyright (c) 2022 ITE Corporation. All Rights Reserved.
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# SPDX-License-Identifier: Apache-2.0
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description: ITE it8xxx2 PECI
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compatible: "ite,peci-it8xxx2"
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include: peci.yaml
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properties:
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pinctrl-0:
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type: phandles
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required: true
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description: Configuration of the PECI pin which is mapped to the GPIO
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@ -134,6 +134,11 @@
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pinctrls = <&pinmuxm 5 IT8XXX2_PINMUX_FUNC_1>;
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};
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/* PECI alternate function */
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pinctrl_peci: peci {
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pinctrls = <&pinmuxf 6 IT8XXX2_PINMUX_FUNC_3>;
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};
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/* Keyboard alternate function */
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pinctrl_kso16: kso16 {
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pinctrls = <&pinmuxc 3 IT8XXX2_PINMUX_FUNC_1>;
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label = "GCTRL";
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};
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peci0: peci@f02c00 {
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compatible = "ite,peci-it8xxx2";
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reg = <0x00f02c00 15>;
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label = "PECI_0";
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#address-cells=<1>;
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#size-cells = <0>;
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interrupt-parent = <&intc>;
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interrupts = <160 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&pinctrl_peci>;
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};
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kscan0: kscan@f01d00 {
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compatible = "ite,it8xxx2-kscan";
|
||||
reg = <0x00f01d00 0x29
|
||||
|
|
|
@ -78,6 +78,23 @@ IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_P80HDR, 0x51);
|
|||
IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_H2ROFSR, 0x53);
|
||||
IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_ECHIPID2, 0x86);
|
||||
|
||||
/* PECI register structure check */
|
||||
IT8XXX2_REG_SIZE_CHECK(peci_it8xxx2_regs, 0x0F);
|
||||
IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, HOSTAR, 0x00);
|
||||
IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, HOCTLR, 0x01);
|
||||
IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, HOCMDR, 0x02);
|
||||
IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, HOTRADDR, 0x03);
|
||||
IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, HOWRLR, 0x04);
|
||||
IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, HORDLR, 0x05);
|
||||
IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, HOWRDR, 0x06);
|
||||
IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, HORDDR, 0x07);
|
||||
IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, HOCTL2R, 0x08);
|
||||
IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, RWFCSV, 0x09);
|
||||
IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, RRFCSV, 0x0A);
|
||||
IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, WFCSV, 0x0B);
|
||||
IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, RFCSV, 0x0C);
|
||||
IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, AWFCSV, 0x0D);
|
||||
IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, PADCTLR, 0x0E);
|
||||
/* KSCAN register structure check */
|
||||
IT8XXX2_REG_SIZE_CHECK(kscan_it8xxx2_regs, 0x0F);
|
||||
IT8XXX2_REG_OFFSET_CHECK(kscan_it8xxx2_regs, KBS_KSOL, 0x00);
|
||||
|
|
|
@ -1372,39 +1372,43 @@ enum ext_timer_idx {
|
|||
#define TMRCE ECREG(EC_REG_BASE_ADDR + 0x290B)
|
||||
#define TMEIE ECREG(EC_REG_BASE_ADDR + 0x290C)
|
||||
|
||||
/**
|
||||
*
|
||||
/*
|
||||
* (2Cxxh) Platform Environment Control Interface (PECI)
|
||||
*
|
||||
*/
|
||||
#define HOSTAR ECREG(EC_REG_BASE_ADDR + 0x2C00)
|
||||
#define TEMPERR BIT(7)
|
||||
#define BUSERR BIT(6)
|
||||
#define EXTERR BIT(5)
|
||||
#define WR_FCS_ERR BIT(3)
|
||||
#define RD_FCS_ERR BIT(2)
|
||||
#define FINISH BIT(1)
|
||||
#define HOBY BIT(0)
|
||||
#define HOCTLR ECREG(EC_REG_BASE_ADDR + 0x2C01)
|
||||
#define FIFOCLR BIT(5)
|
||||
#define FCSERR_ABT BIT(4)
|
||||
#define PECIHEN BIT(3)
|
||||
#define CONCTRL BIT(2)
|
||||
#define AWFCS_EN BIT(1)
|
||||
#define PECISTART BIT(0)
|
||||
#define HOCMDR ECREG(EC_REG_BASE_ADDR + 0x2C02)
|
||||
#define HOTRADDR ECREG(EC_REG_BASE_ADDR + 0x2C03)
|
||||
#define HOWRLR ECREG(EC_REG_BASE_ADDR + 0x2C04)
|
||||
#define HORDLR ECREG(EC_REG_BASE_ADDR + 0x2C05)
|
||||
#define HOWRDR ECREG(EC_REG_BASE_ADDR + 0x2C06)
|
||||
#define HORDDR ECREG(EC_REG_BASE_ADDR + 0x2C07)
|
||||
#define HOCTL2R ECREG(EC_REG_BASE_ADDR + 0x2C08)
|
||||
#define RWFCSV ECREG(EC_REG_BASE_ADDR + 0x2C09)
|
||||
#define RRFCSV ECREG(EC_REG_BASE_ADDR + 0x2C0A)
|
||||
#define WFCSV ECREG(EC_REG_BASE_ADDR + 0x2C0B)
|
||||
#define RFCSV ECREG(EC_REG_BASE_ADDR + 0x2C0C)
|
||||
#define AWFCSV ECREG(EC_REG_BASE_ADDR + 0x2C0D)
|
||||
#define PADCTLR ECREG(EC_REG_BASE_ADDR + 0x2C0E)
|
||||
#ifndef __ASSEMBLER__
|
||||
struct peci_it8xxx2_regs {
|
||||
/* 0x00: Host Status */
|
||||
volatile uint8_t HOSTAR;
|
||||
/* 0x01: Host Control */
|
||||
volatile uint8_t HOCTLR;
|
||||
/* 0x02: Host Command */
|
||||
volatile uint8_t HOCMDR;
|
||||
/* 0x03: Host Target Address */
|
||||
volatile uint8_t HOTRADDR;
|
||||
/* 0x04: Host Write Length */
|
||||
volatile uint8_t HOWRLR;
|
||||
/* 0x05: Host Read Length */
|
||||
volatile uint8_t HORDLR;
|
||||
/* 0x06: Host Write Data */
|
||||
volatile uint8_t HOWRDR;
|
||||
/* 0x07: Host Read Data */
|
||||
volatile uint8_t HORDDR;
|
||||
/* 0x08: Host Control 2 */
|
||||
volatile uint8_t HOCTL2R;
|
||||
/* 0x09: Received Write FCS value */
|
||||
volatile uint8_t RWFCSV;
|
||||
/* 0x0A: Received Read FCS value */
|
||||
volatile uint8_t RRFCSV;
|
||||
/* 0x0B: Write FCS Value */
|
||||
volatile uint8_t WFCSV;
|
||||
/* 0x0C: Read FCS Value */
|
||||
volatile uint8_t RFCSV;
|
||||
/* 0x0D: Assured Write FCS Value */
|
||||
volatile uint8_t AWFCSV;
|
||||
/* 0x0E: Pad Control */
|
||||
volatile uint8_t PADCTLR;
|
||||
};
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
|
||||
/**
|
||||
*
|
||||
|
|
|
@ -76,6 +76,11 @@ config TACH_IT8XXX2
|
|||
default y
|
||||
depends on SENSOR
|
||||
|
||||
config PECI_ITE_IT8XXX2
|
||||
default y
|
||||
depends on PECI
|
||||
select PECI_INTERRUPT_DRIVEN
|
||||
|
||||
if ITE_IT8XXX2_INTC
|
||||
config NUM_IRQS
|
||||
default 185
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue