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boards: mimxrt1xxx: Added support for GPT hardware timer on RT1xxx

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Adds support for using GPT as the hardware timer source (as opposed to
systick) for all RT1xxx platforms. This requires moving the clock
frequency of these devices into a defconfig so it can be overridden by
the GPT clock frequency.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2021-10-14 09:45:59 -05:00 • committed by Christopher Friedt
commit b330f18a39
36 changed files with 126 additions and 36 deletions
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6
boards/arm/mimxrt1010_evk/doc/index.rst
View file

@ -78,6 +78,8 @@ features:
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| GPT | on-chip | gpt |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
``boards/arm/mimxrt1010_evk/mimxrt1010_evk_defconfig``
@ -120,8 +122,8 @@ The MIMXRT1010 SoC has five pairs of pinmux/gpio controllers.
System Clock
============
The MIMXRT1010 SoC is configured to use the 24 MHz external oscillator on the
board with the on-chip PLL to generate a 500 MHz core clock.
The MIMXRT1010 SoC is configured to use the 32 KHz low frequency oscillator on
the board as a source for the GPT timer to generate a system clock.
Serial Port
===========

7
boards/arm/mimxrt1010_evk/mimxrt1010_evk.dts
View file

@ -83,3 +83,10 @@ zephyr_udc0: &usb1 {
&edma0 {
status = "okay";
};
/* Enable GPT for use as a hardware timer. This disables Cortex Systick.
* to use systick, change this node from "gpt_hw_timer" to "systick"
*/
&gpt_hw_timer {
status = "okay";
};

2
boards/arm/mimxrt1010_evk/mimxrt1010_evk_defconfig
View file

@ -9,8 +9,6 @@ CONFIG_SOC_SERIES_IMX_RT=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_GPIO=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=500000000
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y

6
boards/arm/mimxrt1015_evk/doc/index.rst
View file

@ -78,6 +78,8 @@ features:
+-----------+------------+-------------------------------------+
| ADC | on-chip | ADC |
+-----------+------------+-------------------------------------+
| GPT | on-chip | gpt |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
``boards/arm/mimxrt1015_evk/mimxrt1015_evk_defconfig``
@ -124,8 +126,8 @@ The MIMXRT1015 SoC has five pairs of pinmux/gpio controllers.
System Clock
============
The MIMXRT1015 SoC is configured to use the 24 MHz external oscillator on the
board with the on-chip PLL to generate a 500 MHz core clock.
The MIMXRT1015 SoC is configured to use the 32 KHz low frequency oscillator on
the board as a source for the GPT timer to generate a system clock.
Serial Port
===========

7
boards/arm/mimxrt1015_evk/mimxrt1015_evk.dts
View file

@ -112,3 +112,10 @@ zephyr_udc0: &usb1 {
&edma0 {
status = "okay";
};
/* Enable GPT for use as a hardware timer. This disables Cortex Systick.
* to use systick, change this node from "gpt_hw_timer" to "systick"
*/
&gpt_hw_timer {
status = "okay";
};

2
boards/arm/mimxrt1015_evk/mimxrt1015_evk_defconfig
View file

@ -9,8 +9,6 @@ CONFIG_SOC_SERIES_IMX_RT=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_GPIO=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=500000000
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y

6
boards/arm/mimxrt1020_evk/doc/index.rst
View file

@ -92,6 +92,8 @@ features:
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| GPT | on-chip | gpt |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
``boards/arm/mimxrt1020_evk/mimxrt1020_evk_defconfig``
@ -174,8 +176,8 @@ The MIMXRT1020 SoC has five pairs of pinmux/gpio controllers.
System Clock
============
The MIMXRT1020 SoC is configured to use the 24 MHz external oscillator on the
board with the on-chip PLL to generate a 500 MHz core clock.
The MIMXRT1020 SoC is configured to use the 32 KHz low frequency oscillator on
the board as a source for the GPT timer to generate a system clock.
Serial Port
===========

7
boards/arm/mimxrt1020_evk/mimxrt1020_evk.dts
View file

@ -169,3 +169,10 @@ zephyr_udc0: &usb1 {
&edma0 {
status = "okay";
};
/* Enable GPT for use as a hardware timer. This disables Cortex Systick.
* to use systick, change this node from "gpt_hw_timer" to "systick"
*/
&gpt_hw_timer {
status = "okay";
};

2
boards/arm/mimxrt1020_evk/mimxrt1020_evk_defconfig
View file

@ -9,8 +9,6 @@ CONFIG_SOC_SERIES_IMX_RT=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_GPIO=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=500000000
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y

6
boards/arm/mimxrt1024_evk/doc/index.rst
View file

@ -99,6 +99,8 @@ features:
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| GPT | on-chip | gpt |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
``boards/arm/mimxrt1024_evk/mimxrt1024_evk_defconfig``
@ -161,8 +163,8 @@ The MIMXRT1024 SoC has five pairs of pinmux/gpio controllers.
System Clock
============
The MIMXRT1024 SoC is configured to use the 24 MHz external oscillator on the
board with the on-chip PLL to generate a 500 MHz core clock.
The MIMXRT1024 SoC is configured to use the 32 KHz low frequency oscillator on
the board as a source for the GPT timer to generate a system clock.
Serial Port
===========

7
boards/arm/mimxrt1024_evk/mimxrt1024_evk.dts
View file

@ -127,3 +127,10 @@
&adc1 {
status = "okay";
};
/* Enable GPT for use as a hardware timer. This disables Cortex Systick.
* to use systick, change this node from "gpt_hw_timer" to "systick"
*/
&gpt_hw_timer {
status = "okay";
};

2
boards/arm/mimxrt1024_evk/mimxrt1024_evk_defconfig
View file

@ -9,8 +9,6 @@ CONFIG_SOC_SERIES_IMX_RT=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_GPIO=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=500000000
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y

6
boards/arm/mimxrt1050_evk/doc/index.rst
View file

@ -118,6 +118,8 @@ features:
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| GPT | on-chip | gpt |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
@ -255,8 +257,8 @@ The MIMXRT1050 SoC has five pairs of pinmux/gpio controllers.
System Clock
============
The MIMXRT1050 SoC is configured to use the 24 MHz external oscillator on the
board with the on-chip PLL to generate a 600 MHz core clock.
The MIMXRT1050 SoC is configured to use the 32 KHz low frequency oscillator on
the board as a source for the GPT timer to generate a system clock.
Serial Port
===========

7
boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts
View file

@ -232,3 +232,10 @@ zephyr_udc0: &usb1 {
&edma0 {
status = "okay";
};
/* Enable GPT for use as a hardware timer. This disables Cortex Systick.
* to use systick, change this node from "gpt_hw_timer" to "systick"
*/
&gpt_hw_timer {
status = "okay";
};

2
boards/arm/mimxrt1050_evk/mimxrt1050_evk_defconfig
View file

@ -10,8 +10,6 @@ CONFIG_BOARD_MIMXRT1050_EVK=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_GPIO=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=600000000
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y

2
boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi_defconfig
View file

@ -10,8 +10,6 @@ CONFIG_BOARD_MIMXRT1050_EVK_QSPI=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_GPIO=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=600000000
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y

6
boards/arm/mimxrt1060_evk/doc/index.rst
View file

@ -123,6 +123,8 @@ features:
+-----------+------------+-------------------------------------+
| SAI | on-chip | i2s |
+-----------+------------+-------------------------------------+
| GPT | on-chip | gpt |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
``boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig``
@ -271,8 +273,8 @@ The MIMXRT1060 SoC has five pairs of pinmux/gpio controllers.
System Clock
============
The MIMXRT1060 SoC is configured to use the 24 MHz external oscillator on the
board with the on-chip PLL to generate a 600 MHz core clock.
The MIMXRT1060 SoC is configured to use the 32 KHz low frequency oscillator on
the board as a source for the GPT timer to generate a system clock.
Serial Port
===========

7
boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts
View file

@ -219,3 +219,10 @@ zephyr_udc0: &usb1 {
&sai1 {
status = "okay";
};
/* Enable GPT for use as a hardware timer. This disables Cortex Systick.
* to use systick, change this node from "gpt_hw_timer" to "systick"
*/
&gpt_hw_timer {
status = "okay";
};

2
boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig
View file

@ -10,8 +10,6 @@ CONFIG_BOARD_MIMXRT1060_EVK=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_GPIO=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=600000000
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y

2
boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash_defconfig
View file

@ -10,8 +10,6 @@ CONFIG_BOARD_MIMXRT1060_EVK_HYPERFLASH=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_GPIO=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=600000000
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y

6
boards/arm/mimxrt1160_evk/doc/index.rst
View file

@ -113,6 +113,8 @@ features:
+-----------+------------+-------------------------------------+
| DMA | on-chip | dma |
+-----------+------------+-------------------------------------+
| GPT | on-chip | gpt |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
``boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7_defconfig``
@ -162,8 +164,8 @@ The MIMXRT1160 SoC has six pairs of pinmux/gpio controllers.
System Clock
============
The MIMXRT1160 SoC is configured to use the 24 MHz external oscillator on the
board with the on-chip PLL to generate a 600 MHz core clock.
The MIMXRT1160 SoC is configured to use the 32 KHz low frequency oscillator on
the board as a source for the GPT timer to generate a system clock.
Serial Port
===========

7
boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.dts
View file

@ -84,3 +84,10 @@
};
};
};
/* Enable GPT for use as a hardware timer. This disables Cortex Systick.
* to use systick, change this node from "gpt_hw_timer" to "systick"
*/
&gpt_hw_timer {
status = "okay";
};

7
boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.dts
View file

@ -96,6 +96,13 @@
};
};
/* Enable GPT for use as a hardware timer. This disables Cortex Systick.
* to use systick, change this node from "gpt_hw_timer" to "systick"
*/
&gpt_hw_timer {
status = "okay";
};
&lpadc0 {
status = "okay";
};

6
boards/arm/mimxrt1170_evk/doc/index.rst
View file

@ -113,6 +113,8 @@ features:
+-----------+------------+-------------------------------------+
| DMA | on-chip | dma |
+-----------+------------+-------------------------------------+
| GPT | on-chip | gpt |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
``boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7_defconfig``
@ -162,8 +164,8 @@ The MIMXRT1170 SoC has six pairs of pinmux/gpio controllers.
System Clock
============
The MIMXRT1170 SoC is configured to use the 24 MHz external oscillator on the
board with the on-chip PLL to generate a 1 GHz core clock.
The MIMXRT1170 SoC is configured to use the 32 KHz low frequency oscillator on
the board as a source for the GPT timer to generate a system clock.
Serial Port
===========

7
boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4.dts
View file

@ -84,3 +84,10 @@
};
};
};
/* Enable GPT for use as a hardware timer. This disables Cortex Systick.
* to use systick, change this node from "gpt_hw_timer" to "systick"
*/
&gpt_hw_timer {
status = "okay";
};

2
boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4_defconfig
View file

@ -9,8 +9,6 @@ CONFIG_SOC_SERIES_IMX_RT=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_GPIO=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=400000000
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y

7
boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.dts
View file

@ -110,3 +110,10 @@
&edma0 {
status = "okay";
};
/* Enable GPT for use as a hardware timer. This disables Cortex Systick.
* to use systick, change this node from "gpt_hw_timer" to "systick"
*/
&gpt_hw_timer {
status = "okay";
};

2
boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7_defconfig
View file

@ -9,9 +9,7 @@ CONFIG_SOC_SERIES_IMX_RT=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_GPIO=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=996000000
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET=0x400

3
soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1010
View file

@ -30,4 +30,7 @@ config GPIO
config FLEXSPI_CONFIG_BLOCK_OFFSET
default 0x400
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 500000000 if CORTEX_M_SYSTICK
endif # SOC_MIMXRT1010

3
soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1015
View file

@ -23,4 +23,7 @@ config IPG_DIV
config GPIO
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 500000000 if CORTEX_M_SYSTICK
endif # SOC_MIMXRT1015

3
soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1021
View file

@ -23,4 +23,7 @@ config IPG_DIV
config GPIO
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 500000000 if CORTEX_M_SYSTICK
endif # SOC_MIMXRT1021

3
soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1024
View file

@ -23,4 +23,7 @@ config IPG_DIV
config GPIO
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 500000000 if CORTEX_M_SYSTICK
endif # SOC_MIMXRT1024

3
soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1052
View file

@ -23,4 +23,7 @@ config IPG_DIV
config GPIO
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 600000000 if CORTEX_M_SYSTICK
endif # SOC_MIMXRT1052

3
soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1062
View file

@ -23,4 +23,7 @@ config IPG_DIV
config GPIO
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 600000000 if CORTEX_M_SYSTICK
endif # SOC_MIMXRT1062

3
soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm4
View file

@ -14,4 +14,7 @@ config NUM_IRQS
config GPIO
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 400000000 if CORTEX_M_SYSTICK
endif # SOC_MIMXRT1170_CM4

3
soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm7
View file

@ -14,4 +14,7 @@ config NUM_IRQS
config GPIO
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 996000000 if CORTEX_M_SYSTICK
endif # SOC_MIMXRT1176_CM7