drivers/i2c: stm32: Use DT_NODELABEL_ macros
Make use of DT_NODELABEL macros to get device instances information to configure drivers I2C instances. This allows to remove I2C related lines in fixup.h files Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
parent
9580992b3e
commit
c01c74c020
14 changed files with 41 additions and 356 deletions
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@ -208,23 +208,23 @@ static int i2c_stm32_init(struct device *dev)
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*/
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switch ((u32_t)cfg->i2c) {
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#ifdef CONFIG_I2C_1
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case DT_I2C_1_BASE_ADDRESS:
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#if DT_HAS_NODE(DT_NODELABEL(i2c1))
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case DT_REG_ADDR(DT_NODELABEL(i2c1)):
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LL_RCC_SetI2CClockSource(LL_RCC_I2C1_CLKSOURCE_SYSCLK);
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break;
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#endif /* CONFIG_I2C_1 */
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#endif
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#if defined(CONFIG_SOC_SERIES_STM32F3X) && defined(CONFIG_I2C_2)
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case DT_I2C_2_BASE_ADDRESS:
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#if defined(CONFIG_SOC_SERIES_STM32F3X) && DT_HAS_NODE(DT_NODELABEL(i2c2))
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case DT_REG_ADDR(DT_NODELABEL(i2c2)):
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LL_RCC_SetI2CClockSource(LL_RCC_I2C2_CLKSOURCE_SYSCLK);
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break;
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#endif /* CONFIG_SOC_SERIES_STM32F3X && CONFIG_I2C_2 */
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#endif
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#ifdef CONFIG_I2C_3
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case DT_I2C_3_BASE_ADDRESS:
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#if DT_HAS_NODE(DT_NODELABEL(i2c3))
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case DT_REG_ADDR(DT_NODELABEL(i2c3)):
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LL_RCC_SetI2CClockSource(LL_RCC_I2C3_CLKSOURCE_SYSCLK);
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break;
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#endif /* CONFIG_I2C_3 */
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#endif
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}
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#endif /* CONFIG_SOC_SERIES_STM32F3X) || CONFIG_SOC_SERIES_STM32F0X */
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@ -246,26 +246,28 @@ static int i2c_stm32_init(struct device *dev)
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#ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
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#define STM32_I2C_IRQ_CONNECT_AND_ENABLE(name) \
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do { \
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IRQ_CONNECT(DT_##name##_COMBINED_IRQ, \
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DT_##name##_COMBINED_IRQ_PRI, \
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IRQ_CONNECT(DT_IRQN(DT_NODELABEL(name)), \
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DT_IRQ(DT_NODELABEL(name), priority), \
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stm32_i2c_combined_isr, \
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DEVICE_GET(i2c_stm32_##name), 0); \
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irq_enable(DT_##name##_COMBINED_IRQ); \
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irq_enable(DT_IRQN(DT_NODELABEL(name))); \
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} while (0)
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#else
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#define STM32_I2C_IRQ_CONNECT_AND_ENABLE(name) \
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do { \
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IRQ_CONNECT(DT_##name##_EVENT_IRQ, \
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DT_##name##_EVENT_IRQ_PRI, \
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IRQ_CONNECT(DT_IRQ_BY_NAME(DT_NODELABEL(name), event, irq),\
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DT_IRQ_BY_NAME(DT_NODELABEL(name), event, \
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priority),\
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stm32_i2c_event_isr, \
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DEVICE_GET(i2c_stm32_##name), 0); \
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irq_enable(DT_##name##_EVENT_IRQ); \
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irq_enable(DT_IRQ_BY_NAME(DT_NODELABEL(name), event, irq));\
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\
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IRQ_CONNECT(DT_##name##_ERROR_IRQ, \
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DT_##name##_ERROR_IRQ_PRI, \
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IRQ_CONNECT(DT_IRQ_BY_NAME(DT_NODELABEL(name), error, irq),\
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DT_IRQ_BY_NAME(DT_NODELABEL(name), error, \
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priority),\
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stm32_i2c_error_isr, \
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DEVICE_GET(i2c_stm32_##name), 0); \
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irq_enable(DT_##name##_ERROR_IRQ); \
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irq_enable(DT_IRQ_BY_NAME(DT_NODELABEL(name), error, irq));\
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} while (0)
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#endif /* CONFIG_I2C_STM32_COMBINED_INTERRUPT */
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@ -286,22 +288,22 @@ static void i2c_stm32_irq_config_func_##name(struct device *dev) \
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#endif /* CONFIG_I2C_STM32_INTERRUPT */
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#define STM32_I2C_INIT(name, n) \
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#define STM32_I2C_INIT(name) \
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STM32_I2C_IRQ_HANDLER_DECL(name); \
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\
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static const struct i2c_stm32_config i2c_stm32_cfg_##name = { \
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.i2c = (I2C_TypeDef *)DT_##name##_BASE_ADDRESS, \
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.i2c = (I2C_TypeDef *)DT_REG_ADDR(DT_NODELABEL(name)), \
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.pclken = { \
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.enr = DT_##name##_CLOCK_BITS, \
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.bus = DT_##name##_CLOCK_BUS, \
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.enr = DT_CLOCKS_CELL(DT_NODELABEL(name), bits), \
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.bus = DT_CLOCKS_CELL(DT_NODELABEL(name), bus), \
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}, \
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STM32_I2C_IRQ_HANDLER_FUNCTION(name) \
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.bitrate = DT_##name##_BITRATE, \
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.bitrate = DT_PROP(DT_NODELABEL(name), clock_frequency), \
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}; \
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\
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static struct i2c_stm32_data i2c_stm32_dev_data_##name; \
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\
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DEVICE_AND_API_INIT(i2c_stm32_##name, DT_LABEL(DT_NODELABEL(i2c##n)), \
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DEVICE_AND_API_INIT(i2c_stm32_##name, DT_LABEL(DT_NODELABEL(name)), \
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&i2c_stm32_init, &i2c_stm32_dev_data_##name, \
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&i2c_stm32_cfg_##name, \
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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@ -311,38 +313,22 @@ STM32_I2C_IRQ_HANDLER(name)
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/* I2C instances declaration */
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#ifdef CONFIG_I2C_1
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STM32_I2C_INIT(I2C_1, 1);
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#endif /* CONFIG_I2C_1 */
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#if DT_HAS_NODE(DT_NODELABEL(i2c1))
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STM32_I2C_INIT(i2c1);
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#endif
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#ifdef CONFIG_I2C_2
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STM32_I2C_INIT(I2C_2, 2);
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#endif /* CONFIG_I2C_2 */
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#if DT_HAS_NODE(DT_NODELABEL(i2c2))
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STM32_I2C_INIT(i2c2);
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#endif
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#ifdef CONFIG_I2C_3
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#if DT_HAS_NODE(DT_NODELABEL(i2c3))
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STM32_I2C_INIT(i2c3);
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#endif
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#ifndef I2C3_BASE
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#error "I2C_3 is not available on the platform that you selected"
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#endif /* I2C3_BASE */
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#if DT_HAS_NODE(DT_NODELABEL(i2c4))
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STM32_I2C_INIT(i2c4);
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#endif
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STM32_I2C_INIT(I2C_3, 3);
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#endif /* CONFIG_I2C_3 */
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#ifdef CONFIG_I2C_4
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#ifndef I2C4_BASE
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#error "I2C_4 is not available on the platform that you selected"
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#endif /* I2C4_BASE */
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STM32_I2C_INIT(I2C_4, 4);
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#endif /* CONFIG_I2C_4 */
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#ifdef CONFIG_I2C_5
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#ifndef I2C5_BASE
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#error "I2C_5 is not available on the platform that you selected"
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#endif /* I2C5_BASE */
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STM32_I2C_INIT(I2C_5, 5);
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#endif /* CONFIG_I2C_5 */
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#if DT_HAS_NODE(DT_NODELABEL(i2c5))
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STM32_I2C_INIT(i2c5);
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#endif
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@ -4,20 +4,6 @@
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
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#define DT_I2C_1_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED_PRIORITY
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#define DT_I2C_1_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED
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#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
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#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
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#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
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#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS
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#define DT_I2C_2_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED_PRIORITY
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#define DT_I2C_2_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED
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#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
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#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS
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#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS
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#define DT_CAN_1_BASE_ADDRESS DT_ST_STM32_CAN_40006400_BASE_ADDRESS
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#define DT_CAN_1_BUS_SPEED DT_ST_STM32_CAN_40006400_BUS_SPEED
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#define DT_CAN_1_NAME DT_ST_STM32_CAN_40006400_LABEL
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@ -4,24 +4,6 @@
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005400_BASE_ADDRESS
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#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT_PRIORITY
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#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR_PRIORITY
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#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT
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#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR
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#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V1_40005400_CLOCK_FREQUENCY
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#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V1_40005400_CLOCK_BITS
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#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V1_40005400_CLOCK_BUS
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#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005800_BASE_ADDRESS
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#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT_PRIORITY
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#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR_PRIORITY
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#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT
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#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR
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#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY
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#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V1_40005800_CLOCK_BITS
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#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V1_40005800_CLOCK_BUS
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
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#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012400_LABEL
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@ -4,33 +4,6 @@
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
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#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY
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#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY
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#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT
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#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR
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#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
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#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
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#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
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#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS
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#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY
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#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY
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#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT
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#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR
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#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
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#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS
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#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS
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#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40007800_BASE_ADDRESS
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#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40007800_IRQ_EVENT_PRIORITY
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#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40007800_IRQ_ERROR_PRIORITY
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#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40007800_IRQ_EVENT
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#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40007800_IRQ_ERROR
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#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40007800_CLOCK_FREQUENCY
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#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40007800_CLOCK_BITS
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#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40007800_CLOCK_BUS
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#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, st_stm32f3_flash_controller))
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#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005400_BASE_ADDRESS
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#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT_PRIORITY
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#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR_PRIORITY
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#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT
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#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR
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#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V1_40005400_CLOCK_FREQUENCY
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#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V1_40005400_CLOCK_BITS
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#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V1_40005400_CLOCK_BUS
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#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005800_BASE_ADDRESS
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#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT_PRIORITY
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#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR_PRIORITY
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#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT
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#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR
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#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY
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#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V1_40005800_CLOCK_BITS
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#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V1_40005800_CLOCK_BUS
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#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005C00_BASE_ADDRESS
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#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005C00_IRQ_EVENT_PRIORITY
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#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005C00_IRQ_ERROR_PRIORITY
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#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V1_40005C00_IRQ_EVENT
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#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V1_40005C00_IRQ_ERROR
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#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V1_40005C00_CLOCK_FREQUENCY
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#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V1_40005C00_CLOCK_BITS
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#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V1_40005C00_CLOCK_BUS
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#define DT_I2S_1_BASE_ADDRESS DT_ST_STM32_I2S_40013000_BASE_ADDRESS
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#define DT_I2S_1_IRQ_PRI DT_ST_STM32_I2S_40013000_IRQ_0_PRIORITY
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#define DT_I2S_1_NAME DT_ST_STM32_I2S_40013000_LABEL
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#define DT_NUM_MPU_REGIONS DT_ARM_ARMV7M_MPU_E000ED90_ARM_NUM_MPU_REGIONS
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#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
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#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY
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#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY
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#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT
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#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR
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#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
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#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
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#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
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|
||||
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS
|
||||
#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY
|
||||
#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY
|
||||
#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT
|
||||
#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR
|
||||
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
|
||||
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS
|
||||
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS
|
||||
|
||||
#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005C00_BASE_ADDRESS
|
||||
#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT_PRIORITY
|
||||
#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR_PRIORITY
|
||||
#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT
|
||||
#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR
|
||||
#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY
|
||||
#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BITS
|
||||
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BUS
|
||||
|
||||
#define DT_I2C_4_BASE_ADDRESS DT_ST_STM32_I2C_V2_40006000_BASE_ADDRESS
|
||||
#define DT_I2C_4_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40006000_IRQ_EVENT_PRIORITY
|
||||
#define DT_I2C_4_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40006000_IRQ_ERROR_PRIORITY
|
||||
#define DT_I2C_4_EVENT_IRQ DT_ST_STM32_I2C_V2_40006000_IRQ_EVENT
|
||||
#define DT_I2C_4_ERROR_IRQ DT_ST_STM32_I2C_V2_40006000_IRQ_ERROR
|
||||
#define DT_I2C_4_BITRATE DT_ST_STM32_I2C_V2_40006000_CLOCK_FREQUENCY
|
||||
#define DT_I2C_4_CLOCK_BITS DT_ST_STM32_I2C_V2_40006000_CLOCK_BITS
|
||||
#define DT_I2C_4_CLOCK_BUS DT_ST_STM32_I2C_V2_40006000_CLOCK_BUS
|
||||
|
||||
#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))
|
||||
|
||||
#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, st_stm32f7_flash_controller))
|
||||
|
|
|
@ -13,20 +13,6 @@
|
|||
#define DT_PWM_STM32_3_DEV_NAME DT_ST_STM32_PWM_40000400_PWM_LABEL
|
||||
#define DT_PWM_STM32_3_PRESCALER DT_ST_STM32_PWM_40000400_PWM_ST_PRESCALER
|
||||
|
||||
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
|
||||
#define DT_I2C_1_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED_PRIORITY
|
||||
#define DT_I2C_1_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED
|
||||
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
|
||||
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
|
||||
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
|
||||
|
||||
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS
|
||||
#define DT_I2C_2_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED_PRIORITY
|
||||
#define DT_I2C_2_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED
|
||||
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
|
||||
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS
|
||||
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS
|
||||
|
||||
#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
|
||||
|
||||
/* End of SoC Level DTS fixup file */
|
||||
|
|
|
@ -10,33 +10,6 @@
|
|||
|
||||
#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, st_stm32g4_flash_controller))
|
||||
|
||||
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
|
||||
#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY
|
||||
#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY
|
||||
#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT
|
||||
#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR
|
||||
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
|
||||
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
|
||||
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
|
||||
|
||||
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS
|
||||
#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY
|
||||
#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY
|
||||
#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT
|
||||
#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR
|
||||
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
|
||||
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS
|
||||
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS
|
||||
|
||||
#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40007800_BASE_ADDRESS
|
||||
#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40007800_IRQ_EVENT_PRIORITY
|
||||
#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40007800_IRQ_ERROR_PRIORITY
|
||||
#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40007800_IRQ_EVENT
|
||||
#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40007800_IRQ_ERROR
|
||||
#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40007800_CLOCK_FREQUENCY
|
||||
#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40007800_CLOCK_BITS
|
||||
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40007800_CLOCK_BUS
|
||||
|
||||
#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))
|
||||
|
||||
#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
|
||||
|
|
|
@ -12,40 +12,4 @@
|
|||
|
||||
#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))
|
||||
|
||||
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
|
||||
#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY
|
||||
#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY
|
||||
#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT
|
||||
#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR
|
||||
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
|
||||
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
|
||||
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
|
||||
|
||||
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS
|
||||
#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY
|
||||
#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY
|
||||
#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT
|
||||
#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR
|
||||
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
|
||||
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS
|
||||
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS
|
||||
|
||||
#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005C00_BASE_ADDRESS
|
||||
#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT_PRIORITY
|
||||
#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR_PRIORITY
|
||||
#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT
|
||||
#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR
|
||||
#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY
|
||||
#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BITS
|
||||
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BUS
|
||||
|
||||
#define DT_I2C_4_BASE_ADDRESS DT_ST_STM32_I2C_V2_58001C00_BASE_ADDRESS
|
||||
#define DT_I2C_4_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_58001C00_IRQ_EVENT_PRIORITY
|
||||
#define DT_I2C_4_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_58001C00_IRQ_ERROR_PRIORITY
|
||||
#define DT_I2C_4_EVENT_IRQ DT_ST_STM32_I2C_V2_58001C00_IRQ_EVENT
|
||||
#define DT_I2C_4_ERROR_IRQ DT_ST_STM32_I2C_V2_58001C00_IRQ_ERROR
|
||||
#define DT_I2C_4_BITRATE DT_ST_STM32_I2C_V2_58001C00_CLOCK_FREQUENCY
|
||||
#define DT_I2C_4_CLOCK_BITS DT_ST_STM32_I2C_V2_58001C00_CLOCK_BITS
|
||||
#define DT_I2C_4_CLOCK_BUS DT_ST_STM32_I2C_V2_58001C00_CLOCK_BUS
|
||||
|
||||
/* End of SoC Level DTS fixup file */
|
||||
|
|
|
@ -4,27 +4,6 @@
|
|||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
|
||||
#define DT_I2C_1_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED_PRIORITY
|
||||
#define DT_I2C_1_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED
|
||||
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
|
||||
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
|
||||
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
|
||||
|
||||
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS
|
||||
#define DT_I2C_2_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED_PRIORITY
|
||||
#define DT_I2C_2_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED
|
||||
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
|
||||
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS
|
||||
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS
|
||||
|
||||
#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40007800_BASE_ADDRESS
|
||||
#define DT_I2C_3_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40007800_IRQ_COMBINED_PRIORITY
|
||||
#define DT_I2C_3_COMBINED_IRQ DT_ST_STM32_I2C_V2_40007800_IRQ_COMBINED
|
||||
#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40007800_CLOCK_FREQUENCY
|
||||
#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40007800_CLOCK_BITS
|
||||
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40007800_CLOCK_BUS
|
||||
|
||||
#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
|
||||
|
||||
#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012400_LABEL
|
||||
|
|
|
@ -8,24 +8,6 @@
|
|||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005400_BASE_ADDRESS
|
||||
#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT_PRIORITY
|
||||
#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR_PRIORITY
|
||||
#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT
|
||||
#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR
|
||||
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V1_40005400_CLOCK_FREQUENCY
|
||||
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V1_40005400_CLOCK_BITS
|
||||
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V1_40005400_CLOCK_BUS
|
||||
|
||||
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005800_BASE_ADDRESS
|
||||
#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT_PRIORITY
|
||||
#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR_PRIORITY
|
||||
#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT
|
||||
#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR
|
||||
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY
|
||||
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V1_40005800_CLOCK_BITS
|
||||
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V1_40005800_CLOCK_BUS
|
||||
|
||||
#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
|
||||
|
||||
#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012400_LABEL
|
||||
|
|
|
@ -4,42 +4,6 @@
|
|||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
|
||||
#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY
|
||||
#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY
|
||||
#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT
|
||||
#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR
|
||||
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
|
||||
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
|
||||
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
|
||||
|
||||
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS
|
||||
#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY
|
||||
#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY
|
||||
#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT
|
||||
#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR
|
||||
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
|
||||
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS
|
||||
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS
|
||||
|
||||
#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005C00_BASE_ADDRESS
|
||||
#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT_PRIORITY
|
||||
#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR_PRIORITY
|
||||
#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT
|
||||
#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR
|
||||
#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY
|
||||
#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BITS
|
||||
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BUS
|
||||
|
||||
#define DT_I2C_4_BASE_ADDRESS DT_ST_STM32_I2C_V2_40008400_BASE_ADDRESS
|
||||
#define DT_I2C_4_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40008400_IRQ_EVENT_PRIORITY
|
||||
#define DT_I2C_4_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40008400_IRQ_ERROR_PRIORITY
|
||||
#define DT_I2C_4_EVENT_IRQ DT_ST_STM32_I2C_V2_40008400_IRQ_EVENT
|
||||
#define DT_I2C_4_ERROR_IRQ DT_ST_STM32_I2C_V2_40008400_IRQ_ERROR
|
||||
#define DT_I2C_4_BITRATE DT_ST_STM32_I2C_V2_40008400_CLOCK_FREQUENCY
|
||||
#define DT_I2C_4_CLOCK_BITS DT_ST_STM32_I2C_V2_40008400_CLOCK_BITS
|
||||
#define DT_I2C_4_CLOCK_BUS DT_ST_STM32_I2C_V2_40008400_CLOCK_BUS
|
||||
|
||||
#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))
|
||||
|
||||
#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, st_stm32l4_flash_controller))
|
||||
|
|
|
@ -8,13 +8,4 @@
|
|||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_I2C_5_BASE_ADDRESS DT_ST_STM32_I2C_V2_40015000_BASE_ADDRESS
|
||||
#define DT_I2C_5_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40015000_IRQ_EVENT_PRIORITY
|
||||
#define DT_I2C_5_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40015000_IRQ_ERROR_PRIORITY
|
||||
#define DT_I2C_5_EVENT_IRQ DT_ST_STM32_I2C_V2_40015000_IRQ_EVENT
|
||||
#define DT_I2C_5_ERROR_IRQ DT_ST_STM32_I2C_V2_40015000_IRQ_ERROR
|
||||
#define DT_I2C_5_BITRATE DT_ST_STM32_I2C_V2_40015000_CLOCK_FREQUENCY
|
||||
#define DT_I2C_5_CLOCK_BITS DT_ST_STM32_I2C_V2_40015000_CLOCK_BITS
|
||||
#define DT_I2C_5_CLOCK_BUS DT_ST_STM32_I2C_V2_40015000_CLOCK_BUS
|
||||
|
||||
/* End of SoC Level DTS fixup file */
|
||||
|
|
|
@ -12,24 +12,6 @@
|
|||
|
||||
#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, st_stm32wb_flash_controller))
|
||||
|
||||
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
|
||||
#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY
|
||||
#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY
|
||||
#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT
|
||||
#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR
|
||||
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
|
||||
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
|
||||
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
|
||||
|
||||
#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005C00_BASE_ADDRESS
|
||||
#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT_PRIORITY
|
||||
#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR_PRIORITY
|
||||
#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT
|
||||
#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR
|
||||
#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY
|
||||
#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BITS
|
||||
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BUS
|
||||
|
||||
#define DT_ADC_1_NAME DT_ST_STM32_ADC_50040000_LABEL
|
||||
|
||||
#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue