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drivers/i2c: stm32: Use DT_NODELABEL_ macros

Browse source 
Make use of DT_NODELABEL macros to get device instances
information to configure drivers I2C instances.
This allows to remove I2C related lines in fixup.h files

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2020-04-13 16:00:31 +02:00 • committed by Kumar Gala
commit c01c74c020
14 changed files with 41 additions and 356 deletions
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96
drivers/i2c/i2c_ll_stm32.c
View file

@ -208,23 +208,23 @@ static int i2c_stm32_init(struct device *dev)
*/
switch ((u32_t)cfg->i2c) {
#ifdef CONFIG_I2C_1
case DT_I2C_1_BASE_ADDRESS:
#if DT_HAS_NODE(DT_NODELABEL(i2c1))
case DT_REG_ADDR(DT_NODELABEL(i2c1)):
LL_RCC_SetI2CClockSource(LL_RCC_I2C1_CLKSOURCE_SYSCLK);
break;
#endif /* CONFIG_I2C_1 */
#endif
#if defined(CONFIG_SOC_SERIES_STM32F3X) && defined(CONFIG_I2C_2)
case DT_I2C_2_BASE_ADDRESS:
#if defined(CONFIG_SOC_SERIES_STM32F3X) && DT_HAS_NODE(DT_NODELABEL(i2c2))
case DT_REG_ADDR(DT_NODELABEL(i2c2)):
LL_RCC_SetI2CClockSource(LL_RCC_I2C2_CLKSOURCE_SYSCLK);
break;
#endif /* CONFIG_SOC_SERIES_STM32F3X && CONFIG_I2C_2 */
#endif
#ifdef CONFIG_I2C_3
case DT_I2C_3_BASE_ADDRESS:
#if DT_HAS_NODE(DT_NODELABEL(i2c3))
case DT_REG_ADDR(DT_NODELABEL(i2c3)):
LL_RCC_SetI2CClockSource(LL_RCC_I2C3_CLKSOURCE_SYSCLK);
break;
#endif /* CONFIG_I2C_3 */
#endif
}
#endif /* CONFIG_SOC_SERIES_STM32F3X) || CONFIG_SOC_SERIES_STM32F0X */
@ -246,26 +246,28 @@ static int i2c_stm32_init(struct device *dev)
#ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
#define STM32_I2C_IRQ_CONNECT_AND_ENABLE(name) \
do { \
IRQ_CONNECT(DT_##name##_COMBINED_IRQ, \
DT_##name##_COMBINED_IRQ_PRI, \
IRQ_CONNECT(DT_IRQN(DT_NODELABEL(name)), \
DT_IRQ(DT_NODELABEL(name), priority), \
stm32_i2c_combined_isr, \
DEVICE_GET(i2c_stm32_##name), 0); \
irq_enable(DT_##name##_COMBINED_IRQ); \
irq_enable(DT_IRQN(DT_NODELABEL(name))); \
} while (0)
#else
#define STM32_I2C_IRQ_CONNECT_AND_ENABLE(name) \
do { \
IRQ_CONNECT(DT_##name##_EVENT_IRQ, \
DT_##name##_EVENT_IRQ_PRI, \
IRQ_CONNECT(DT_IRQ_BY_NAME(DT_NODELABEL(name), event, irq),\
DT_IRQ_BY_NAME(DT_NODELABEL(name), event, \
priority),\
stm32_i2c_event_isr, \
DEVICE_GET(i2c_stm32_##name), 0); \
irq_enable(DT_##name##_EVENT_IRQ); \
irq_enable(DT_IRQ_BY_NAME(DT_NODELABEL(name), event, irq));\
\
IRQ_CONNECT(DT_##name##_ERROR_IRQ, \
DT_##name##_ERROR_IRQ_PRI, \
IRQ_CONNECT(DT_IRQ_BY_NAME(DT_NODELABEL(name), error, irq),\
DT_IRQ_BY_NAME(DT_NODELABEL(name), error, \
priority),\
stm32_i2c_error_isr, \
DEVICE_GET(i2c_stm32_##name), 0); \
irq_enable(DT_##name##_ERROR_IRQ); \
irq_enable(DT_IRQ_BY_NAME(DT_NODELABEL(name), error, irq));\
} while (0)
#endif /* CONFIG_I2C_STM32_COMBINED_INTERRUPT */
@ -286,22 +288,22 @@ static void i2c_stm32_irq_config_func_##name(struct device *dev) \
#endif /* CONFIG_I2C_STM32_INTERRUPT */
#define STM32_I2C_INIT(name, n) \
#define STM32_I2C_INIT(name) \
STM32_I2C_IRQ_HANDLER_DECL(name); \
\
static const struct i2c_stm32_config i2c_stm32_cfg_##name = { \
.i2c = (I2C_TypeDef *)DT_##name##_BASE_ADDRESS, \
.i2c = (I2C_TypeDef *)DT_REG_ADDR(DT_NODELABEL(name)), \
.pclken = { \
.enr = DT_##name##_CLOCK_BITS, \
.bus = DT_##name##_CLOCK_BUS, \
.enr = DT_CLOCKS_CELL(DT_NODELABEL(name), bits), \
.bus = DT_CLOCKS_CELL(DT_NODELABEL(name), bus), \
}, \
STM32_I2C_IRQ_HANDLER_FUNCTION(name) \
.bitrate = DT_##name##_BITRATE, \
.bitrate = DT_PROP(DT_NODELABEL(name), clock_frequency), \
}; \
\
static struct i2c_stm32_data i2c_stm32_dev_data_##name; \
\
DEVICE_AND_API_INIT(i2c_stm32_##name, DT_LABEL(DT_NODELABEL(i2c##n)), \
DEVICE_AND_API_INIT(i2c_stm32_##name, DT_LABEL(DT_NODELABEL(name)), \
&i2c_stm32_init, &i2c_stm32_dev_data_##name, \
&i2c_stm32_cfg_##name, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
@ -311,38 +313,22 @@ STM32_I2C_IRQ_HANDLER(name)
/* I2C instances declaration */
#ifdef CONFIG_I2C_1
STM32_I2C_INIT(I2C_1, 1);
#endif /* CONFIG_I2C_1 */
#if DT_HAS_NODE(DT_NODELABEL(i2c1))
STM32_I2C_INIT(i2c1);
#endif
#ifdef CONFIG_I2C_2
STM32_I2C_INIT(I2C_2, 2);
#endif /* CONFIG_I2C_2 */
#if DT_HAS_NODE(DT_NODELABEL(i2c2))
STM32_I2C_INIT(i2c2);
#endif
#ifdef CONFIG_I2C_3
#if DT_HAS_NODE(DT_NODELABEL(i2c3))
STM32_I2C_INIT(i2c3);
#endif
#ifndef I2C3_BASE
#error "I2C_3 is not available on the platform that you selected"
#endif /* I2C3_BASE */
#if DT_HAS_NODE(DT_NODELABEL(i2c4))
STM32_I2C_INIT(i2c4);
#endif
STM32_I2C_INIT(I2C_3, 3);
#endif /* CONFIG_I2C_3 */
#ifdef CONFIG_I2C_4
#ifndef I2C4_BASE
#error "I2C_4 is not available on the platform that you selected"
#endif /* I2C4_BASE */
STM32_I2C_INIT(I2C_4, 4);
#endif /* CONFIG_I2C_4 */
#ifdef CONFIG_I2C_5
#ifndef I2C5_BASE
#error "I2C_5 is not available on the platform that you selected"
#endif /* I2C5_BASE */
STM32_I2C_INIT(I2C_5, 5);
#endif /* CONFIG_I2C_5 */
#if DT_HAS_NODE(DT_NODELABEL(i2c5))
STM32_I2C_INIT(i2c5);
#endif

14
soc/arm/st_stm32/stm32f0/dts_fixup.h
View file

@ -4,20 +4,6 @@
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
#define DT_I2C_1_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED_PRIORITY
#define DT_I2C_1_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS
#define DT_I2C_2_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED_PRIORITY
#define DT_I2C_2_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS
#define DT_CAN_1_BASE_ADDRESS DT_ST_STM32_CAN_40006400_BASE_ADDRESS
#define DT_CAN_1_BUS_SPEED DT_ST_STM32_CAN_40006400_BUS_SPEED
#define DT_CAN_1_NAME DT_ST_STM32_CAN_40006400_LABEL

18
soc/arm/st_stm32/stm32f1/dts_fixup.h
View file

@ -4,24 +4,6 @@
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005400_BASE_ADDRESS
#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT_PRIORITY
#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR_PRIORITY
#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT
#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V1_40005400_CLOCK_FREQUENCY
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V1_40005400_CLOCK_BITS
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V1_40005400_CLOCK_BUS
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005800_BASE_ADDRESS
#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT_PRIORITY
#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR_PRIORITY
#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT
#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V1_40005800_CLOCK_BITS
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V1_40005800_CLOCK_BUS
#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012400_LABEL

27
soc/arm/st_stm32/stm32f3/dts_fixup.h
View file

@ -4,33 +4,6 @@
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY
#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY
#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT
#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS
#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY
#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY
#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT
#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS
#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40007800_BASE_ADDRESS
#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40007800_IRQ_EVENT_PRIORITY
#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40007800_IRQ_ERROR_PRIORITY
#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40007800_IRQ_EVENT
#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40007800_IRQ_ERROR
#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40007800_CLOCK_FREQUENCY
#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40007800_CLOCK_BITS
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40007800_CLOCK_BUS
#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, st_stm32f3_flash_controller))
#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))

27
soc/arm/st_stm32/stm32f4/dts_fixup.h
View file

@ -4,33 +4,6 @@
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005400_BASE_ADDRESS
#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT_PRIORITY
#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR_PRIORITY
#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT
#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V1_40005400_CLOCK_FREQUENCY
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V1_40005400_CLOCK_BITS
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V1_40005400_CLOCK_BUS
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005800_BASE_ADDRESS
#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT_PRIORITY
#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR_PRIORITY
#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT
#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V1_40005800_CLOCK_BITS
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V1_40005800_CLOCK_BUS
#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005C00_BASE_ADDRESS
#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005C00_IRQ_EVENT_PRIORITY
#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005C00_IRQ_ERROR_PRIORITY
#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V1_40005C00_IRQ_EVENT
#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V1_40005C00_IRQ_ERROR
#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V1_40005C00_CLOCK_FREQUENCY
#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V1_40005C00_CLOCK_BITS
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V1_40005C00_CLOCK_BUS
#define DT_I2S_1_BASE_ADDRESS DT_ST_STM32_I2S_40013000_BASE_ADDRESS
#define DT_I2S_1_IRQ_PRI DT_ST_STM32_I2S_40013000_IRQ_0_PRIORITY
#define DT_I2S_1_NAME DT_ST_STM32_I2S_40013000_LABEL

36
soc/arm/st_stm32/stm32f7/dts_fixup.h
View file

@ -6,42 +6,6 @@
#define DT_NUM_MPU_REGIONS DT_ARM_ARMV7M_MPU_E000ED90_ARM_NUM_MPU_REGIONS
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY
#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY
#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT
#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS
#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY
#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY
#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT
#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS
#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005C00_BASE_ADDRESS
#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT_PRIORITY
#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR_PRIORITY
#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT
#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR
#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY
#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BITS
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BUS
#define DT_I2C_4_BASE_ADDRESS DT_ST_STM32_I2C_V2_40006000_BASE_ADDRESS
#define DT_I2C_4_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40006000_IRQ_EVENT_PRIORITY
#define DT_I2C_4_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40006000_IRQ_ERROR_PRIORITY
#define DT_I2C_4_EVENT_IRQ DT_ST_STM32_I2C_V2_40006000_IRQ_EVENT
#define DT_I2C_4_ERROR_IRQ DT_ST_STM32_I2C_V2_40006000_IRQ_ERROR
#define DT_I2C_4_BITRATE DT_ST_STM32_I2C_V2_40006000_CLOCK_FREQUENCY
#define DT_I2C_4_CLOCK_BITS DT_ST_STM32_I2C_V2_40006000_CLOCK_BITS
#define DT_I2C_4_CLOCK_BUS DT_ST_STM32_I2C_V2_40006000_CLOCK_BUS
#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))
#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, st_stm32f7_flash_controller))

14
soc/arm/st_stm32/stm32g0/dts_fixup.h
View file

@ -13,20 +13,6 @@
#define DT_PWM_STM32_3_DEV_NAME DT_ST_STM32_PWM_40000400_PWM_LABEL
#define DT_PWM_STM32_3_PRESCALER DT_ST_STM32_PWM_40000400_PWM_ST_PRESCALER
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
#define DT_I2C_1_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED_PRIORITY
#define DT_I2C_1_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS
#define DT_I2C_2_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED_PRIORITY
#define DT_I2C_2_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS
#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
/* End of SoC Level DTS fixup file */

27
soc/arm/st_stm32/stm32g4/dts_fixup.h
View file

@ -10,33 +10,6 @@
#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, st_stm32g4_flash_controller))
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY
#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY
#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT
#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS
#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY
#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY
#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT
#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS
#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40007800_BASE_ADDRESS
#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40007800_IRQ_EVENT_PRIORITY
#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40007800_IRQ_ERROR_PRIORITY
#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40007800_IRQ_EVENT
#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40007800_IRQ_ERROR
#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40007800_CLOCK_FREQUENCY
#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40007800_CLOCK_BITS
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40007800_CLOCK_BUS
#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))
#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))

36
soc/arm/st_stm32/stm32h7/dts_fixup.h
View file

@ -12,40 +12,4 @@
#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY
#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY
#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT
#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS
#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY
#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY
#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT
#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS
#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005C00_BASE_ADDRESS
#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT_PRIORITY
#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR_PRIORITY
#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT
#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR
#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY
#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BITS
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BUS
#define DT_I2C_4_BASE_ADDRESS DT_ST_STM32_I2C_V2_58001C00_BASE_ADDRESS
#define DT_I2C_4_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_58001C00_IRQ_EVENT_PRIORITY
#define DT_I2C_4_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_58001C00_IRQ_ERROR_PRIORITY
#define DT_I2C_4_EVENT_IRQ DT_ST_STM32_I2C_V2_58001C00_IRQ_EVENT
#define DT_I2C_4_ERROR_IRQ DT_ST_STM32_I2C_V2_58001C00_IRQ_ERROR
#define DT_I2C_4_BITRATE DT_ST_STM32_I2C_V2_58001C00_CLOCK_FREQUENCY
#define DT_I2C_4_CLOCK_BITS DT_ST_STM32_I2C_V2_58001C00_CLOCK_BITS
#define DT_I2C_4_CLOCK_BUS DT_ST_STM32_I2C_V2_58001C00_CLOCK_BUS
/* End of SoC Level DTS fixup file */

21
soc/arm/st_stm32/stm32l0/dts_fixup.h
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@ -4,27 +4,6 @@
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
#define DT_I2C_1_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED_PRIORITY
#define DT_I2C_1_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS
#define DT_I2C_2_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED_PRIORITY
#define DT_I2C_2_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS
#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40007800_BASE_ADDRESS
#define DT_I2C_3_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40007800_IRQ_COMBINED_PRIORITY
#define DT_I2C_3_COMBINED_IRQ DT_ST_STM32_I2C_V2_40007800_IRQ_COMBINED
#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40007800_CLOCK_FREQUENCY
#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40007800_CLOCK_BITS
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40007800_CLOCK_BUS
#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012400_LABEL

18
soc/arm/st_stm32/stm32l1/dts_fixup.h
View file

@ -8,24 +8,6 @@
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005400_BASE_ADDRESS
#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT_PRIORITY
#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR_PRIORITY
#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT
#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V1_40005400_CLOCK_FREQUENCY
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V1_40005400_CLOCK_BITS
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V1_40005400_CLOCK_BUS
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005800_BASE_ADDRESS
#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT_PRIORITY
#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR_PRIORITY
#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT
#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V1_40005800_CLOCK_BITS
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V1_40005800_CLOCK_BUS
#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012400_LABEL

36
soc/arm/st_stm32/stm32l4/dts_fixup.h
View file

@ -4,42 +4,6 @@
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY
#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY
#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT
#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS
#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY
#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY
#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT
#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS
#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005C00_BASE_ADDRESS
#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT_PRIORITY
#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR_PRIORITY
#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT
#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR
#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY
#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BITS
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BUS
#define DT_I2C_4_BASE_ADDRESS DT_ST_STM32_I2C_V2_40008400_BASE_ADDRESS
#define DT_I2C_4_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40008400_IRQ_EVENT_PRIORITY
#define DT_I2C_4_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40008400_IRQ_ERROR_PRIORITY
#define DT_I2C_4_EVENT_IRQ DT_ST_STM32_I2C_V2_40008400_IRQ_EVENT
#define DT_I2C_4_ERROR_IRQ DT_ST_STM32_I2C_V2_40008400_IRQ_ERROR
#define DT_I2C_4_BITRATE DT_ST_STM32_I2C_V2_40008400_CLOCK_FREQUENCY
#define DT_I2C_4_CLOCK_BITS DT_ST_STM32_I2C_V2_40008400_CLOCK_BITS
#define DT_I2C_4_CLOCK_BUS DT_ST_STM32_I2C_V2_40008400_CLOCK_BUS
#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))
#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, st_stm32l4_flash_controller))

9
soc/arm/st_stm32/stm32mp1/dts_fixup.h
View file

@ -8,13 +8,4 @@
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define DT_I2C_5_BASE_ADDRESS DT_ST_STM32_I2C_V2_40015000_BASE_ADDRESS
#define DT_I2C_5_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40015000_IRQ_EVENT_PRIORITY
#define DT_I2C_5_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40015000_IRQ_ERROR_PRIORITY
#define DT_I2C_5_EVENT_IRQ DT_ST_STM32_I2C_V2_40015000_IRQ_EVENT
#define DT_I2C_5_ERROR_IRQ DT_ST_STM32_I2C_V2_40015000_IRQ_ERROR
#define DT_I2C_5_BITRATE DT_ST_STM32_I2C_V2_40015000_CLOCK_FREQUENCY
#define DT_I2C_5_CLOCK_BITS DT_ST_STM32_I2C_V2_40015000_CLOCK_BITS
#define DT_I2C_5_CLOCK_BUS DT_ST_STM32_I2C_V2_40015000_CLOCK_BUS
/* End of SoC Level DTS fixup file */

18
soc/arm/st_stm32/stm32wb/dts_fixup.h
View file

@ -12,24 +12,6 @@
#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, st_stm32wb_flash_controller))
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY
#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY
#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT
#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005C00_BASE_ADDRESS
#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT_PRIORITY
#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR_PRIORITY
#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT
#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR
#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY
#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BITS
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BUS
#define DT_ADC_1_NAME DT_ST_STM32_ADC_50040000_LABEL
#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))