intel-adsp: migrate cavs-mem.h to adsp_memory.h
Move header and make it soc specific. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
parent
3586227a7c
commit
af3d5331a1
21 changed files with 171 additions and 44 deletions
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@ -3,7 +3,7 @@
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/ipm.h>
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#include <cavs-mem.h>
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#include <adsp_memory.h>
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#include <adsp_shim.h>
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#include <cavs_ipc.h>
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@ -33,7 +33,7 @@
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#include <zephyr/sys/mem_blocks.h>
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#include <soc.h>
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#include <cavs-mem.h>
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#include <adsp_memory.h>
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#include "mm_drv_common.h"
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@ -31,7 +31,7 @@
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#include <zephyr/sys/util.h>
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#include <soc.h>
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#include <cavs-mem.h>
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#include <adsp_memory.h>
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#include <zephyr/drivers/mm/system_mm.h>
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#include "mm_drv_common.h"
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@ -17,7 +17,7 @@ OUTPUT_ARCH(xtensa)
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#include <xtensa/config/core-isa.h>
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#include <zephyr/linker/sections.h>
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#include <cavs-vectors.h>
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#include <cavs-mem.h>
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#include <adsp_memory.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/linker/linker-tool.h>
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@ -6,6 +6,37 @@
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#ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
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#define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
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#include <zephyr/devicetree.h>
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#include <cavs-vectors.h>
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#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
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#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
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#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
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#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
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#define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
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/* Linker-usable RAM region */
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#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
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#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
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/* Host shared memory windows */
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#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
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#define HP_SRAM_WIN0_SIZE 0x2000
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#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
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#define HP_SRAM_WIN3_SIZE 0x2000
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/* The rimage tool produces two blob addresses we need to find: one is
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* our bootloader code block which starts at its entry point, the
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* other is the "manifest" containing the HP-SRAM data to unpack,
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* which appears 24k earlier in the DMA'd file, and thus in IMR
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* memory. There's no ability to change this offset, it's a magic
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* number from rimage we simply need to honor.
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*/
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
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#define ADSP_L1_CACHE_PREFCTL_VALUE 0x1038
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#endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */
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@ -10,7 +10,7 @@
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#include <soc.h>
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#include <ace_v1x-regs.h>
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#include <ace-ipc-regs.h>
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#include <cavs-mem.h>
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#include <adsp_memory.h>
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#define CORE_POWER_CHECK_NUM 32
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#define CORE_POWER_CHECK_DELAY 256
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@ -8,7 +8,7 @@
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#include <zephyr/irq_nextlevel.h>
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#include <ace_v1x-regs.h>
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#include <cavs-mem.h>
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#include <adsp_memory.h>
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#include <adsp_shim.h>
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#include <cpu_init.h>
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#include <soc.h>
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#ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
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#define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
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#include <zephyr/devicetree.h>
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#include <cavs-vectors.h>
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#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
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#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
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#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
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#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
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#define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
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/* Linker-usable RAM region */
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#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
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#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
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/* Host shared memory windows */
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#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
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#define HP_SRAM_WIN0_SIZE 0x2000
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#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
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#define HP_SRAM_WIN3_SIZE 0x2000
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/* The rimage tool produces two blob addresses we need to find: one is
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* our bootloader code block which starts at its entry point, the
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* other is the "manifest" containing the HP-SRAM data to unpack,
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* which appears 24k earlier in the DMA'd file, and thus in IMR
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* memory. There's no ability to change this offset, it's a magic
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* number from rimage we simply need to honor.
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*/
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
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#define ADSP_L1_CACHE_PREFCTL_VALUE 0
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#endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */
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#ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
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#define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
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#include <zephyr/devicetree.h>
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#include <cavs-vectors.h>
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#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
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#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
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#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
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#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
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#define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
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/* Linker-usable RAM region */
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#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
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#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
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/* Host shared memory windows */
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#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
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#define HP_SRAM_WIN0_SIZE 0x2000
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#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
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#define HP_SRAM_WIN3_SIZE 0x2000
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/* The rimage tool produces two blob addresses we need to find: one is
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* our bootloader code block which starts at its entry point, the
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* other is the "manifest" containing the HP-SRAM data to unpack,
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* which appears 24k earlier in the DMA'd file, and thus in IMR
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* memory. There's no ability to change this offset, it's a magic
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* number from rimage we simply need to honor.
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*/
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
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#define ADSP_L1_CACHE_PREFCTL_VALUE 0
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#endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */
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#ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
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#define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
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#include <zephyr/devicetree.h>
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#include <cavs-vectors.h>
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#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
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#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
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#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
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#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
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#define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
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/* Linker-usable RAM region */
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#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
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#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
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/* Host shared memory windows */
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#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
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#define HP_SRAM_WIN0_SIZE 0x2000
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#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
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#define HP_SRAM_WIN3_SIZE 0x2000
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/* The rimage tool produces two blob addresses we need to find: one is
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* our bootloader code block which starts at its entry point, the
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* other is the "manifest" containing the HP-SRAM data to unpack,
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* which appears 24k earlier in the DMA'd file, and thus in IMR
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* memory. There's no ability to change this offset, it's a magic
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* number from rimage we simply need to honor.
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*/
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
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#define ADSP_L1_CACHE_PREFCTL_VALUE 0
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#endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */
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#ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
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#define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
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#include <zephyr/devicetree.h>
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#include <cavs-vectors.h>
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#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
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#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
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#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
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#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
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#define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
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/* Linker-usable RAM region */
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#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
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#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
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/* Host shared memory windows */
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#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
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#define HP_SRAM_WIN0_SIZE 0x2000
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#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
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#define HP_SRAM_WIN3_SIZE 0x2000
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/* The rimage tool produces two blob addresses we need to find: one is
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* our bootloader code block which starts at its entry point, the
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* other is the "manifest" containing the HP-SRAM data to unpack,
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* which appears 24k earlier in the DMA'd file, and thus in IMR
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* memory. There's no ability to change this offset, it's a magic
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* number from rimage we simply need to honor.
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*/
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
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#define ADSP_L1_CACHE_PREFCTL_VALUE 0x1038
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#endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */
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#include <soc.h>
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#include <zephyr/arch/xtensa/cache.h>
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#include <adsp_shim.h>
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#include <cavs-mem.h>
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#include <adsp_memory.h>
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#include <cpu_init.h>
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#include "manifest.h"
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#include <xtensa/config/core-isa.h>
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#include <zephyr/linker/sections.h>
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#include <cavs-vectors.h>
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#include <cavs-mem.h>
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#include <adsp_memory.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/linker/linker-tool.h>
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#ifndef _ZEPHYR_SOC_INTEL_ADSP_MEM
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#define _ZEPHYR_SOC_INTEL_ADSP_MEM
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#include <zephyr/devicetree.h>
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#include <cavs-vectors.h>
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#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
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#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
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#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
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#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
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#define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
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/* Linker-usable RAM region */
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#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
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#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
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/* Host shared memory windows */
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#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
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#define HP_SRAM_WIN0_SIZE 0x2000
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#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
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#define HP_SRAM_WIN3_SIZE 0x2000
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/* The rimage tool produces two blob addresses we need to find: one is
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* our bootloader code block which starts at its entry point, the
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* other is the "manifest" containing the HP-SRAM data to unpack,
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* which appears 24k earlier in the DMA'd file, and thus in IMR
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* memory. There's no ability to change this offset, it's a magic
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* number from rimage we simply need to honor.
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*/
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
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#include <adsp_memory.h>
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#endif /* _ZEPHYR_SOC_INTEL_ADSP_MEM */
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <adsp_shim.h>
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#include <cavs-mem.h>
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#include <adsp_memory.h>
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/**
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* @brief HDA stream functionality for Intel ADSP
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#include <soc.h>
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#include <zephyr/arch/xtensa/cache.h>
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#include <adsp_shim.h>
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#include <cavs-mem.h>
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#include <adsp_memory.h>
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#include <cpu_init.h>
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struct cpustart_rec {
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*/
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#include <zephyr/zephyr.h>
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#include <cavs-idc.h>
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#include <cavs-mem.h>
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#include <adsp_memory.h>
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#include <adsp_shim.h>
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/* IDC power up message to the ROM firmware. This isn't documented
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <manifest.h>
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#include <cavs-mem.h>
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#include <adsp_memory.h>
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#include <zephyr/toolchain.h>
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/* These two modules defined here aren't runtime data used by Zephyr or
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#include <soc.h>
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#include <zephyr/arch/xtensa/cache.h>
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#include <adsp_shim.h>
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#include <cavs-mem.h>
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#include <adsp_memory.h>
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#include <cpu_init.h>
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#include "manifest.h"
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*/
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#include <zephyr/zephyr.h>
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#include <soc.h>
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#include <cavs-mem.h>
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#include <adsp_memory.h>
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#include <zephyr/sys/winstream.h>
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struct k_spinlock trace_lock;
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#include <zephyr/drivers/mm/system_mm.h>
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#include <soc.h>
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#include <cavs-mem.h>
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#include <adsp_memory.h>
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#define N_PAGES 3
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#define PAGE_SZ CONFIG_MM_DRV_PAGE_SIZE
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