intel-adsp: migrate cavs-mem.h to adsp_memory.h

Move header and make it soc specific.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2022-07-14 10:59:07 -04:00
commit af3d5331a1
21 changed files with 171 additions and 44 deletions

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@ -3,7 +3,7 @@
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/ipm.h>
#include <cavs-mem.h>
#include <adsp_memory.h>
#include <adsp_shim.h>
#include <cavs_ipc.h>

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@ -33,7 +33,7 @@
#include <zephyr/sys/mem_blocks.h>
#include <soc.h>
#include <cavs-mem.h>
#include <adsp_memory.h>
#include "mm_drv_common.h"

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@ -31,7 +31,7 @@
#include <zephyr/sys/util.h>
#include <soc.h>
#include <cavs-mem.h>
#include <adsp_memory.h>
#include <zephyr/drivers/mm/system_mm.h>
#include "mm_drv_common.h"

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@ -17,7 +17,7 @@ OUTPUT_ARCH(xtensa)
#include <xtensa/config/core-isa.h>
#include <zephyr/linker/sections.h>
#include <cavs-vectors.h>
#include <cavs-mem.h>
#include <adsp_memory.h>
#include <zephyr/linker/linker-defs.h>
#include <zephyr/linker/linker-tool.h>

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@ -6,6 +6,37 @@
#ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
#define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
#include <zephyr/devicetree.h>
#include <cavs-vectors.h>
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
#define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
/* Linker-usable RAM region */
#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
/* Host shared memory windows */
#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
#define HP_SRAM_WIN0_SIZE 0x2000
#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
#define HP_SRAM_WIN3_SIZE 0x2000
/* The rimage tool produces two blob addresses we need to find: one is
* our bootloader code block which starts at its entry point, the
* other is the "manifest" containing the HP-SRAM data to unpack,
* which appears 24k earlier in the DMA'd file, and thus in IMR
* memory. There's no ability to change this offset, it's a magic
* number from rimage we simply need to honor.
*/
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
#define ADSP_L1_CACHE_PREFCTL_VALUE 0x1038
#endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */

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@ -10,7 +10,7 @@
#include <soc.h>
#include <ace_v1x-regs.h>
#include <ace-ipc-regs.h>
#include <cavs-mem.h>
#include <adsp_memory.h>
#define CORE_POWER_CHECK_NUM 32
#define CORE_POWER_CHECK_DELAY 256

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@ -8,7 +8,7 @@
#include <zephyr/irq_nextlevel.h>
#include <ace_v1x-regs.h>
#include <cavs-mem.h>
#include <adsp_memory.h>
#include <adsp_shim.h>
#include <cpu_init.h>
#include <soc.h>

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@ -6,6 +6,37 @@
#ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
#define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
#include <zephyr/devicetree.h>
#include <cavs-vectors.h>
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
#define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
/* Linker-usable RAM region */
#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
/* Host shared memory windows */
#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
#define HP_SRAM_WIN0_SIZE 0x2000
#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
#define HP_SRAM_WIN3_SIZE 0x2000
/* The rimage tool produces two blob addresses we need to find: one is
* our bootloader code block which starts at its entry point, the
* other is the "manifest" containing the HP-SRAM data to unpack,
* which appears 24k earlier in the DMA'd file, and thus in IMR
* memory. There's no ability to change this offset, it's a magic
* number from rimage we simply need to honor.
*/
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
#define ADSP_L1_CACHE_PREFCTL_VALUE 0
#endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */

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@ -6,6 +6,37 @@
#ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
#define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
#include <zephyr/devicetree.h>
#include <cavs-vectors.h>
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
#define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
/* Linker-usable RAM region */
#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
/* Host shared memory windows */
#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
#define HP_SRAM_WIN0_SIZE 0x2000
#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
#define HP_SRAM_WIN3_SIZE 0x2000
/* The rimage tool produces two blob addresses we need to find: one is
* our bootloader code block which starts at its entry point, the
* other is the "manifest" containing the HP-SRAM data to unpack,
* which appears 24k earlier in the DMA'd file, and thus in IMR
* memory. There's no ability to change this offset, it's a magic
* number from rimage we simply need to honor.
*/
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
#define ADSP_L1_CACHE_PREFCTL_VALUE 0
#endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */

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@ -6,6 +6,37 @@
#ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
#define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
#include <zephyr/devicetree.h>
#include <cavs-vectors.h>
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
#define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
/* Linker-usable RAM region */
#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
/* Host shared memory windows */
#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
#define HP_SRAM_WIN0_SIZE 0x2000
#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
#define HP_SRAM_WIN3_SIZE 0x2000
/* The rimage tool produces two blob addresses we need to find: one is
* our bootloader code block which starts at its entry point, the
* other is the "manifest" containing the HP-SRAM data to unpack,
* which appears 24k earlier in the DMA'd file, and thus in IMR
* memory. There's no ability to change this offset, it's a magic
* number from rimage we simply need to honor.
*/
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
#define ADSP_L1_CACHE_PREFCTL_VALUE 0
#endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */

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@ -6,6 +6,37 @@
#ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
#define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
#include <zephyr/devicetree.h>
#include <cavs-vectors.h>
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
#define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
/* Linker-usable RAM region */
#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
/* Host shared memory windows */
#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
#define HP_SRAM_WIN0_SIZE 0x2000
#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
#define HP_SRAM_WIN3_SIZE 0x2000
/* The rimage tool produces two blob addresses we need to find: one is
* our bootloader code block which starts at its entry point, the
* other is the "manifest" containing the HP-SRAM data to unpack,
* which appears 24k earlier in the DMA'd file, and thus in IMR
* memory. There's no ability to change this offset, it's a magic
* number from rimage we simply need to honor.
*/
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
#define ADSP_L1_CACHE_PREFCTL_VALUE 0x1038
#endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */

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@ -9,7 +9,7 @@
#include <soc.h>
#include <zephyr/arch/xtensa/cache.h>
#include <adsp_shim.h>
#include <cavs-mem.h>
#include <adsp_memory.h>
#include <cpu_init.h>
#include "manifest.h"

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@ -17,7 +17,7 @@ OUTPUT_ARCH(xtensa)
#include <xtensa/config/core-isa.h>
#include <zephyr/linker/sections.h>
#include <cavs-vectors.h>
#include <cavs-mem.h>
#include <adsp_memory.h>
#include <zephyr/linker/linker-defs.h>
#include <zephyr/linker/linker-tool.h>

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@ -4,34 +4,6 @@
#ifndef _ZEPHYR_SOC_INTEL_ADSP_MEM
#define _ZEPHYR_SOC_INTEL_ADSP_MEM
#include <zephyr/devicetree.h>
#include <cavs-vectors.h>
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
#define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
#define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
/* Linker-usable RAM region */
#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
/* Host shared memory windows */
#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
#define HP_SRAM_WIN0_SIZE 0x2000
#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
#define HP_SRAM_WIN3_SIZE 0x2000
/* The rimage tool produces two blob addresses we need to find: one is
* our bootloader code block which starts at its entry point, the
* other is the "manifest" containing the HP-SRAM data to unpack,
* which appears 24k earlier in the DMA'd file, and thus in IMR
* memory. There's no ability to change this offset, it's a magic
* number from rimage we simply need to honor.
*/
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
#include <adsp_memory.h>
#endif /* _ZEPHYR_SOC_INTEL_ADSP_MEM */

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@ -9,7 +9,7 @@
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <adsp_shim.h>
#include <cavs-mem.h>
#include <adsp_memory.h>
/**
* @brief HDA stream functionality for Intel ADSP

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@ -22,7 +22,7 @@ LOG_MODULE_REGISTER(soc_mp, CONFIG_SOC_LOG_LEVEL);
#include <soc.h>
#include <zephyr/arch/xtensa/cache.h>
#include <adsp_shim.h>
#include <cavs-mem.h>
#include <adsp_memory.h>
#include <cpu_init.h>
struct cpustart_rec {

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@ -3,7 +3,7 @@
*/
#include <zephyr/zephyr.h>
#include <cavs-idc.h>
#include <cavs-mem.h>
#include <adsp_memory.h>
#include <adsp_shim.h>
/* IDC power up message to the ROM firmware. This isn't documented

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@ -2,7 +2,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <manifest.h>
#include <cavs-mem.h>
#include <adsp_memory.h>
#include <zephyr/toolchain.h>
/* These two modules defined here aren't runtime data used by Zephyr or

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@ -9,7 +9,7 @@
#include <soc.h>
#include <zephyr/arch/xtensa/cache.h>
#include <adsp_shim.h>
#include <cavs-mem.h>
#include <adsp_memory.h>
#include <cpu_init.h>
#include "manifest.h"

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@ -3,7 +3,7 @@
*/
#include <zephyr/zephyr.h>
#include <soc.h>
#include <cavs-mem.h>
#include <adsp_memory.h>
#include <zephyr/sys/winstream.h>
struct k_spinlock trace_lock;

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@ -14,7 +14,7 @@
#include <zephyr/drivers/mm/system_mm.h>
#include <soc.h>
#include <cavs-mem.h>
#include <adsp_memory.h>
#define N_PAGES 3
#define PAGE_SZ CONFIG_MM_DRV_PAGE_SIZE