soc: nxp_imx: rt: enable SWO output for iMX RT 10xx series
enable swo output for iMX RT 10xx series. SWO pinmux settings are currently only present for the RT1060 and RT1064 Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
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10 changed files with 77 additions and 2 deletions
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@ -333,6 +333,12 @@ etc.):
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- Parity: None
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- Stop bits: 1
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Using SWO
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---------
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SWO can be used as a logging backend, by setting ``CONFIG_LOG_BACKEND_SWO=y``.
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Your SWO viewer should be configured with a CPU frequency of 132MHz, and
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SWO frequency of 7500KHz.
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Flashing
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========
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@ -2,7 +2,7 @@
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* Copyright (c) 2022, NXP
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* SPDX-License-Identifier: Apache-2.0
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*
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* Note: File generated by rt_cfg_utils.py
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* Note: File generated by imx_cfg_utils.py
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* from mimxrt1060_evk.mex
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*/
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@ -327,6 +327,17 @@
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};
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};
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/* Note SWO is configured with a cpu frequency of 132MHz and SWO frequency of 7500KHz */
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pinmux_swo: pinmux_swo {
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group0 {
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pinmux = <&iomuxc_gpio_ad_b0_10_arm_trace_swo>;
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bias-disable;
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drive-strength = "r0-7";
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slew-rate = "fast";
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nxp,speed = "200-mhz";
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};
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};
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pinmux_usdhc1: pinmux_usdhc1 {
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group0 {
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pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
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@ -286,3 +286,8 @@ zephyr_udc0: &usb1 {
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&iomuxcgpr {
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status = "okay";
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};
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&itm {
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pinctrl-0 = <&pinmux_swo>;
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pinctrl-names = "default";
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};
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@ -339,6 +339,12 @@ etc.):
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- Parity: None
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- Stop bits: 1
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Using SWO
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---------
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SWO can be used as a logging backend, by setting ``CONFIG_LOG_BACKEND_SWO=y``.
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Your SWO viewer should be configured with a CPU frequency of 132MHz, and
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SWO frequency of 7500KHz.
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Flashing
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========
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@ -2,7 +2,7 @@
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* Copyright (c) 2022, NXP
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* SPDX-License-Identifier: Apache-2.0
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*
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* Note: File generated by rt_cfg_utils.py
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* Note: File generated by imx_cfg_utils.py
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* from mimxrt1064_evk.mex
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*/
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@ -314,6 +314,16 @@
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};
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};
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/* note swo is configured with a cpu frequency of 132mhz and swo frequency of 7500khz */
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pinmux_swo: pinmux_swo {
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group0 {
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pinmux = <&iomuxc_gpio_ad_b0_10_arm_trace_swo>;
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drive-strength = "r0-6";
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slew-rate = "fast";
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nxp,speed = "100-mhz";
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};
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};
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pinmux_usdhc1: pinmux_usdhc1 {
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group0 {
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pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
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@ -348,3 +348,8 @@ zephyr_udc0: &usb1 {
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&gpt_hw_timer {
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status = "okay";
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};
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&itm {
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pinctrl-0 = <&pinmux_swo>;
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pinctrl-names = "default";
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};
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@ -33,6 +33,12 @@
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reg = <0xe000ed90 0x40>;
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arm,num-mpu-regions = <16>;
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};
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itm: itm@e0000000 {
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compatible = "arm,armv7m-itm";
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reg = <0xe0000000 0x1000>;
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swo-ref-frequency = <132000000>;
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};
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};
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};
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@ -64,6 +64,10 @@ config IMX_USDHC
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default y if (HAS_MCUX_USDHC1 || HAS_MCUX_USDHC2)
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depends on SDHC
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config LOG_BACKEND_SWO_FREQ_HZ
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default 7500000
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depends on LOG_BACKEND_SWO
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if FLASH_MCUX_FLEXSPI_XIP
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# Avoid RWW hazards by defaulting logging to disabled
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@ -29,6 +29,7 @@ config SOC_MIMXRT1011
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select HAS_MCUX_DCDC
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select HAS_MCUX_PMU
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select HAS_MCUX_IOMUXC
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select HAS_SWO
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config SOC_MIMXRT1015
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bool "SOC_MIMXRT1015"
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@ -53,6 +54,7 @@ config SOC_MIMXRT1015
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select HAS_MCUX_DCDC
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select HAS_MCUX_PMU
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select HAS_MCUX_IOMUXC
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select HAS_SWO
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config SOC_MIMXRT1021
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bool "SOC_MIMXRT1021"
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@ -83,6 +85,7 @@ config SOC_MIMXRT1021
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select HAS_MCUX_DCDC
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select HAS_MCUX_PMU
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select HAS_MCUX_IOMUXC
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select HAS_SWO
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config SOC_MIMXRT1024
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bool "SOC_MIMXRT1024"
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@ -113,6 +116,7 @@ config SOC_MIMXRT1024
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select HAS_MCUX_DCDC
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select HAS_MCUX_PMU
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select HAS_MCUX_IOMUXC
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select HAS_SWO
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config SOC_MIMXRT1051
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bool "SOC_MIMXRT1051"
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@ -143,6 +147,7 @@ config SOC_MIMXRT1051
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select HAS_MCUX_DCDC
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select HAS_MCUX_PMU
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select HAS_MCUX_IOMUXC
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select HAS_SWO
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config SOC_MIMXRT1052
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bool "SOC_MIMXRT1052"
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@ -177,6 +182,7 @@ config SOC_MIMXRT1052
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select HAS_MCUX_DCDC
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select HAS_MCUX_PMU
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select HAS_MCUX_IOMUXC
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select HAS_SWO
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config SOC_MIMXRT1061
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bool "SOC_MIMXRT1061"
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@ -207,6 +213,7 @@ config SOC_MIMXRT1061
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select HAS_MCUX_DCDC
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select HAS_MCUX_PMU
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select HAS_MCUX_IOMUXC
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select HAS_SWO
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config SOC_MIMXRT1062
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bool "SOC_MIMXRT1062"
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@ -246,6 +253,7 @@ config SOC_MIMXRT1062
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select HAS_MCUX_IOMUXC
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select HAS_MCUX_ADC_ETC
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select HAS_MCUX_SRC
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select HAS_SWO
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config SOC_MIMXRT1064
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bool "SOC_MIMXRT1064"
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@ -283,6 +291,7 @@ config SOC_MIMXRT1064
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select HAS_MCUX_DCDC
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select HAS_MCUX_PMU
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select HAS_MCUX_IOMUXC
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select HAS_SWO
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config SOC_MIMXRT1176_CM7
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bool "SOC_MIMXRT1176_CM7"
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@ -323,6 +332,7 @@ config SOC_MIMXRT1176_CM7
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select HAS_MCUX_ACMP
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select HAS_MCUX_SRC_V2
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select HAS_MCUX_IOMUXC
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select HAS_SWO
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config SOC_MIMXRT1176_CM4
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bool "SOC_MIMXRT1176_CM4"
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@ -352,6 +362,7 @@ config SOC_MIMXRT1176_CM4
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select HAS_MCUX_ACMP
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select HAS_MCUX_SRC_V2
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select HAS_MCUX_IOMUXC
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select HAS_SWO
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config SOC_MIMXRT1166_CM7
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bool "SOC_MIMXRT1166_CM7"
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@ -388,6 +399,7 @@ config SOC_MIMXRT1166_CM7
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select HAS_MCUX_USB_EHCI
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select HAS_MCUX_SRC_V2
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select HAS_MCUX_IOMUXC
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select HAS_SWO
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config SOC_MIMXRT1166_CM4
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@ -416,6 +428,7 @@ config SOC_MIMXRT1166_CM4
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select HAS_MCUX_GPC
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select HAS_MCUX_SRC_V2
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select HAS_MCUX_IOMUXC
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select HAS_SWO
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endchoice
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@ -212,6 +212,15 @@ static ALWAYS_INLINE void clock_init(void)
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CLOCK_SetMux(kCLOCK_CanMux, 2); /* Set Can clock source. */
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#endif
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#ifdef CONFIG_LOG_BACKEND_SWO
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/* Enable ARM trace clock to enable SWO output */
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CLOCK_EnableClock(kCLOCK_Trace);
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/* Divide root clock output by 3 */
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CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
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/* Source clock from 528MHz system PLL */
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CLOCK_SetMux(kCLOCK_TraceMux, 0);
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#endif
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/* Keep the system clock running so SYSTICK can wake up the system from
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* wfi.
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*/
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