soc: riscv: riscv-privilege: add GP relative addressing support

Initialize GP at common entry point of riscv-privilege SoCs so that
this commit add GP support of these SoCs at once.

As some privilege SoCs want to customize the entry point, they should
disable linker relaxation by `.norelax option` before entrying the
common entry point `__start`.

Signed-off-by: Jim Shu <cwshu@andestech.com>

soc/riscv/riscv-privilege/common/vector.S

@@ -15,6 +15,14 @@ GTEXT(__initialize)
 GTEXT(__irq_wrapper)
 
 SECTION_FUNC(vectors, __start)
+#if defined(CONFIG_RISCV_GP)
+	/* Initialize global pointer */
+	.option push
+	.option norelax
+	la gp, __global_pointer$
+	.option pop
+#endif
+
 	.option norvc;
 
 	/*

soc/riscv/riscv-privilege/miv/Kconfig.defconfig.series

@@ -17,6 +17,9 @@ config RISCV_HAS_CPU_IDLE
 config RISCV_HAS_PLIC
 	default y
 
+config RISCV_GP
+	default y
+
 config 2ND_LVL_ISR_TBL_OFFSET
 	default 12
 

soc/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series

@@ -17,6 +17,9 @@ config RISCV_HAS_CPU_IDLE
 config RISCV_HAS_PLIC
 	default y
 
+config RISCV_GP
+	default y
+
 config 2ND_LVL_ISR_TBL_OFFSET
 	default 12
 

soc/riscv/riscv-privilege/starfive_jh71xx/Kconfig.defconfig.series

@@ -18,6 +18,9 @@ config RISCV_HAS_CPU_IDLE
 config RISCV_HAS_PLIC
 	default y
 
+config RISCV_GP
+	default y
+
 config 2ND_LVL_ISR_TBL_OFFSET
 	default 12
 

soc/riscv/riscv-privilege/virt/Kconfig.defconfig.series

@@ -18,6 +18,9 @@ config RISCV_HAS_CPU_IDLE
 config RISCV_HAS_PLIC
 	default y
 
+config RISCV_GP
+	default y
+
 config 2ND_LVL_ISR_TBL_OFFSET
 	default 12