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dts: clocks: kinetis: set pllfll and er32k clock settings from dts

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Setup osc clock settings from dts.

Signed-off-by: Nicolai Glud <nicolai.glud@prevas.dk>
This commit is contained in:
Nicolai Glud 2020-07-02 14:14:18 +02:00 • committed by Maureen Helm
commit bc72b67a5d
18 changed files with 84 additions and 52 deletions
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5
boards/arm/frdm_k22f/frdm_k22f.dts
View file

@ -87,6 +87,11 @@
};
};
&sim {
pllfll-select = <KINETIS_SIM_PLLFLLSEL_MCGPLLCLK>;
er32k-select = <KINETIS_SIM_ER32KSEL_RTC>;
};
&adc0 {
status = "okay";
};

5
boards/arm/frdm_k64f/frdm_k64f.dts
View file

@ -87,6 +87,11 @@
};
};
&sim {
pllfll-select = <KINETIS_SIM_PLLFLLSEL_MCGPLLCLK>;
er32k-select = <KINETIS_SIM_ER32KSEL_RTC>;
};
arduino_serial: &uart3 {
status = "okay";
current-speed = <115200>;

5
boards/arm/frdm_k82f/frdm_k82f.dts
View file

@ -106,6 +106,11 @@
};
};
&sim {
pllfll-select = <KINETIS_SIM_PLLFLLSEL_MCGPLLCLK>;
er32k-select = <KINETIS_SIM_ER32KSEL_OSC32KCLK>;
};
&adc0 {
status = "okay";
};

5
boards/arm/frdm_kl25z/frdm_kl25z.dts
View file

@ -81,6 +81,11 @@
};
};
&sim {
pllfll-select = <KINETIS_SIM_PLLFLLSEL_MCGPLLCLK>;
er32k-select = <KINETIS_SIM_ER32KSEL_LPO1KHZ>;
};
&cpu0 {
clock-frequency = <48000000>;
};

5
boards/arm/frdm_kw41z/frdm_kw41z.dts
View file

@ -102,6 +102,11 @@
};
};
&sim {
pllfll-select = <KINETIS_SIM_PLLFLLSEL_MCGPLLCLK>;
er32k-select = <KINETIS_SIM_ER32KSEL_OSC32KCLK>;
};
&adc0 {
status = "okay";
};

5
boards/arm/hexiwear_k64/hexiwear_k64.dts
View file

@ -59,6 +59,11 @@
};
};
&sim {
pllfll-select = <KINETIS_SIM_PLLFLLSEL_MCGPLLCLK>;
er32k-select = <KINETIS_SIM_ER32KSEL_RTC>;
};
&cpu0 {
clock-frequency = <120000000>;
};

5
boards/arm/hexiwear_kw40z/hexiwear_kw40z.dts
View file

@ -14,6 +14,11 @@
};
};
&sim {
pllfll-select = <KINETIS_SIM_PLLFLLSEL_MCGPLLCLK>;
er32k-select = <KINETIS_SIM_ER32KSEL_OSC32KCLK>;
};
&adc0 {
status = "okay";
};

5
boards/arm/ip_k66f/ip_k66f.dts
View file

@ -42,6 +42,11 @@
clock-frequency = <120000000>;
};
&sim {
pllfll-select = <KINETIS_SIM_PLLFLLSEL_MCGPLLCLK>;
er32k-select = <KINETIS_SIM_ER32KSEL_RTC>;
};
&gpioa {
status = "okay";
};

6
boards/arm/twr_kv58f220m/twr_kv58f220m.dts
View file

@ -73,6 +73,12 @@
};
};
&sim {
pllfll-select = <KINETIS_SIM_PLLFLLSEL_MCGPLLCLK>;
er32k-select = <KINETIS_SIM_ER32KSEL_OSC32KCLK>;
};
&gpioa {
status = "okay";
};

5
boards/arm/usb_kw24d512/usb_kw24d512.dts
View file

@ -43,6 +43,11 @@
};
};
&sim {
pllfll-select = <KINETIS_SIM_PLLFLLSEL_MCGPLLCLK>;
er32k-select = <KINETIS_SIM_ER32KSEL_RTC>;
};
&cpu0 {
clock-frequency = <48000000>;
};

10
dts/bindings/arm/nxp,kinetis-sim.yaml
View file

@ -14,6 +14,16 @@ properties:
label:
required: true
pllfll-select:
type: int
required: true
description: pll/fll selection for clock system
er32k-select:
type: int
required: true
description: er32k selection for clock system
clkout-source:
type: int
required: false

9
include/dt-bindings/clock/kinetis_sim.h
View file

@ -15,4 +15,13 @@
#define KINETIS_SIM_DMAMUX_CLK KINETIS_SIM_BUS_CLK
#define KINETIS_SIM_DMA_CLK KINETIS_SIM_CORESYS_CLK
#define KINETIS_SIM_PLLFLLSEL_MCGFLLCLK 0
#define KINETIS_SIM_PLLFLLSEL_MCGPLLCLK 1
#define KINETIS_SIM_PLLFLLSEL_IRC48MHZ 3
#define KINETIS_SIM_ER32KSEL_OSC32KCLK 0
#define KINETIS_SIM_ER32KSEL_RTC 2
#define KINETIS_SIM_ER32KSEL_LPO1KHZ 3
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SIM_H_ */

12
soc/arm/nxp_kinetis/k2x/soc.c
View file

@ -25,14 +25,6 @@
#include <arch/cpu.h>
#include <arch/arm/aarch32/cortex_m/cmsis.h>
#define PLLFLLSEL_MCGFLLCLK (0)
#define PLLFLLSEL_MCGPLLCLK (1)
#define PLLFLLSEL_IRC48MHZ (3)
#define ER32KSEL_OSC32KCLK (0)
#define ER32KSEL_RTC (2)
#define ER32KSEL_LPO1KHZ (3)
#define TIMESRC_OSCERCLK (2)
static const osc_config_t oscConfig = {
@ -62,8 +54,8 @@ static const mcg_pll_config_t pll0Config = {
};
static const sim_clock_config_t simConfig = {
.pllFllSel = PLLFLLSEL_MCGPLLCLK, /* PLLFLLSEL select PLL. */
.er32kSrc = ER32KSEL_RTC, /* ERCLK32K selection, use RTC. */
.pllFllSel = DT_PROP(DT_INST(0, nxp_kinetis_sim), pllfll_select),
.er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CONFIG_K22_CORE_CLOCK_DIVIDER - 1) |
SIM_CLKDIV1_OUTDIV2(CONFIG_K22_BUS_CLOCK_DIVIDER - 1) |
SIM_CLKDIV1_OUTDIV3(CONFIG_K22_FLEXBUS_CLOCK_DIVIDER - 1) |

12
soc/arm/nxp_kinetis/k6x/soc.c
View file

@ -23,14 +23,6 @@
#include <arch/cpu.h>
#include <arch/arm/aarch32/cortex_m/cmsis.h>
#define PLLFLLSEL_MCGFLLCLK (0)
#define PLLFLLSEL_MCGPLLCLK (1)
#define PLLFLLSEL_IRC48MHZ (3)
#define ER32KSEL_OSC32KCLK (0)
#define ER32KSEL_RTC (2)
#define ER32KSEL_LPO1KHZ (3)
#define TIMESRC_OSCERCLK (2)
#define RUNM_HSRUN (3)
@ -65,8 +57,8 @@ static const mcg_pll_config_t pll0Config = {
};
static const sim_clock_config_t simConfig = {
.pllFllSel = PLLFLLSEL_MCGPLLCLK, /* PLLFLLSEL select PLL. */
.er32kSrc = ER32KSEL_RTC, /* ERCLK32K selection, use RTC. */
.pllFllSel = DT_PROP(DT_INST(0, nxp_kinetis_sim), pllfll_select),
.er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CONFIG_K6X_CORE_CLOCK_DIVIDER - 1) |
SIM_CLKDIV1_OUTDIV2(CONFIG_K6X_BUS_CLOCK_DIVIDER - 1) |
SIM_CLKDIV1_OUTDIV3(CONFIG_K6X_FLEXBUS_CLOCK_DIVIDER - 1) |

19
soc/arm/nxp_kinetis/k8x/soc.c
View file

@ -14,13 +14,6 @@
#include <fsl_common.h>
#include <fsl_clock.h>
#define PLLFLLSEL_MCGFLLCLK (0)
#define PLLFLLSEL_MCGPLLCLK (1)
#define PLLFLLSEL_IRC48MHZ (3)
#define ER32KSEL_OSC32KCLK (0)
#define ER32KSEL_LPO1KHZ (3)
#define PERIPH_CLK_PLLFLLSEL (1)
#define PERIPH_CLK_OSCERCLK (2)
#define PERIPH_CLK_MCGIRCLK (3)
@ -59,14 +52,15 @@ static const mcg_pll_config_t pll0_config = {
};
static const sim_clock_config_t sim_config = {
/* PLLFLLSEL: select PLL. */
.pllFllSel = PLLFLLSEL_MCGPLLCLK,
/* ERCLK32K selection: use system oscillator. */
.er32kSrc = ER32KSEL_OSC32KCLK,
.pllFllSel = DT_PROP(DT_INST(0, nxp_kinetis_sim), pllfll_select),
.er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CONFIG_K8X_CORE_CLOCK_DIVIDER - 1) |
SIM_CLKDIV1_OUTDIV2(CONFIG_K8X_BUS_CLOCK_DIVIDER - 1) |
SIM_CLKDIV1_OUTDIV3(CONFIG_K8X_FLEXBUS_CLOCK_DIVIDER - 1) |
SIM_CLKDIV1_OUTDIV4(CONFIG_K8X_FLASH_CLOCK_DIVIDER - 1),
/* Divide PLL output frequency by 2 for peripherals */
.pllFllDiv = (1),
.pllFllFrac = (0),
};
static ALWAYS_INLINE void clk_init(void)
@ -83,9 +77,6 @@ static ALWAYS_INLINE void clk_init(void)
CLOCK_SetSimConfig(&sim_config);
/* Divide PLL output frequency by 2 for peripherals */
CLOCK_SetPllFllSelClock(PLLFLLSEL_MCGPLLCLK, 1, 0);
#if CONFIG_UART_MCUX_LPUART
CLOCK_SetLpuartClock(PERIPH_CLK_PLLFLLSEL);
#endif

4
soc/arm/nxp_kinetis/kl2x/soc.c
View file

@ -28,8 +28,8 @@ static ALWAYS_INLINE void clock_init(void)
.enableMode = 0U, .prdiv = CONFIG_MCG_PRDIV0, .vdiv = CONFIG_MCG_VDIV0,
};
const sim_clock_config_t simConfig = {
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.er32kSrc = 3U, /* ERCLK32K selection, use LPO. */
.pllFllSel = DT_PROP(DT_INST(0, nxp_kinetis_sim), pllfll_select),
.er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
.clkdiv1 = 0x10010000U, /* SIM_CLKDIV1. */
};

13
soc/arm/nxp_kinetis/kv5x/soc.c
View file

@ -14,13 +14,6 @@
#include <fsl_common.h>
#include <fsl_clock.h>
#define PLLFLLSEL_MCGFLLCLK (0)
#define PLLFLLSEL_MCGPLLCLK (1)
#define PLLFLLSEL_IRC48MHZ (3)
#define ER32KSEL_OSC32KCLK (0)
#define ER32KSEL_LPO1KHZ (3)
#define RUNM_RUN (0)
#define RUNM_VLPR (2)
#define RUNM_HSRUN (3)
@ -55,10 +48,8 @@ static const mcg_pll_config_t pll0_config = {
};
static const sim_clock_config_t sim_config = {
/* PLLFLLSEL: select PLL. */
.pllFllSel = PLLFLLSEL_MCGPLLCLK,
/* ERCLK32K selection: use system oscillator. */
.er32kSrc = ER32KSEL_OSC32KCLK,
.pllFllSel = DT_PROP(DT_INST(0, nxp_kinetis_sim), pllfll_select),
.er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CONFIG_KV5X_CORE_CLOCK_DIVIDER - 1) |
SIM_CLKDIV1_OUTDIV2(CONFIG_KV5X_BUS_CLOCK_DIVIDER - 1) |
SIM_CLKDIV1_OUTDIV3(CONFIG_KV5X_FLEXBUS_CLOCK_DIVIDER - 1) |

6
soc/arm/nxp_kinetis/kwx/soc_kw4xz.c
View file

@ -13,10 +13,6 @@
#include <fsl_clock.h>
#include <arch/cpu.h>
#define ER32KSEL_OSC32KCLK (0)
#define ER32KSEL_RTC (2)
#define ER32KSEL_LPO1KHZ (3)
#define LPUART0SRC_OSCERCLK (1)
#define TPMSRC_MCGPLLCLK (1)
@ -37,7 +33,7 @@ static const osc_config_t oscConfig = {
};
static const sim_clock_config_t simConfig = {
.er32kSrc = ER32KSEL_OSC32KCLK,
.er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
.clkdiv1 = SIM_CLKDIV1_OUTDIV4(CLKDIV1_DIVBY2),
};