soc: riscv: andes_v5: introduce Andes V5 PMA to support nocache memory
Andes V5 PMA can let SW programmably configure memory attribute of physical memory region. This commit enable CONFIG_NOCACHE_MEMORY of Andes V5 CPUs based on the PMA. Use PMA region 0 to set whole nocache section as uncached memory. Signed-off-by: Jim Shu <cwshu@andestech.com>
This commit is contained in:
Jim Shu
Anas Nashif
parent
7db0fedcfe
commit
3b7221363a
4 changed files with 289 additions and 0 deletions
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@ -7,6 +7,8 @@ zephyr_sources(
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soc_irq.S
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)
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zephyr_sources_ifdef(CONFIG_SOC_ANDES_V5_PMA pma.c)
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# Note: AndeStar V5 DSP needs custom Andes V5 toolchain
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if(CONFIG_SOC_ANDES_V5_HWDSP)
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zephyr_cc_option(-mext-dsp)
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@ -63,4 +63,21 @@ config SOC_ANDES_V5_PFT
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The PowerBrake extension throttles performance by reducing instruction
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executing rate.
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config SOC_ANDES_V5_PMA
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bool "Enable Andes V5 Physical Memory Attribute (PMA)"
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select ARCH_HAS_NOCACHE_MEMORY_SUPPORT
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help
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This option enables the Andes V5 PMA, in order to support SW to
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configure physical memory attribute by PMA CSRs. The address
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matching of Andes V5 PMA is like RISC-V PMP NAPOT mode
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(power-of-two alignment).
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config SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE
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int
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depends on SOC_ANDES_V5_PMA
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default 4096
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help
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Minimum size (and alignment) of an PMA region. Use this symbol
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to guarantee minimum size and alignment of PMA regions.
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endif # SOC_SERIES_RISCV_ANDES_V5
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@ -59,6 +59,27 @@
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#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS
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#define RAM_SIZE KB(CONFIG_SRAM_SIZE)
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/* Make linker section alignment comply with PMA granularity. */
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#if defined(CONFIG_SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE)
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_region_min_align = CONFIG_SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE;
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#else
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_region_min_align = 4;
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#endif
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#if defined(CONFIG_SOC_ANDES_V5_PMA)
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/*
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* Andes-V5 PMA needs power-of-2 alignment.
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*/
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#define MPU_MIN_SIZE_ALIGN . = ALIGN(_region_min_align);
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#define MPU_ALIGN(region_size) \
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. = ALIGN(_region_min_align); \
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. = ALIGN( 1 << LOG2CEIL(region_size))
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#else
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#define MPU_MIN_SIZE_ALIGN
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#define MPU_ALIGN(region_size) \
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. = ALIGN(_region_min_align)
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#endif
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MEMORY
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{
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#ifdef CONFIG_XIP
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249
soc/riscv/riscv-privilege/andes_v5/pma.c
Normal file
249
soc/riscv/riscv-privilege/andes_v5/pma.c
Normal file
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@ -0,0 +1,249 @@
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/*
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* Copyright (c) 2021 Andes Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <init.h>
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <linker/linker-defs.h>
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/* Programmable PMA mechanism is supported */
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#define MMSC_CFG_PPMA (1 << 30)
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/*
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* PMA Configuration (PMACFG) bitfields
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*/
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/* ETYPE: Entry address matching mode */
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#define PMACFG_ETYPE_MASK 3
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#define PMACFG_ETYPE_OFF 0
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#define PMACFG_ETYPE_TOR 1
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#define PMACFG_ETYPE_NA4 2
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#define PMACFG_ETYPE_NAPOT 3
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/* MTYPE: Memory type attribute */
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#define PMACFG_MTYPE_MASK (0xF << 2)
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/* non-cacheable attributes (bufferable or not) */
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#define PMACFG_MTYPE_MEMORY_NOCACHE_BUFFERABLE (3 << 2)
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/* cacheable attributes (write-through/back, no/read/write/RW-allocate) */
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#define PMACFG_MTYPE_MEMORY_WBCACHE_RWALLOC (11 << 2)
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/* pmaaddr is 4-byte granularity in each mode */
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#define TO_PMA_ADDR(addr) ((addr) >> 2)
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/* The base address is aligned to size */
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#define NAPOT_BASE(start, size) TO_PMA_ADDR((start) & ~((size) - 1))
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/* The encoding of size is 0b01...1
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* (change the leading bit of bitmask to 0)
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*/
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#define NAPOT_SIZE(size) TO_PMA_ADDR(((size) - 1) >> 1)
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#define NA4_ENCODING(start) TO_PMA_ADDR(start)
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#define NAPOT_ENCODING(start, size) (NAPOT_BASE(start, size) \
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| NAPOT_SIZE(size))
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#ifdef CONFIG_64BIT
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/* In riscv64, CSR pmacfg number are even number (0, 2, ...) */
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# define PMACFG_NUM(index) ((index / RV_REGSIZE) * 2)
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#else
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# define PMACFG_NUM(index) (index / RV_REGSIZE)
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#endif
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#define PMACFG_SHIFT(index) ((index % RV_REGSIZE) * 8)
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/* Wrappers of inline assembly */
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#define read_csr(var, csr) \
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__asm__ volatile ("csrr %0, %1" : "=r" (var) : "i" (csr))
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#define write_csr(csr, val) \
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__asm__ volatile ("csrw %0, %1" :: "i" (csr), "r" (val))
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struct pma_region_attr {
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/* Attributes belonging to pmacfg{i} */
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uint8_t pmacfg;
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};
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struct pma_region {
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ulong_t start;
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ulong_t size;
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struct pma_region_attr attr;
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};
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/*
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* Write value to CSRs pmaaddr{i}
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*/
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static void write_pmaaddr_csr(const uint32_t index, ulong_t value)
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{
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switch (index) {
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case 0:
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write_csr(NDS_PMAADDR0, value); break;
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case 1:
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write_csr(NDS_PMAADDR1, value); break;
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case 2:
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write_csr(NDS_PMAADDR2, value); break;
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case 3:
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write_csr(NDS_PMAADDR3, value); break;
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case 4:
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write_csr(NDS_PMAADDR4, value); break;
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case 5:
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write_csr(NDS_PMAADDR5, value); break;
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case 6:
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write_csr(NDS_PMAADDR6, value); break;
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case 7:
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write_csr(NDS_PMAADDR7, value); break;
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case 8:
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write_csr(NDS_PMAADDR8, value); break;
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case 9:
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write_csr(NDS_PMAADDR9, value); break;
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case 10:
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write_csr(NDS_PMAADDR10, value); break;
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case 11:
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write_csr(NDS_PMAADDR11, value); break;
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case 12:
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write_csr(NDS_PMAADDR12, value); break;
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case 13:
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write_csr(NDS_PMAADDR13, value); break;
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case 14:
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write_csr(NDS_PMAADDR14, value); break;
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case 15:
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write_csr(NDS_PMAADDR15, value); break;
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}
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}
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/*
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* Write value to pma{i}cfg entry which are packed into CSRs pmacfg{j}
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*/
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static void write_pmacfg_entry(const uint32_t entry_index,
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uint8_t entry_value)
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{
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/* 1-byte pma{i}cfg entries are packed into XLEN-byte CSRs pmacfg{j} */
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uint32_t index = PMACFG_NUM(entry_index);
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uint8_t shift = PMACFG_SHIFT(entry_index);
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ulong_t pmacfg = 0;
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switch (index) {
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case 0:
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read_csr(pmacfg, NDS_PMACFG0); break;
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case 1:
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read_csr(pmacfg, NDS_PMACFG1); break;
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case 2:
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read_csr(pmacfg, NDS_PMACFG2); break;
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case 3:
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read_csr(pmacfg, NDS_PMACFG3); break;
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}
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/* clear old value in pmacfg entry */
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pmacfg &= ~(0xFF << shift);
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/* set new value to pmacfg entry value */
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pmacfg |= entry_value << shift;
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switch (index) {
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case 0:
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write_csr(NDS_PMACFG0, pmacfg); break;
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case 1:
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write_csr(NDS_PMACFG1, pmacfg); break;
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case 2:
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write_csr(NDS_PMACFG2, pmacfg); break;
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case 3:
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write_csr(NDS_PMACFG3, pmacfg); break;
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}
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}
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/*
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* This internal function performs PMA region initialization.
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*
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* Note:
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* The caller must provide a valid region index.
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*/
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static void region_init(const uint32_t index,
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const struct pma_region *region_conf)
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{
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ulong_t pmaaddr;
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uint8_t pmacfg;
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if (region_conf->size == 4) {
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pmaaddr = NA4_ENCODING(region_conf->start);
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pmacfg = region_conf->attr.pmacfg | PMACFG_ETYPE_NA4;
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} else {
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pmaaddr = NAPOT_ENCODING(region_conf->start, region_conf->size);
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pmacfg = region_conf->attr.pmacfg | PMACFG_ETYPE_NAPOT;
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}
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write_pmaaddr_csr(index, pmaaddr);
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write_pmacfg_entry(index, pmacfg);
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}
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/*
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* This internal function performs run-time sanity check for
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* PMA region start address and size.
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*/
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static int pma_region_is_valid(const struct pma_region *region)
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{
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/* Region size must be power-of-two,
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* and greater or equal to the minimum
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* PMA region size. Start address of the
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* region must align with size.
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*/
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int region_is_valid =
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((region->size & (region->size - 1)) == 0U)
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&&
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(region->size >= CONFIG_SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE)
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&&
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((region->start & (region->size - 1)) == 0U);
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return region_is_valid;
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}
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#ifdef CONFIG_NOCACHE_MEMORY
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static void configure_nocache_region(void)
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{
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const struct pma_region nocache_region = {
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.start = (ulong_t)&_nocache_ram_start,
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.size = (ulong_t)&_nocache_ram_size,
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.attr = {PMACFG_MTYPE_MEMORY_NOCACHE_BUFFERABLE},
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};
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if (pma_region_is_valid(&nocache_region) == -EINVAL) {
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__ASSERT(0, "Configuring PMA region of nocache region failed\n");
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}
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/* Initialize nocache region at PMA region 0 */
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region_init(0, &nocache_region);
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}
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#endif /* CONFIG_NOCACHE_MEMORY */
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/*
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* @brief Init PMA CSRs of each CPU core
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*
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* In SMP, each CPU has it's own PMA CSR and PMA CSR only affect one CPU.
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* We should configure CSRs of all CPUs to make memory attribute
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* (e.g. uncacheable) affects all CPUs.
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*/
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void pma_init_per_core(void)
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{
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#ifdef CONFIG_NOCACHE_MEMORY
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configure_nocache_region();
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#endif /* CONFIG_NOCACHE_MEMORY */
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}
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static int pma_init(const struct device *arg)
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{
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ulong_t mmsc_cfg;
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__asm__ volatile ("csrr %0, %1" : "=r" (mmsc_cfg) : "i" (NDS_MMSC_CFG));
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if (!(mmsc_cfg & MMSC_CFG_PPMA)) {
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/* This CPU doesn't support PMA */
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__ASSERT(0, "CPU doesn't support PMA. "
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"Please disable CONFIG_SOC_ANDES_V5_PMA\n");
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return -1;
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}
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pma_init_per_core();
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return 0;
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}
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SYS_INIT(pma_init, PRE_KERNEL_2,
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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