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soc: xtensa: Convert to new DT_INST macros

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Convert older DT_INST_ macro use the new include/devicetree.h
DT_INST macro APIs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-03-27 05:34:41 -05:00 • committed by Kumar Gala
commit 120674660e
6 changed files with 12 additions and 12 deletions
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4
soc/xtensa/intel_apl_adsp/dts_fixup.h
View file

@ -9,8 +9,8 @@
#define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS
#define DT_L2_SRAM_SIZE (CONFIG_SRAM_SIZE * 1024)
#define DT_LP_SRAM_BASE DT_INST_1_MMIO_SRAM_BASE_ADDRESS
#define DT_LP_SRAM_SIZE DT_INST_1_MMIO_SRAM_SIZE
#define DT_LP_SRAM_BASE DT_REG_ADDR(DT_INST(1, mmio_sram))
#define DT_LP_SRAM_SIZE DT_REG_SIZE(DT_INST(1, mmio_sram))
#define DT_CAVS_ICTL_BASE_ADDR DT_INTEL_CAVS_INTC_1600_BASE_ADDRESS
#define DT_CAVS_ICTL_0_IRQ DT_INTEL_CAVS_INTC_1600_IRQ_0

4
soc/xtensa/intel_apl_adsp/soc_mp.c
View file

@ -106,7 +106,7 @@ static void mp_entry2(void)
#ifdef CONFIG_IPM_CAVS_IDC
/* Interrupt must be enabled while running on current core */
irq_enable(XTENSA_IRQ_NUMBER(DT_INST_0_INTEL_CAVS_IDC_IRQ_0));
irq_enable(XTENSA_IRQ_NUMBER(DT_IRQN(DT_INST(0, intel_cavs_idc))));
#endif /* CONFIG_IPM_CAVS_IDC */
start_rec.alive = 1;
@ -178,7 +178,7 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
SOC_DCACHE_FLUSH(&start_rec, sizeof(start_rec));
#ifdef CONFIG_SCHED_IPI_SUPPORTED
idc = device_get_binding(DT_INST_0_INTEL_CAVS_IDC_LABEL);
idc = device_get_binding(DT_LABEL(DT_INST(0, intel_cavs_idc)));
#endif
/* Enable IDC interrupt on the other core */

4
soc/xtensa/intel_s1000/dts_fixup.h
View file

@ -7,8 +7,8 @@
#define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS
#define DT_L2_SRAM_SIZE CONFIG_SRAM_SIZE * 1024
#define DT_LP_SRAM_BASE DT_INST_1_MMIO_SRAM_BASE_ADDRESS
#define DT_LP_SRAM_SIZE DT_INST_1_MMIO_SRAM_SIZE
#define DT_LP_SRAM_BASE DT_REG_ADDR(DT_INST(1, mmio_sram))
#define DT_LP_SRAM_SIZE DT_REG_SIZE(DT_INST(1, mmio_sram))
#define DT_CAVS_ICTL_BASE_ADDR DT_INTEL_CAVS_INTC_78800_BASE_ADDRESS
#define DT_CAVS_ICTL_0_IRQ DT_INTEL_CAVS_INTC_78800_IRQ_0

6
soc/xtensa/intel_s1000/soc.c
View file

@ -54,7 +54,7 @@ void z_soc_irq_enable(u32_t irq)
switch (CAVS_IRQ_NUMBER(irq)) {
case DW_ICTL_IRQ_CAVS_OFFSET:
dev_ictl = device_get_binding(DT_INST_0_SNPS_DESIGNWARE_INTC_LABEL);
dev_ictl = device_get_binding(DT_LABEL(DT_INST(0, snps_designware_intc)));
break;
default:
/* The source of the interrupt is in CAVS interrupt logic */
@ -112,7 +112,7 @@ void z_soc_irq_disable(u32_t irq)
switch (CAVS_IRQ_NUMBER(irq)) {
case DW_ICTL_IRQ_CAVS_OFFSET:
dev_ictl = device_get_binding(DT_INST_0_SNPS_DESIGNWARE_INTC_LABEL);
dev_ictl = device_get_binding(DT_LABEL(DT_INST(0, snps_designware_intc)));
break;
default:
/* The source of the interrupt is in CAVS interrupt logic */
@ -179,7 +179,7 @@ int z_soc_irq_is_enabled(unsigned int irq)
switch (CAVS_IRQ_NUMBER(irq)) {
case DW_ICTL_IRQ_CAVS_OFFSET:
dev_ictl = device_get_binding(DT_INST_0_SNPS_DESIGNWARE_INTC_LABEL);
dev_ictl = device_get_binding(DT_LABEL(DT_INST(0, snps_designware_intc)));
break;
default:
/* The source of the interrupt is in CAVS interrupt logic */

2
soc/xtensa/intel_s1000/soc.h
View file

@ -45,7 +45,7 @@
#define IOAPIC_HIGH 0
/* DW interrupt controller */
#define DW_ICTL_IRQ_CAVS_OFFSET CAVS_IRQ_NUMBER(DT_INST_0_SNPS_DESIGNWARE_INTC_IRQ_0)
#define DW_ICTL_IRQ_CAVS_OFFSET CAVS_IRQ_NUMBER(DT_IRQN(DT_INST(0, snps_designware_intc)))
#define DW_ICTL_NUM_IRQS 9
/* GPIO */

4
soc/xtensa/intel_s1000/soc_mp.c
View file

@ -69,7 +69,7 @@ static void mp_entry2(void)
#ifdef CONFIG_IPM_CAVS_IDC
/* Interrupt must be enabled while running on current core */
irq_enable(XTENSA_IRQ_NUMBER(DT_INST_0_INTEL_CAVS_IDC_IRQ_0));
irq_enable(XTENSA_IRQ_NUMBER(DT_IRQN(DT_INST(0, intel_cavs_idc))));
#endif /* CONFIG_IPM_CAVS_IDC */
start_rec.alive = 1;
@ -141,7 +141,7 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
SOC_DCACHE_FLUSH(&start_rec, sizeof(start_rec));
#ifdef CONFIG_SCHED_IPI_SUPPORTED
idc = device_get_binding(DT_INST_0_INTEL_CAVS_IDC_LABEL);
idc = device_get_binding(DT_LABEL(DT_INST(0, intel_cavs_idc)));
#endif
/*