linker: Introduce zephyr,memory-region compatible
Introduce a new "zephyr,memory-region" compatible to be used when a new memory region must be created in the linker script from the devicetree nodes using the compatible. Remove also the LINKER_DT_REGION_FROM_NODE macro and add a new LINKER_DT_REGIONS macro to cycle through all the compatible regions. In the same PR modify the DTS files and the linker scripts. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
parent
3c0c03b9eb
commit
18ffcdcf74
75 changed files with 132 additions and 150 deletions
|
@ -26,13 +26,13 @@
|
|||
|
||||
soc {
|
||||
itcm: memory@0 {
|
||||
compatible = "arm,itcm";
|
||||
compatible = "zephyr,memory-region", "arm,itcm";
|
||||
reg = <0x00000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "ITCM";
|
||||
};
|
||||
|
||||
dtcm: memory@20000000 {
|
||||
compatible = "arm,dtcm";
|
||||
compatible = "zephyr,memory-region", "arm,dtcm";
|
||||
reg = <0x20000000 DT_SIZE_K(32)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
|
|
@ -32,13 +32,13 @@
|
|||
|
||||
soc {
|
||||
itcm: memory@0 {
|
||||
compatible = "arm,itcm";
|
||||
compatible = "zephyr,memory-region", "arm,itcm";
|
||||
reg = <0x00000000 DT_SIZE_K(32)>;
|
||||
zephyr,memory-region = "ITCM";
|
||||
};
|
||||
|
||||
dtcm: memory@20000000 {
|
||||
compatible = "arm,dtcm";
|
||||
compatible = "zephyr,memory-region", "arm,dtcm";
|
||||
reg = <0x20000000 DT_SIZE_K(32)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
|
|
@ -80,13 +80,13 @@
|
|||
*/
|
||||
|
||||
sram1: memory@10000000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x10000000 DT_SIZE_M(4)>;
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
||||
sram2_3: memory@38000000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x38000000 DT_SIZE_M(4)>;
|
||||
zephyr,memory-region = "SRAM2_3";
|
||||
};
|
||||
|
|
|
@ -80,13 +80,13 @@
|
|||
*/
|
||||
|
||||
sram1: memory@0 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x0 DT_SIZE_M(4)>;
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
||||
sram2_3: memory@28000000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x28000000 DT_SIZE_M(4)>;
|
||||
zephyr,memory-region = "SRAM2_3";
|
||||
};
|
||||
|
|
|
@ -80,13 +80,13 @@
|
|||
*/
|
||||
|
||||
sram1: memory@0 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x0 DT_SIZE_M(4)>;
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
||||
sram2_3: memory@28000000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x28000000 DT_SIZE_M(4)>;
|
||||
zephyr,memory-region = "SRAM2_3";
|
||||
};
|
||||
|
|
|
@ -108,6 +108,7 @@
|
|||
* you'll get the non-secure alias
|
||||
*/
|
||||
itcm: itcm@10000000 { /* alias @ 0x0 */
|
||||
compatible = "zephyr,memory-region";
|
||||
reg = <0x10000000 DT_SIZE_K(512)>;
|
||||
zephyr,memory-region = "ITCM";
|
||||
};
|
||||
|
@ -118,6 +119,7 @@
|
|||
};
|
||||
|
||||
dtcm: dtcm@30000000 { /* alias @ 0x20000000 */
|
||||
compatible = "zephyr,memory-region";
|
||||
reg = <0x30000000 DT_SIZE_K(512)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
|
|
@ -22,7 +22,7 @@
|
|||
};
|
||||
|
||||
sdram2: sdram@d0000000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
device_type = "memory";
|
||||
reg = <0xd0000000 DT_SIZE_M(8)>;
|
||||
zephyr,memory-region = "SDRAM2";
|
||||
|
|
|
@ -23,7 +23,7 @@
|
|||
};
|
||||
|
||||
sdram1: sdram@c0000000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
device_type = "memory";
|
||||
reg = <0xc0000000 DT_SIZE_M(16)>;
|
||||
zephyr,memory-region = "SDRAM1";
|
||||
|
|
|
@ -22,7 +22,7 @@
|
|||
};
|
||||
|
||||
sdram2: sdram@d0000000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
device_type = "memory";
|
||||
reg = <0xd0000000 DT_SIZE_M(32)>;
|
||||
zephyr,memory-region = "SDRAM2";
|
||||
|
|
|
@ -46,7 +46,7 @@
|
|||
* exclusive for USB descriptors
|
||||
*/
|
||||
sram1: memory@21000000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x21000000 DT_SIZE_K(4)>;
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
|
|
@ -57,13 +57,13 @@
|
|||
};
|
||||
|
||||
sram1: memory@8023000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x08023000 DT_SIZE_K(4)>;
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
||||
sram2: memory@8024000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x08024000 DT_SIZE_K(112)>;
|
||||
zephyr,memory-region = "SRAM2";
|
||||
};
|
||||
|
|
|
@ -49,7 +49,7 @@
|
|||
};
|
||||
|
||||
sram1: memory@21000000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
||||
|
|
|
@ -24,13 +24,13 @@
|
|||
};
|
||||
|
||||
sram1:memory@20000000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x20000000 0x800>;
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
||||
sram2:memory@20004000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x20004000 0x800>;
|
||||
zephyr,memory-region = "SRAM2";
|
||||
};
|
||||
|
|
|
@ -50,13 +50,13 @@
|
|||
};
|
||||
|
||||
sram1:memory@20010000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x20010000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
||||
sram2:memory@20020000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x20020000 DT_SIZE_K(32)>;
|
||||
zephyr,memory-region = "SRAM2";
|
||||
};
|
||||
|
|
|
@ -45,20 +45,20 @@
|
|||
};
|
||||
|
||||
sram1: memory@20008000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x20008000 DT_SIZE_K(16)>;
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
||||
sram2: memory@2000c000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x2000c000 DT_SIZE_K(16)>;
|
||||
zephyr,memory-region = "SRAM2";
|
||||
};
|
||||
|
||||
sram4: memory@20010000 {
|
||||
/* Conencted to USB bus*/
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x20010000 DT_SIZE_K(16)>;
|
||||
zephyr,memory-region = "SRAM4";
|
||||
};
|
||||
|
|
|
@ -53,19 +53,19 @@
|
|||
};
|
||||
|
||||
sram1: memory@20010000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x20010000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
||||
sram2: memory@20020000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x20020000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "SRAM2";
|
||||
};
|
||||
|
||||
sram4: memory@20040000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x20040000 DT_SIZE_K(16)>;
|
||||
zephyr,memory-region = "SRAM4";
|
||||
};
|
||||
|
|
|
@ -57,25 +57,25 @@
|
|||
};
|
||||
|
||||
sram1: memory@20010000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x20010000 DT_SIZE_K(32)>;
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
||||
sram2: memory@20018000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x20018000 DT_SIZE_K(32)>;
|
||||
zephyr,memory-region = "SRAM2";
|
||||
};
|
||||
|
||||
sram3: memory@20020000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x20020000 DT_SIZE_K(32)>;
|
||||
zephyr,memory-region = "SRAM3";
|
||||
};
|
||||
|
||||
sram4: memory@40100000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x40100000 DT_SIZE_K(16)>;
|
||||
zephyr,memory-region = "SRAM4";
|
||||
};
|
||||
|
|
|
@ -50,13 +50,13 @@
|
|||
#size-cells = <1>;
|
||||
|
||||
itcm: itcm@0 {
|
||||
compatible = "nxp,imx-itcm";
|
||||
compatible = "zephyr,memory-region", "nxp,imx-itcm";
|
||||
reg = <0x00000000 DT_SIZE_K(128)>;
|
||||
zephyr,memory-region = "ITCM";
|
||||
};
|
||||
|
||||
dtcm: dtcm@20000000 {
|
||||
compatible = "nxp,imx-dtcm";
|
||||
compatible = "zephyr,memory-region", "nxp,imx-dtcm";
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
|
|
@ -28,7 +28,7 @@
|
|||
};
|
||||
|
||||
sram1: memory@20000000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
|
|
@ -29,13 +29,13 @@
|
|||
#size-cells = <1>;
|
||||
|
||||
itcm: itcm@0 {
|
||||
compatible = "nxp,imx-itcm";
|
||||
compatible = "zephyr,memory-region", "nxp,imx-itcm";
|
||||
reg = <0x00000000 DT_SIZE_K(256)>;
|
||||
zephyr,memory-region = "ITCM";
|
||||
};
|
||||
|
||||
dtcm: dtcm@20000000 {
|
||||
compatible = "nxp,imx-dtcm";
|
||||
compatible = "zephyr,memory-region", "nxp,imx-dtcm";
|
||||
reg = <0x20000000 DT_SIZE_K(256)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
|
|
@ -28,7 +28,7 @@
|
|||
};
|
||||
|
||||
sram1: memory@20000000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
|
|
@ -29,13 +29,13 @@
|
|||
#size-cells = <1>;
|
||||
|
||||
itcm: itcm@0 {
|
||||
compatible = "nxp,imx-itcm";
|
||||
compatible = "zephyr,memory-region", "nxp,imx-itcm";
|
||||
reg = <0x00000000 DT_SIZE_K(256)>;
|
||||
zephyr,memory-region = "ITCM";
|
||||
};
|
||||
|
||||
dtcm: dtcm@20000000 {
|
||||
compatible = "nxp,imx-dtcm";
|
||||
compatible = "zephyr,memory-region", "nxp,imx-dtcm";
|
||||
reg = <0x20000000 DT_SIZE_K(256)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
|
|
@ -549,7 +549,7 @@
|
|||
};
|
||||
|
||||
backup_sram: memory@40024000 {
|
||||
compatible = "st,stm32-backup-sram";
|
||||
compatible = "zephyr,memory-region", "st,stm32-backup-sram";
|
||||
reg = <0x40024000 DT_SIZE_K(4)>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
|
||||
label = "BACKUP_SRAM";
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
compatible = "zephyr,memory-region", "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(8)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
compatible = "zephyr,memory-region", "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(8)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
compatible = "zephyr,memory-region", "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(16)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
compatible = "zephyr,memory-region", "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(4)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
|
|
@ -250,7 +250,7 @@
|
|||
};
|
||||
|
||||
backup_sram: memory@40024000 {
|
||||
compatible = "st,stm32-backup-sram";
|
||||
compatible = "zephyr,memory-region", "st,stm32-backup-sram";
|
||||
reg = <0x40024000 DT_SIZE_K(4)>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
|
||||
label = "BACKUP_SRAM";
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
compatible = "zephyr,memory-region", "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
compatible = "zephyr,memory-region", "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
compatible = "zephyr,memory-region", "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
compatible = "zephyr,memory-region", "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
compatible = "zephyr,memory-region", "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
compatible = "zephyr,memory-region", "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
compatible = "zephyr,memory-region", "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
compatible = "zephyr,memory-region", "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
compatible = "zephyr,memory-region", "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
compatible = "zephyr,memory-region", "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
compatible = "zephyr,memory-region", "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
|
|
@ -100,7 +100,7 @@
|
|||
};
|
||||
|
||||
backup_sram: memory@40024000 {
|
||||
compatible = "st,stm32-backup-sram";
|
||||
compatible = "zephyr,memory-region", "st,stm32-backup-sram";
|
||||
reg = <0x40024000 DT_SIZE_K(4)>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
|
||||
label = "BACKUP_SRAM";
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
compatible = "zephyr,memory-region", "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
|
|
@ -737,7 +737,7 @@
|
|||
};
|
||||
|
||||
backup_sram: memory@40024000 {
|
||||
compatible = "st,stm32-backup-sram";
|
||||
compatible = "zephyr,memory-region", "st,stm32-backup-sram";
|
||||
reg = <0x40024000 DT_SIZE_K(4)>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
|
||||
label = "BACKUP_SRAM";
|
||||
|
|
|
@ -15,7 +15,7 @@
|
|||
};
|
||||
|
||||
dtcm: memory@20000000 {
|
||||
compatible = "arm,dtcm";
|
||||
compatible = "zephyr,memory-region", "arm,dtcm";
|
||||
reg = <0x20000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
|
|
@ -15,7 +15,7 @@
|
|||
};
|
||||
|
||||
dtcm: memory@20000000 {
|
||||
compatible = "arm,dtcm";
|
||||
compatible = "zephyr,memory-region", "arm,dtcm";
|
||||
reg = <0x20000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
|
|
@ -17,7 +17,7 @@
|
|||
};
|
||||
|
||||
dtcm: memory@20000000 {
|
||||
compatible = "arm,dtcm";
|
||||
compatible = "zephyr,memory-region", "arm,dtcm";
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
|
|
@ -871,7 +871,7 @@
|
|||
};
|
||||
|
||||
backup_sram: memory@38800000 {
|
||||
compatible = "st,stm32-backup-sram";
|
||||
compatible = "zephyr,memory-region", "st,stm32-backup-sram";
|
||||
reg = <0x38800000 DT_SIZE_K(4)>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x10000000>;
|
||||
label = "BACKUP_SRAM";
|
||||
|
|
|
@ -44,7 +44,7 @@
|
|||
|
||||
/* DTCM memory directly coppled to CPU */
|
||||
dtcm: memory@20000000 {
|
||||
compatible = "arm,dtcm";
|
||||
compatible = "zephyr,memory-region", "arm,dtcm";
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
|
|
@ -60,26 +60,26 @@
|
|||
/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
|
||||
sram1: memory@30000000 {
|
||||
reg = <0x30000000 DT_SIZE_K(16)>;
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
||||
/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
|
||||
sram2: memory@30040000 {
|
||||
reg = <0x30040000 DT_SIZE_K(16)>;
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
zephyr,memory-region = "SRAM2";
|
||||
};
|
||||
|
||||
/* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
|
||||
sram4: memory@38000000 {
|
||||
reg = <0x38000000 DT_SIZE_K(16)>;
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
zephyr,memory-region = "SRAM4";
|
||||
};
|
||||
|
||||
dtcm: memory@20000000 {
|
||||
compatible = "arm,dtcm";
|
||||
compatible = "zephyr,memory-region", "arm,dtcm";
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
|
|
@ -43,20 +43,20 @@
|
|||
/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
|
||||
sram1: memory@30000000 {
|
||||
reg = <0x30000000 DT_SIZE_K(128)>;
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
||||
/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
|
||||
sram2: memory@30020000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x30020000 DT_SIZE_K(128)>;
|
||||
zephyr,memory-region = "SRAM2";
|
||||
};
|
||||
|
||||
/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
|
||||
sram3: memory@30040000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x30040000 DT_SIZE_K(32)>;
|
||||
zephyr,memory-region = "SRAM3";
|
||||
};
|
||||
|
@ -64,12 +64,12 @@
|
|||
/* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
|
||||
sram4: memory@38000000 {
|
||||
reg = <0x38000000 DT_SIZE_K(64)>;
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
zephyr,memory-region = "SRAM4";
|
||||
};
|
||||
|
||||
dtcm: memory@20000000 {
|
||||
compatible = "arm,dtcm";
|
||||
compatible = "zephyr,memory-region", "arm,dtcm";
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
|
|
@ -40,20 +40,20 @@
|
|||
/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
|
||||
sram1: memory@30000000 {
|
||||
reg = <0x30000000 DT_SIZE_K(128)>;
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
||||
/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
|
||||
sram2: memory@30020000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x30020000 DT_SIZE_K(128)>;
|
||||
zephyr,memory-region = "SRAM2";
|
||||
};
|
||||
|
||||
/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
|
||||
sram3: memory@30040000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x30040000 DT_SIZE_K(32)>;
|
||||
zephyr,memory-region = "SRAM3";
|
||||
};
|
||||
|
@ -61,7 +61,7 @@
|
|||
/* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
|
||||
sram4: memory@38000000 {
|
||||
reg = <0x38000000 DT_SIZE_K(64)>;
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
zephyr,memory-region = "SRAM4";
|
||||
};
|
||||
};
|
||||
|
|
|
@ -15,7 +15,7 @@
|
|||
};
|
||||
|
||||
dtcm: memory@20000000 {
|
||||
compatible = "arm,dtcm";
|
||||
compatible = "zephyr,memory-region", "arm,dtcm";
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
|
|
@ -22,20 +22,20 @@
|
|||
/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
|
||||
sram1: memory@30000000 {
|
||||
reg = <0x30000000 DT_SIZE_K(128)>;
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
||||
/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
|
||||
sram2: memory@30020000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x30020000 DT_SIZE_K(128)>;
|
||||
zephyr,memory-region = "SRAM2";
|
||||
};
|
||||
|
||||
/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
|
||||
sram3: memory@30040000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x30040000 DT_SIZE_K(32)>;
|
||||
zephyr,memory-region = "SRAM3";
|
||||
};
|
||||
|
@ -43,12 +43,12 @@
|
|||
/* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
|
||||
sram4: memory@38000000 {
|
||||
reg = <0x38000000 DT_SIZE_K(64)>;
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
zephyr,memory-region = "SRAM4";
|
||||
};
|
||||
|
||||
dtcm: memory@20000000 {
|
||||
compatible = "arm,dtcm";
|
||||
compatible = "zephyr,memory-region", "arm,dtcm";
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
|
|
@ -29,41 +29,41 @@
|
|||
|
||||
/* System data RAM accessible over AXI bus: AXI SRAM2 in CD domain */
|
||||
sram1: memory@24040000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x24040000 DT_SIZE_K(384)>;
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
||||
/* System data RAM accessible over AXI bus: AXI SRAM3 in CD domain */
|
||||
sram2: memory@240A0000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x240A0000 DT_SIZE_K(384)>;
|
||||
zephyr,memory-region = "SRAM2";
|
||||
};
|
||||
|
||||
/* System data RAM accessible over AHB bus: SRAM1 in CD domain */
|
||||
sram3: memory@30000000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x30000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "SRAM3";
|
||||
};
|
||||
|
||||
/* System data RAM accessible over AHB bus: SRAM2 in CD domain */
|
||||
sram4: memory@30010000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x30010000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "SRAM4";
|
||||
};
|
||||
|
||||
/* System data RAM accessible over AHB bus: SRD SRAM in SRD domain */
|
||||
sram5: memory@38000000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x38000000 DT_SIZE_K(32)>;
|
||||
zephyr,memory-region = "SRAM5";
|
||||
};
|
||||
|
||||
dtcm: memory@20000000 {
|
||||
compatible = "arm,dtcm";
|
||||
compatible = "zephyr,memory-region", "arm,dtcm";
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
|
|
@ -34,13 +34,13 @@
|
|||
};
|
||||
|
||||
sram1: memory@20030000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x20030000 0x2800>;
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
||||
sram2: memory@20038000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x20038000 0x5000>;
|
||||
zephyr,memory-region = "SRAM2";
|
||||
};
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
|
||||
/* CCFG registers occupy the last 88 bytes of flash */
|
||||
ti_ccfg_partition: partition@57fa8 {
|
||||
compatible = "zephyr,memory-region";
|
||||
label = "ti_ccfg";
|
||||
reg = <0x57fa8 88>;
|
||||
zephyr,memory-region = "FLASH_CCFG";
|
||||
|
|
|
@ -30,7 +30,7 @@
|
|||
|
||||
/* VIMS RAM configurable in CCFG as GPRAM or cache for FLASH (default) */
|
||||
sram1: memory@11000000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x11000000 0x2000>;
|
||||
zephyr,memory-region = "SRAM1";
|
||||
};
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
|
||||
/* CCFG registers occupy the last 88 bytes of flash */
|
||||
ti_ccfg_partition: partition@57fa8 {
|
||||
compatible = "zephyr,memory-region";
|
||||
label = "ti_ccfg";
|
||||
reg = <0x57fa8 88>;
|
||||
zephyr,memory-region = "FLASH_CCFG";
|
||||
|
|
|
@ -13,13 +13,13 @@
|
|||
interrupt-parent = <&gic>;
|
||||
|
||||
ocm_low: memory@1000 {
|
||||
compatible = "xlnx,zynq-ocm";
|
||||
compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
|
||||
reg = <0x00001000 DT_SIZE_K(188)>;
|
||||
zephyr,memory-region = "OCM_LOW";
|
||||
};
|
||||
|
||||
ocm_high: memory@fffc0000 {
|
||||
compatible = "xlnx,zynq-ocm";
|
||||
compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
|
||||
reg = <0xFFFC0000 DT_SIZE_K(256)>;
|
||||
zephyr,memory-region = "OCM_HIGH";
|
||||
};
|
||||
|
|
|
@ -4,7 +4,7 @@ description: Cortex-M DTCM (Data Tightly Coupled Memory)
|
|||
|
||||
compatible: "arm,dtcm"
|
||||
|
||||
include: [base.yaml, mem-region.yaml]
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
|
|
|
@ -4,7 +4,7 @@ description: Cortex-M ITCM (Instruction Tightly Coupled Memory)
|
|||
|
||||
compatible: "arm,itcm"
|
||||
|
||||
include: [base.yaml, mem-region.yaml]
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
|
|
|
@ -5,7 +5,7 @@ description: i.MX DTCM (Data Tightly Coupled Memory)
|
|||
|
||||
compatible: "nxp,imx-dtcm"
|
||||
|
||||
include: [base.yaml, mem-region.yaml]
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
|
|
|
@ -5,7 +5,7 @@ description: i.MX ITCM (Instruction Tightly Coupled Memory)
|
|||
|
||||
compatible: "nxp,imx-itcm"
|
||||
|
||||
include: [base.yaml, mem-region.yaml]
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
|
|
|
@ -4,7 +4,7 @@ description: STM32 CCM (Core Coupled Memory)
|
|||
|
||||
compatible: "st,stm32-ccm"
|
||||
|
||||
include: [base.yaml, mem-region.yaml]
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
|
|
|
@ -4,7 +4,7 @@ description: Xilinx Zynq OCM (On-Chip Memory)
|
|||
|
||||
compatible: "xlnx,zynq-ocm"
|
||||
|
||||
include: [base.yaml, mem-region.yaml]
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
|
|
|
@ -1,11 +1,16 @@
|
|||
# Copyright (c) 2021, CSIRO
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
# Common fields for devices resulting in linker memory regions
|
||||
|
||||
description: Compatible for devices resulting in linker memory regions
|
||||
|
||||
compatible: "zephyr,memory-region"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
zephyr,memory-region:
|
||||
type: string
|
||||
required: false
|
||||
required: true
|
||||
description: |
|
||||
Signify that this node should result in a dedicated linker script
|
||||
memory region in the final executable. The region address and size
|
|
@ -9,7 +9,7 @@ description: |
|
|||
|
||||
compatible: "st,stm32-backup-sram"
|
||||
|
||||
include: [base.yaml, mem-region.yaml]
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
label:
|
||||
|
|
|
@ -56,14 +56,14 @@ description: |
|
|||
memory device/s in DeviceTree:
|
||||
|
||||
sdram1: sdram@c0000000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
device_type = "memory";
|
||||
reg = <0xc000000 DT_SIZE_M(X)>;
|
||||
zephyr,memory-region = "SDRAM1";
|
||||
};
|
||||
|
||||
sdram2: sdram@d0000000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
device_type = "memory";
|
||||
reg = <0xd000000 DT_SIZE_M(X)>;
|
||||
zephyr,memory-region = "SDRAM2";
|
||||
|
|
|
@ -28,12 +28,3 @@ child-binding:
|
|||
type: array
|
||||
description: register space
|
||||
required: true
|
||||
zephyr,memory-region:
|
||||
type: string
|
||||
required: false
|
||||
description: |
|
||||
Signify that this node should result in a dedicated linker script
|
||||
memory region in the final executable. The region address and size
|
||||
is taken from the <reg> property, while the name is the value of
|
||||
this property. This must only be added to memory-mapped partitions,
|
||||
not partitions on external flash.
|
||||
|
|
|
@ -5,7 +5,7 @@ description: Generic on-chip SRAM description
|
|||
|
||||
compatible: "mmio-sram"
|
||||
|
||||
include: [base.yaml, mem-region.yaml]
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
|
|
|
@ -81,7 +81,7 @@ MEMORY
|
|||
{
|
||||
FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
|
||||
SRAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
|
||||
LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_ocm), rw)
|
||||
LINKER_DT_REGIONS()
|
||||
/* Used by and documented in include/linker/intlist.ld */
|
||||
IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
|
||||
}
|
||||
|
|
|
@ -81,22 +81,7 @@ MEMORY
|
|||
{
|
||||
FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
|
||||
SRAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
|
||||
/* TI CCFG Registers */
|
||||
LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(ti_ccfg_partition), rwx)
|
||||
/* Data & Instruction Tightly Coupled Memory */
|
||||
LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_itcm), rw)
|
||||
LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_dtcm), rw)
|
||||
/* STM32 Core Coupled Memory */
|
||||
LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_ccm), rw)
|
||||
/* STM32WB IPC RAM */
|
||||
LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(sram1), rw)
|
||||
LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(sram2), rw)
|
||||
/* STM32 alternate RAM configurations */
|
||||
LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(sram3), rw)
|
||||
LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(sram4), rw)
|
||||
LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(sdram1), rw)
|
||||
LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(sdram2), rw)
|
||||
LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(backup_sram), rw)
|
||||
LINKER_DT_REGIONS()
|
||||
/* Used by and documented in include/linker/intlist.ld */
|
||||
IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
|
||||
}
|
||||
|
|
|
@ -81,9 +81,7 @@ MEMORY
|
|||
#endif
|
||||
RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
|
||||
|
||||
/* Data & Instruction Tightly Coupled Memory */
|
||||
LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_itcm), rw)
|
||||
LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_dtcm), rw)
|
||||
LINKER_DT_REGIONS()
|
||||
|
||||
/* Used by and documented in include/linker/intlist.ld */
|
||||
IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
|
||||
|
|
|
@ -37,27 +37,28 @@
|
|||
|
||||
/** @cond INTERNAL_HIDDEN */
|
||||
|
||||
#define _DT_COMPATIBLE zephyr_memory_region
|
||||
|
||||
/**
|
||||
* @brief Declare a memory region
|
||||
*
|
||||
* @param node_id devicetree node identifier
|
||||
* @param attr region attributes
|
||||
*/
|
||||
#define _REGION_DECLARE(node_id, attr) \
|
||||
LINKER_DT_NODE_REGION_NAME(node_id)(attr) : \
|
||||
ORIGIN = DT_REG_ADDR(node_id), \
|
||||
#define _REGION_DECLARE(node_id) \
|
||||
LINKER_DT_NODE_REGION_NAME(node_id) : \
|
||||
ORIGIN = DT_REG_ADDR(node_id), \
|
||||
LENGTH = DT_REG_SIZE(node_id)
|
||||
|
||||
/** @endcond */
|
||||
|
||||
/**
|
||||
* @brief Generate a linker memory region from a devicetree node
|
||||
* @brief Generate linker memory regions from the device tree nodes with
|
||||
* compatible 'zephyr,memory-region'
|
||||
*
|
||||
* @param node_id devicetree node identifier with a \<reg\> property defining
|
||||
* region location and size
|
||||
* @param attr region attributes to use (rx, rw, ...)
|
||||
* Note: for now we do not deal with MEMORY attributes since those are
|
||||
* optional, not actually used by Zephyr and they will likely conflict with the
|
||||
* MPU configuration.
|
||||
*/
|
||||
#define LINKER_DT_REGION_FROM_NODE(node_id, attr) \
|
||||
COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), \
|
||||
(_REGION_DECLARE(node_id, attr)), \
|
||||
())
|
||||
#define LINKER_DT_REGIONS() \
|
||||
DT_FOREACH_STATUS_OKAY(_DT_COMPATIBLE, _REGION_DECLARE)
|
||||
|
|
|
@ -87,9 +87,7 @@ MEMORY
|
|||
#endif
|
||||
RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
|
||||
|
||||
/* Data & Instruction Tightly Coupled Memory */
|
||||
LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_itcm), rw)
|
||||
LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_dtcm), rw)
|
||||
LINKER_DT_REGIONS()
|
||||
|
||||
/* Used by and documented in include/linker/intlist.ld */
|
||||
IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
|
||||
|
|
|
@ -17,7 +17,7 @@
|
|||
#size-cells = < 0x1 >;
|
||||
|
||||
test_sram1: sram@20000000 {
|
||||
compatible = "mmio-sram";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = < 0x20000000 0x1000 >;
|
||||
zephyr,memory-region = "SRAM_REGION";
|
||||
};
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue