michaelh/zephyr
1
0
Fork 0
Code Releases Activity

linker: Introduce zephyr,memory-region compatible

Browse source 
Introduce a new "zephyr,memory-region" compatible to be used when a new
memory region must be created in the linker script from the devicetree
nodes using the compatible.

Remove also the LINKER_DT_REGION_FROM_NODE macro and add a new
LINKER_DT_REGIONS macro to cycle through all the compatible regions.

In the same PR modify the DTS files and the linker scripts.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
Carlo Caione 2022-01-20 17:51:06 +01:00 • committed by Anas Nashif
commit 18ffcdcf74
75 changed files with 132 additions and 150 deletions
Download patch file Download diff file Expand all files Collapse all files

4
boards/arm/arty/arty_a7_arm_designstart_m1.dts
View file

@ -26,13 +26,13 @@
soc {
itcm: memory@0 {
compatible = "arm,itcm";
compatible = "zephyr,memory-region", "arm,itcm";
reg = <0x00000000 DT_SIZE_K(64)>;
zephyr,memory-region = "ITCM";
};
dtcm: memory@20000000 {
compatible = "arm,dtcm";
compatible = "zephyr,memory-region", "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(32)>;
zephyr,memory-region = "DTCM";
};

4
boards/arm/arty/arty_a7_arm_designstart_m3.dts
View file

@ -32,13 +32,13 @@
soc {
itcm: memory@0 {
compatible = "arm,itcm";
compatible = "zephyr,memory-region", "arm,itcm";
reg = <0x00000000 DT_SIZE_K(32)>;
zephyr,memory-region = "ITCM";
};
dtcm: memory@20000000 {
compatible = "arm,dtcm";
compatible = "zephyr,memory-region", "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(32)>;
zephyr,memory-region = "DTCM";
};

4
boards/arm/mps2_an521/mps2_an521.dts
View file

@ -80,13 +80,13 @@
*/
sram1: memory@10000000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x10000000 DT_SIZE_M(4)>;
zephyr,memory-region = "SRAM1";
};
sram2_3: memory@38000000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x38000000 DT_SIZE_M(4)>;
zephyr,memory-region = "SRAM2_3";
};

4
boards/arm/mps2_an521/mps2_an521_ns.dts
View file

@ -80,13 +80,13 @@
*/
sram1: memory@0 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x0 DT_SIZE_M(4)>;
zephyr,memory-region = "SRAM1";
};
sram2_3: memory@28000000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x28000000 DT_SIZE_M(4)>;
zephyr,memory-region = "SRAM2_3";
};

4
boards/arm/mps2_an521/mps2_an521_remote.dts
View file

@ -80,13 +80,13 @@
*/
sram1: memory@0 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x0 DT_SIZE_M(4)>;
zephyr,memory-region = "SRAM1";
};
sram2_3: memory@28000000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x28000000 DT_SIZE_M(4)>;
zephyr,memory-region = "SRAM2_3";
};

2
boards/arm/mps3_an547/mps3_an547.dts
View file

@ -108,6 +108,7 @@
* you'll get the non-secure alias
*/
itcm: itcm@10000000 { /* alias @ 0x0 */
compatible = "zephyr,memory-region";
reg = <0x10000000 DT_SIZE_K(512)>;
zephyr,memory-region = "ITCM";
};
@ -118,6 +119,7 @@
};
dtcm: dtcm@30000000 { /* alias @ 0x20000000 */
compatible = "zephyr,memory-region";
reg = <0x30000000 DT_SIZE_K(512)>;
zephyr,memory-region = "DTCM";
};

2
boards/arm/stm32f429i_disc1/stm32f429i_disc1.dts
View file

@ -22,7 +22,7 @@
};
sdram2: sdram@d0000000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
device_type = "memory";
reg = <0xd0000000 DT_SIZE_M(8)>;
zephyr,memory-region = "SDRAM2";

2
boards/arm/stm32f769i_disco/stm32f769i_disco.dts
View file

@ -23,7 +23,7 @@
};
sdram1: sdram@c0000000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
device_type = "memory";
reg = <0xc0000000 DT_SIZE_M(16)>;
zephyr,memory-region = "SDRAM1";

2
boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts
View file

@ -22,7 +22,7 @@
};
sdram2: sdram@d0000000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
device_type = "memory";
reg = <0xd0000000 DT_SIZE_M(32)>;
zephyr,memory-region = "SDRAM2";

2
dts/arm/atmel/sam4l.dtsi
View file

@ -46,7 +46,7 @@
* exclusive for USB descriptors
*/
sram1: memory@21000000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x21000000 DT_SIZE_K(4)>;
zephyr,memory-region = "SRAM1";
};

4
dts/arm/cypress/psoc6.dtsi
View file

@ -57,13 +57,13 @@
};
sram1: memory@8023000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x08023000 DT_SIZE_K(4)>;
zephyr,memory-region = "SRAM1";
};
sram2: memory@8024000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x08024000 DT_SIZE_K(112)>;
zephyr,memory-region = "SRAM2";
};

2
dts/arm/nordic/nrf5340_cpunet.dtsi
View file

@ -49,7 +49,7 @@
};
sram1: memory@21000000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "SRAM1";
};

4
dts/arm/nxp/nxp_lpc11u6x.dtsi
View file

@ -24,13 +24,13 @@
};
sram1:memory@20000000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20000000 0x800>;
zephyr,memory-region = "SRAM1";
};
sram2:memory@20004000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20004000 0x800>;
zephyr,memory-region = "SRAM2";
};

4
dts/arm/nxp/nxp_lpc54xxx.dtsi
View file

@ -50,13 +50,13 @@
};
sram1:memory@20010000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20010000 DT_SIZE_K(64)>;
zephyr,memory-region = "SRAM1";
};
sram2:memory@20020000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20020000 DT_SIZE_K(32)>;
zephyr,memory-region = "SRAM2";
};

6
dts/arm/nxp/nxp_lpc55S1x_common.dtsi
View file

@ -45,20 +45,20 @@
};
sram1: memory@20008000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20008000 DT_SIZE_K(16)>;
zephyr,memory-region = "SRAM1";
};
sram2: memory@2000c000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x2000c000 DT_SIZE_K(16)>;
zephyr,memory-region = "SRAM2";
};
sram4: memory@20010000 {
/* Conencted to USB bus*/
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20010000 DT_SIZE_K(16)>;
zephyr,memory-region = "SRAM4";
};

6
dts/arm/nxp/nxp_lpc55S2x_common.dtsi
View file

@ -53,19 +53,19 @@
};
sram1: memory@20010000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20010000 DT_SIZE_K(64)>;
zephyr,memory-region = "SRAM1";
};
sram2: memory@20020000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20020000 DT_SIZE_K(64)>;
zephyr,memory-region = "SRAM2";
};
sram4: memory@20040000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20040000 DT_SIZE_K(16)>;
zephyr,memory-region = "SRAM4";
};

8
dts/arm/nxp/nxp_lpc55S6x_common.dtsi
View file

@ -57,25 +57,25 @@
};
sram1: memory@20010000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20010000 DT_SIZE_K(32)>;
zephyr,memory-region = "SRAM1";
};
sram2: memory@20018000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20018000 DT_SIZE_K(32)>;
zephyr,memory-region = "SRAM2";
};
sram3: memory@20020000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20020000 DT_SIZE_K(32)>;
zephyr,memory-region = "SRAM3";
};
sram4: memory@40100000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x40100000 DT_SIZE_K(16)>;
zephyr,memory-region = "SRAM4";
};

4
dts/arm/nxp/nxp_rt.dtsi
View file

@ -50,13 +50,13 @@
#size-cells = <1>;
itcm: itcm@0 {
compatible = "nxp,imx-itcm";
compatible = "zephyr,memory-region", "nxp,imx-itcm";
reg = <0x00000000 DT_SIZE_K(128)>;
zephyr,memory-region = "ITCM";
};
dtcm: dtcm@20000000 {
compatible = "nxp,imx-dtcm";
compatible = "zephyr,memory-region", "nxp,imx-dtcm";
reg = <0x20000000 DT_SIZE_K(128)>;
zephyr,memory-region = "DTCM";
};

2
dts/arm/nxp/nxp_rt1160_cm4.dtsi
View file

@ -28,7 +28,7 @@
};
sram1: memory@20000000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20000000 DT_SIZE_K(128)>;
zephyr,memory-region = "SRAM1";
};

4
dts/arm/nxp/nxp_rt1160_cm7.dtsi
View file

@ -29,13 +29,13 @@
#size-cells = <1>;
itcm: itcm@0 {
compatible = "nxp,imx-itcm";
compatible = "zephyr,memory-region", "nxp,imx-itcm";
reg = <0x00000000 DT_SIZE_K(256)>;
zephyr,memory-region = "ITCM";
};
dtcm: dtcm@20000000 {
compatible = "nxp,imx-dtcm";
compatible = "zephyr,memory-region", "nxp,imx-dtcm";
reg = <0x20000000 DT_SIZE_K(256)>;
zephyr,memory-region = "DTCM";
};

2
dts/arm/nxp/nxp_rt1170_cm4.dtsi
View file

@ -28,7 +28,7 @@
};
sram1: memory@20000000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20000000 DT_SIZE_K(128)>;
zephyr,memory-region = "SRAM1";
};

4
dts/arm/nxp/nxp_rt1170_cm7.dtsi
View file

@ -29,13 +29,13 @@
#size-cells = <1>;
itcm: itcm@0 {
compatible = "nxp,imx-itcm";
compatible = "zephyr,memory-region", "nxp,imx-itcm";
reg = <0x00000000 DT_SIZE_K(256)>;
zephyr,memory-region = "ITCM";
};
dtcm: dtcm@20000000 {
compatible = "nxp,imx-dtcm";
compatible = "zephyr,memory-region", "nxp,imx-dtcm";
reg = <0x20000000 DT_SIZE_K(256)>;
zephyr,memory-region = "DTCM";
};

2
dts/arm/st/f2/stm32f2.dtsi
View file

@ -549,7 +549,7 @@
};
backup_sram: memory@40024000 {
compatible = "st,stm32-backup-sram";
compatible = "zephyr,memory-region", "st,stm32-backup-sram";
reg = <0x40024000 DT_SIZE_K(4)>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
label = "BACKUP_SRAM";

2
dts/arm/st/f3/stm32f303X8.dtsi
View file

@ -9,7 +9,7 @@
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
compatible = "zephyr,memory-region", "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(8)>;
zephyr,memory-region = "CCM";
};

2
dts/arm/st/f3/stm32f303Xc.dtsi
View file

@ -9,7 +9,7 @@
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
compatible = "zephyr,memory-region", "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(8)>;
zephyr,memory-region = "CCM";
};

2
dts/arm/st/f3/stm32f303Xe.dtsi
View file

@ -9,7 +9,7 @@
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
compatible = "zephyr,memory-region", "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(16)>;
zephyr,memory-region = "CCM";
};

2
dts/arm/st/f3/stm32f334X8.dtsi
View file

@ -9,7 +9,7 @@
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
compatible = "zephyr,memory-region", "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(4)>;
zephyr,memory-region = "CCM";
};

2
dts/arm/st/f4/stm32f405.dtsi
View file

@ -250,7 +250,7 @@
};
backup_sram: memory@40024000 {
compatible = "st,stm32-backup-sram";
compatible = "zephyr,memory-region", "st,stm32-backup-sram";
reg = <0x40024000 DT_SIZE_K(4)>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
label = "BACKUP_SRAM";

2
dts/arm/st/f4/stm32f405Xg.dtsi
View file

@ -9,7 +9,7 @@
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
compatible = "zephyr,memory-region", "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};

2
dts/arm/st/f4/stm32f407Xe.dtsi
View file

@ -9,7 +9,7 @@
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
compatible = "zephyr,memory-region", "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};

2
dts/arm/st/f4/stm32f407Xg.dtsi
View file

@ -9,7 +9,7 @@
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
compatible = "zephyr,memory-region", "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};

2
dts/arm/st/f4/stm32f415Rg.dtsi
View file

@ -9,7 +9,7 @@
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
compatible = "zephyr,memory-region", "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};

2
dts/arm/st/f4/stm32f417Xe.dtsi
View file

@ -9,7 +9,7 @@
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
compatible = "zephyr,memory-region", "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};

2
dts/arm/st/f4/stm32f417Xg.dtsi
View file

@ -9,7 +9,7 @@
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
compatible = "zephyr,memory-region", "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};

2
dts/arm/st/f4/stm32f427Xi.dtsi
View file

@ -9,7 +9,7 @@
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
compatible = "zephyr,memory-region", "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};

2
dts/arm/st/f4/stm32f427vi.dtsi
View file

@ -9,7 +9,7 @@
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
compatible = "zephyr,memory-region", "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};

2
dts/arm/st/f4/stm32f429Xi.dtsi
View file

@ -9,7 +9,7 @@
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
compatible = "zephyr,memory-region", "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};

2
dts/arm/st/f4/stm32f429vi.dtsi
View file

@ -9,7 +9,7 @@
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
compatible = "zephyr,memory-region", "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};

2
dts/arm/st/f4/stm32f437Xi.dtsi
View file

@ -9,7 +9,7 @@
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
compatible = "zephyr,memory-region", "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};

2
dts/arm/st/f4/stm32f446.dtsi
View file

@ -100,7 +100,7 @@
};
backup_sram: memory@40024000 {
compatible = "st,stm32-backup-sram";
compatible = "zephyr,memory-region", "st,stm32-backup-sram";
reg = <0x40024000 DT_SIZE_K(4)>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
label = "BACKUP_SRAM";

2
dts/arm/st/f4/stm32f469Xi.dtsi
View file

@ -9,7 +9,7 @@
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
compatible = "zephyr,memory-region", "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};

2
dts/arm/st/f7/stm32f7.dtsi
View file

@ -737,7 +737,7 @@
};
backup_sram: memory@40024000 {
compatible = "st,stm32-backup-sram";
compatible = "zephyr,memory-region", "st,stm32-backup-sram";
reg = <0x40024000 DT_SIZE_K(4)>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
label = "BACKUP_SRAM";

2
dts/arm/st/f7/stm32f723.dtsi
View file

@ -15,7 +15,7 @@
};
dtcm: memory@20000000 {
compatible = "arm,dtcm";
compatible = "zephyr,memory-region", "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(64)>;
zephyr,memory-region = "DTCM";
};

2
dts/arm/st/f7/stm32f745.dtsi
View file

@ -15,7 +15,7 @@
};
dtcm: memory@20000000 {
compatible = "arm,dtcm";
compatible = "zephyr,memory-region", "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(64)>;
zephyr,memory-region = "DTCM";
};

2
dts/arm/st/f7/stm32f767.dtsi
View file

@ -17,7 +17,7 @@
};
dtcm: memory@20000000 {
compatible = "arm,dtcm";
compatible = "zephyr,memory-region", "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(128)>;
zephyr,memory-region = "DTCM";
};

2
dts/arm/st/h7/stm32h7.dtsi
View file

@ -871,7 +871,7 @@
};
backup_sram: memory@38800000 {
compatible = "st,stm32-backup-sram";
compatible = "zephyr,memory-region", "st,stm32-backup-sram";
reg = <0x38800000 DT_SIZE_K(4)>;
clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x10000000>;
label = "BACKUP_SRAM";

2
dts/arm/st/h7/stm32h723.dtsi
View file

@ -44,7 +44,7 @@
/* DTCM memory directly coppled to CPU */
dtcm: memory@20000000 {
compatible = "arm,dtcm";
compatible = "zephyr,memory-region", "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(128)>;
zephyr,memory-region = "DTCM";
};

8
dts/arm/st/h7/stm32h735.dtsi
View file

@ -60,26 +60,26 @@
/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
sram1: memory@30000000 {
reg = <0x30000000 DT_SIZE_K(16)>;
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "SRAM1";
};
/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
sram2: memory@30040000 {
reg = <0x30040000 DT_SIZE_K(16)>;
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "SRAM2";
};
/* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
sram4: memory@38000000 {
reg = <0x38000000 DT_SIZE_K(16)>;
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "SRAM4";
};
dtcm: memory@20000000 {
compatible = "arm,dtcm";
compatible = "zephyr,memory-region", "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(128)>;
zephyr,memory-region = "DTCM";
};

10
dts/arm/st/h7/stm32h743.dtsi
View file

@ -43,20 +43,20 @@
/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
sram1: memory@30000000 {
reg = <0x30000000 DT_SIZE_K(128)>;
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "SRAM1";
};
/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
sram2: memory@30020000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x30020000 DT_SIZE_K(128)>;
zephyr,memory-region = "SRAM2";
};
/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
sram3: memory@30040000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x30040000 DT_SIZE_K(32)>;
zephyr,memory-region = "SRAM3";
};
@ -64,12 +64,12 @@
/* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
sram4: memory@38000000 {
reg = <0x38000000 DT_SIZE_K(64)>;
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "SRAM4";
};
dtcm: memory@20000000 {
compatible = "arm,dtcm";
compatible = "zephyr,memory-region", "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(128)>;
zephyr,memory-region = "DTCM";
};

8
dts/arm/st/h7/stm32h745.dtsi
View file

@ -40,20 +40,20 @@
/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
sram1: memory@30000000 {
reg = <0x30000000 DT_SIZE_K(128)>;
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "SRAM1";
};
/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
sram2: memory@30020000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x30020000 DT_SIZE_K(128)>;
zephyr,memory-region = "SRAM2";
};
/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
sram3: memory@30040000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x30040000 DT_SIZE_K(32)>;
zephyr,memory-region = "SRAM3";
};
@ -61,7 +61,7 @@
/* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
sram4: memory@38000000 {
reg = <0x38000000 DT_SIZE_K(64)>;
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "SRAM4";
};
};

2
dts/arm/st/h7/stm32h745Xi_m7.dtsi
View file

@ -15,7 +15,7 @@
};
dtcm: memory@20000000 {
compatible = "arm,dtcm";
compatible = "zephyr,memory-region", "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(128)>;
zephyr,memory-region = "DTCM";
};

10
dts/arm/st/h7/stm32h750.dtsi
View file

@ -22,20 +22,20 @@
/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
sram1: memory@30000000 {
reg = <0x30000000 DT_SIZE_K(128)>;
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "SRAM1";
};
/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
sram2: memory@30020000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x30020000 DT_SIZE_K(128)>;
zephyr,memory-region = "SRAM2";
};
/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
sram3: memory@30040000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x30040000 DT_SIZE_K(32)>;
zephyr,memory-region = "SRAM3";
};
@ -43,12 +43,12 @@
/* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
sram4: memory@38000000 {
reg = <0x38000000 DT_SIZE_K(64)>;
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "SRAM4";
};
dtcm: memory@20000000 {
compatible = "arm,dtcm";
compatible = "zephyr,memory-region", "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(128)>;
zephyr,memory-region = "DTCM";
};

12
dts/arm/st/h7/stm32h7a3.dtsi
View file

@ -29,41 +29,41 @@
/* System data RAM accessible over AXI bus: AXI SRAM2 in CD domain */
sram1: memory@24040000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x24040000 DT_SIZE_K(384)>;
zephyr,memory-region = "SRAM1";
};
/* System data RAM accessible over AXI bus: AXI SRAM3 in CD domain */
sram2: memory@240A0000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x240A0000 DT_SIZE_K(384)>;
zephyr,memory-region = "SRAM2";
};
/* System data RAM accessible over AHB bus: SRAM1 in CD domain */
sram3: memory@30000000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x30000000 DT_SIZE_K(64)>;
zephyr,memory-region = "SRAM3";
};
/* System data RAM accessible over AHB bus: SRAM2 in CD domain */
sram4: memory@30010000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x30010000 DT_SIZE_K(64)>;
zephyr,memory-region = "SRAM4";
};
/* System data RAM accessible over AHB bus: SRD SRAM in SRD domain */
sram5: memory@38000000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x38000000 DT_SIZE_K(32)>;
zephyr,memory-region = "SRAM5";
};
dtcm: memory@20000000 {
compatible = "arm,dtcm";
compatible = "zephyr,memory-region", "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(128)>;
zephyr,memory-region = "DTCM";
};

4
dts/arm/st/wb/stm32wb.dtsi
View file

@ -34,13 +34,13 @@
};
sram1: memory@20030000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20030000 0x2800>;
zephyr,memory-region = "SRAM1";
};
sram2: memory@20038000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20038000 0x5000>;
zephyr,memory-region = "SRAM2";
};

1
dts/arm/ti/cc1352r.dtsi
View file

@ -22,6 +22,7 @@
/* CCFG registers occupy the last 88 bytes of flash */
ti_ccfg_partition: partition@57fa8 {
compatible = "zephyr,memory-region";
label = "ti_ccfg";
reg = <0x57fa8 88>;
zephyr,memory-region = "FLASH_CCFG";

2
dts/arm/ti/cc13x2_cc26x2.dtsi
View file

@ -30,7 +30,7 @@
/* VIMS RAM configurable in CCFG as GPRAM or cache for FLASH (default) */
sram1: memory@11000000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x11000000 0x2000>;
zephyr,memory-region = "SRAM1";
};

1
dts/arm/ti/cc2652r.dtsi
View file

@ -22,6 +22,7 @@
/* CCFG registers occupy the last 88 bytes of flash */
ti_ccfg_partition: partition@57fa8 {
compatible = "zephyr,memory-region";
label = "ti_ccfg";
reg = <0x57fa8 88>;
zephyr,memory-region = "FLASH_CCFG";

4
dts/arm/xilinx/zynq7000.dtsi
View file

@ -13,13 +13,13 @@
interrupt-parent = <&gic>;
ocm_low: memory@1000 {
compatible = "xlnx,zynq-ocm";
compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
reg = <0x00001000 DT_SIZE_K(188)>;
zephyr,memory-region = "OCM_LOW";
};
ocm_high: memory@fffc0000 {
compatible = "xlnx,zynq-ocm";
compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
reg = <0xFFFC0000 DT_SIZE_K(256)>;
zephyr,memory-region = "OCM_HIGH";
};

2
dts/bindings/arm/arm,dtcm.yaml
View file

@ -4,7 +4,7 @@ description: Cortex-M DTCM (Data Tightly Coupled Memory)
compatible: "arm,dtcm"
include: [base.yaml, mem-region.yaml]
include: base.yaml
properties:
reg:

2
dts/bindings/arm/arm,itcm.yaml
View file

@ -4,7 +4,7 @@ description: Cortex-M ITCM (Instruction Tightly Coupled Memory)
compatible: "arm,itcm"
include: [base.yaml, mem-region.yaml]
include: base.yaml
properties:
reg:

2
dts/bindings/arm/nxp,imx-dtcm.yaml
View file

@ -5,7 +5,7 @@ description: i.MX DTCM (Data Tightly Coupled Memory)
compatible: "nxp,imx-dtcm"
include: [base.yaml, mem-region.yaml]
include: base.yaml
properties:
reg:

2
dts/bindings/arm/nxp,imx-itcm.yaml
View file

@ -5,7 +5,7 @@ description: i.MX ITCM (Instruction Tightly Coupled Memory)
compatible: "nxp,imx-itcm"
include: [base.yaml, mem-region.yaml]
include: base.yaml
properties:
reg:

2
dts/bindings/arm/st,stm32-ccm.yaml
View file

@ -4,7 +4,7 @@ description: STM32 CCM (Core Coupled Memory)
compatible: "st,stm32-ccm"
include: [base.yaml, mem-region.yaml]
include: base.yaml
properties:
reg:

2
dts/bindings/arm/xlnx,zynq-ocm.yaml
View file

@ -4,7 +4,7 @@ description: Xilinx Zynq OCM (On-Chip Memory)
compatible: "xlnx,zynq-ocm"
include: [base.yaml, mem-region.yaml]
include: base.yaml
properties:
reg:

9
dts/bindings/base/mem-region.yaml → dts/bindings/base/zephyr,memory-region.yaml
View file

@ -1,11 +1,16 @@
# Copyright (c) 2021, CSIRO
# SPDX-License-Identifier: Apache-2.0
# Common fields for devices resulting in linker memory regions
description: Compatible for devices resulting in linker memory regions
compatible: "zephyr,memory-region"
include: base.yaml
properties:
zephyr,memory-region:
type: string
required: false
required: true
description: |
Signify that this node should result in a dedicated linker script
memory region in the final executable. The region address and size

2
dts/bindings/memory-controllers/st,stm32-backup-sram.yaml
View file

@ -9,7 +9,7 @@ description: |
compatible: "st,stm32-backup-sram"
include: [base.yaml, mem-region.yaml]
include: base.yaml
properties:
label:

4
dts/bindings/memory-controllers/st,stm32-fmc-sdram.yaml
View file

@ -56,14 +56,14 @@ description: |
memory device/s in DeviceTree:
sdram1: sdram@c0000000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
device_type = "memory";
reg = <0xc000000 DT_SIZE_M(X)>;
zephyr,memory-region = "SDRAM1";
};
sdram2: sdram@d0000000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
device_type = "memory";
reg = <0xd000000 DT_SIZE_M(X)>;
zephyr,memory-region = "SDRAM2";

9
dts/bindings/mtd/fixed-partitions.yaml
View file

@ -28,12 +28,3 @@ child-binding:
type: array
description: register space
required: true
zephyr,memory-region:
type: string
required: false
description: |
Signify that this node should result in a dedicated linker script
memory region in the final executable. The region address and size
is taken from the <reg> property, while the name is the value of
this property. This must only be added to memory-mapped partitions,
not partitions on external flash.

2
dts/bindings/sram/mmio-sram.yaml
View file

@ -5,7 +5,7 @@ description: Generic on-chip SRAM description
compatible: "mmio-sram"
include: [base.yaml, mem-region.yaml]
include: base.yaml
properties:
reg:

2
include/arch/arm/aarch32/cortex_a_r/scripts/linker.ld
View file

@ -81,7 +81,7 @@ MEMORY
{
FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
SRAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_ocm), rw)
LINKER_DT_REGIONS()
/* Used by and documented in include/linker/intlist.ld */
IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
}

17
include/arch/arm/aarch32/cortex_m/scripts/linker.ld
View file

@ -81,22 +81,7 @@ MEMORY
{
FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
SRAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
/* TI CCFG Registers */
LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(ti_ccfg_partition), rwx)
/* Data & Instruction Tightly Coupled Memory */
LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_itcm), rw)
LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_dtcm), rw)
/* STM32 Core Coupled Memory */
LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_ccm), rw)
/* STM32WB IPC RAM */
LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(sram1), rw)
LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(sram2), rw)
/* STM32 alternate RAM configurations */
LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(sram3), rw)
LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(sram4), rw)
LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(sdram1), rw)
LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(sdram2), rw)
LINKER_DT_REGION_FROM_NODE(DT_NODELABEL(backup_sram), rw)
LINKER_DT_REGIONS()
/* Used by and documented in include/linker/intlist.ld */
IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
}

4
include/arch/riscv/common/linker.ld
View file

@ -81,9 +81,7 @@ MEMORY
#endif
RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
/* Data & Instruction Tightly Coupled Memory */
LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_itcm), rw)
LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_dtcm), rw)
LINKER_DT_REGIONS()
/* Used by and documented in include/linker/intlist.ld */
IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K

23
include/linker/devicetree_regions.h
View file

@ -37,27 +37,28 @@
/** @cond INTERNAL_HIDDEN */
#define _DT_COMPATIBLE zephyr_memory_region
/**
* @brief Declare a memory region
*
* @param node_id devicetree node identifier
* @param attr region attributes
*/
#define _REGION_DECLARE(node_id, attr) \
LINKER_DT_NODE_REGION_NAME(node_id)(attr) : \
ORIGIN = DT_REG_ADDR(node_id), \
#define _REGION_DECLARE(node_id) \
LINKER_DT_NODE_REGION_NAME(node_id) : \
ORIGIN = DT_REG_ADDR(node_id), \
LENGTH = DT_REG_SIZE(node_id)
/** @endcond */
/**
* @brief Generate a linker memory region from a devicetree node
* @brief Generate linker memory regions from the device tree nodes with
* compatible 'zephyr,memory-region'
*
* @param node_id devicetree node identifier with a \<reg\> property defining
* region location and size
* @param attr region attributes to use (rx, rw, ...)
* Note: for now we do not deal with MEMORY attributes since those are
* optional, not actually used by Zephyr and they will likely conflict with the
* MPU configuration.
*/
#define LINKER_DT_REGION_FROM_NODE(node_id, attr) \
COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), \
(_REGION_DECLARE(node_id, attr)), \
())
#define LINKER_DT_REGIONS() \
DT_FOREACH_STATUS_OKAY(_DT_COMPATIBLE, _REGION_DECLARE)

4
soc/riscv/riscv-privilege/andes_v5/ae350/linker.ld
View file

@ -87,9 +87,7 @@ MEMORY
#endif
RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
/* Data & Instruction Tightly Coupled Memory */
LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_itcm), rw)
LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_dtcm), rw)
LINKER_DT_REGIONS()
/* Used by and documented in include/linker/intlist.ld */
IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K

2
tests/lib/devicetree/api_ext/app.overlay
View file

@ -17,7 +17,7 @@
#size-cells = < 0x1 >;
test_sram1: sram@20000000 {
compatible = "mmio-sram";
compatible = "zephyr,memory-region", "mmio-sram";
reg = < 0x20000000 0x1000 >;
zephyr,memory-region = "SRAM_REGION";
};