arm/arm64: Make ARM64 a standalone architecture
Split ARM and ARM64 architectures. Details: - CONFIG_ARM64 is decoupled from CONFIG_ARM (not a subset anymore) - Arch and include AArch64 files are in a dedicated directory (arch/arm64 and include/arch/arm64) - AArch64 boards and SoC are moved to soc/arm64 and boards/arm64 - AArch64-specific DTS files are moved to dts/arm64 - The A72 support for the bcm_vk/viper board is moved in the boards/bcm_vk/viper directory Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
parent
a1c0821b46
commit
3539c2fbb3
147 changed files with 595 additions and 189 deletions
24
arch/Kconfig
24
arch/Kconfig
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@ -32,11 +32,23 @@ config ARM
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select HAS_DTS
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# FIXME: current state of the code for all ARM requires this, but
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# is really only necessary for Cortex-M with ARM MPU!
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select GEN_PRIV_STACKS if !ARM64
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select ARCH_HAS_THREAD_LOCAL_STORAGE if ARM64 || CPU_CORTEX_R || CPU_CORTEX_M
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select GEN_PRIV_STACKS
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select ARCH_HAS_THREAD_LOCAL_STORAGE if CPU_CORTEX_R || CPU_CORTEX_M
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help
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ARM architecture
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config ARM64
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bool
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select ARCH_IS_SET
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select 64BIT
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select HAS_DTS
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select HAS_ARM_SMCCC
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select ARCH_HAS_THREAD_LOCAL_STORAGE
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select USE_SWITCH
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select USE_SWITCH_SUPPORTED
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help
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ARM64 (AArch64) architecture
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config SPARC
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bool
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select ARCH_IS_SET
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@ -162,14 +174,14 @@ config SRAM_BASE_ADDRESS
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/chosen/zephyr,sram in devicetree. The user should generally avoid
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changing it via menuconfig or in configuration files.
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if ARC || ARM || NIOS2 || X86
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if ARC || ARM || ARM64 || NIOS2 || X86
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# Workaround for not being able to have commas in macro arguments
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DT_CHOSEN_Z_FLASH := zephyr,flash
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config FLASH_SIZE
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int "Flash Size in kB"
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default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) if (XIP && ARM) || !ARM
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default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) if (XIP && (ARM ||ARM64)) || !ARM
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help
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This option specifies the size of the flash in kB. It is normally set by
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the board's defconfig file and the user should generally avoid modifying
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@ -177,13 +189,13 @@ config FLASH_SIZE
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config FLASH_BASE_ADDRESS
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hex "Flash Base Address"
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) if (XIP && ARM) || !ARM
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) if (XIP && (ARM || ARM64)) || !ARM
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help
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This option specifies the base address of the flash on the board. It is
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normally set by the board's defconfig file and the user should generally
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avoid modifying it via the menu configuration.
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endif # ARM || ARC || NIOS2 || X86
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endif # ARM || ARM64 || ARC || NIOS2 || X86
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if ARCH_HAS_TRUSTED_EXECUTION
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@ -1,11 +1,5 @@
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# SPDX-License-Identifier: Apache-2.0
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if(CONFIG_ARM64)
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set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf64-littleaarch64)
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set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-littlearm)
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add_subdirectory(core/aarch64)
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else()
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set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-littlearm)
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add_subdirectory(core/aarch32)
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endif()
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add_subdirectory(core/aarch32)
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@ -9,10 +9,6 @@ menu "ARM Options"
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config ARCH
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default "arm"
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config ARM64
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bool
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select 64BIT
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config CPU_CORTEX
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bool
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help
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@ -38,18 +34,6 @@ config ARM_CUSTOM_INTERRUPT_CONTROLLER
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family cores. The Cortex-M family cores are always equipped with
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the ARM Nested Vectored Interrupt Controller (NVIC).
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config HAS_ARM_SMCCC
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bool
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help
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Include support for the Secure Monitor Call (SMC) and Hypervisor
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Call (HVC) instructions on Armv7 and above architectures.
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if !ARM64
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rsource "core/aarch32/Kconfig"
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endif
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if ARM64
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rsource "core/aarch64/Kconfig"
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endif
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endmenu
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@ -6,10 +6,6 @@
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#include <gen_offset.h>
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#if defined(CONFIG_ARM64)
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#include "offsets_aarch64.c"
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#else
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#include "offsets_aarch32.c"
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#endif
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GEN_ABS_SYM_END
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@ -30,8 +30,6 @@
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#elif defined(CONFIG_CPU_CORTEX_R)
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#include <aarch32/cortex_a_r/stack.h>
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#include <aarch32/cortex_a_r/exc.h>
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#elif defined(CONFIG_CPU_CORTEX_A)
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#include <aarch64/exc.h>
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#endif
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#ifndef _ASMLANGUAGE
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@ -7,10 +7,6 @@
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#ifndef ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_FUNC_H_
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#define ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_FUNC_H_
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#if defined(CONFIG_ARM64)
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#include <aarch64/kernel_arch_func.h>
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#else
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#include <aarch32/kernel_arch_func.h>
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#endif
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#endif /* ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_FUNC_H_ */
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@ -7,10 +7,6 @@
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#ifndef ZEPHYR_ARCH_ARM_INCLUDE_OFFSETS_SHORT_ARCH_H_
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#define ZEPHYR_ARCH_ARM_INCLUDE_OFFSETS_SHORT_ARCH_H_
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#if defined(CONFIG_ARM64)
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#include <aarch64/offsets_short_arch.h>
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#else
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#include <aarch32/offsets_short_arch.h>
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#endif
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#endif /* ZEPHYR_ARCH_ARM_INCLUDE_OFFSETS_SHORT_ARCH_H_ */
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5
arch/arm64/CMakeLists.txt
Normal file
5
arch/arm64/CMakeLists.txt
Normal file
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@ -0,0 +1,5 @@
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# SPDX-License-Identifier: Apache-2.0
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set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf64-littleaarch64)
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add_subdirectory(core)
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34
arch/arm64/Kconfig
Normal file
34
arch/arm64/Kconfig
Normal file
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@ -0,0 +1,34 @@
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# ARM64 architecture configuration options
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# Copyright (c) 2014-2015 Wind River Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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menu "ARM64 Options"
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depends on ARM64
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config ARCH
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default "arm64"
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config CPU_CORTEX
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bool
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help
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This option signifies the use of a CPU of the Cortex family.
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config ARM_CUSTOM_INTERRUPT_CONTROLLER
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bool
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help
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This option indicates that the ARM CPU is connected to a custom (i.e.
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non-GIC) interrupt controller.
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A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, ...)
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allow interfacing to a custom external interrupt controller and this
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option must be selected when such cores are connected to an interrupt
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controller that is not the ARM Generic Interrupt Controller (GIC).
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When this option is selected, the architecture interrupt control
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functions are mapped to the SoC interrupt control interface, which is
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implemented at the SoC level.
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rsource "core/Kconfig"
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endmenu
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@ -23,7 +23,7 @@ zephyr_library_sources(
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zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
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zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S)
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zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
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zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE ../common/tls.c)
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zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c)
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zephyr_library_sources_ifdef(CONFIG_HAS_ARM_SMCCC smccc-call.S)
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zephyr_library_sources_ifdef(CONFIG_AARCH64_IMAGE_HEADER header.S)
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@ -7,9 +7,6 @@ config CPU_CORTEX_A
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bool
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select CPU_CORTEX
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select HAS_FLASH_LOAD_OFFSET
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select USE_SWITCH
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select USE_SWITCH_SUPPORTED
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select HAS_ARM_SMCCC
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select SCHED_IPI_SUPPORTED if SMP
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help
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This option signifies the use of a CPU of the Cortex-A family.
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@ -28,6 +25,12 @@ config CPU_CORTEX_A72
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help
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This option signifies the use of a Cortex-A72 CPU
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config HAS_ARM_SMCCC
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bool
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help
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Include support for the Secure Monitor Call (SMC) and Hypervisor
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Call (HVC) instructions on Armv7 and above architectures.
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config NUM_IRQS
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int
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@ -29,7 +29,7 @@ void z_arm64_fatal_error(unsigned int reason, z_arch_esf_t *esf);
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* When a custom interrupt controller is used (i.e.
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* CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER is enabled), the architecture
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* interrupt control functions are mapped to the SoC layer in
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* `include/arch/arm/aarch64/irq.h`.
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* `include/arch/arm64/irq.h`.
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*/
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void arch_irq_enable(unsigned int irq)
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@ -11,7 +11,7 @@
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#include <kernel.h>
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#include <irq_offload.h>
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#include <aarch64/exc.h>
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#include <exc.h>
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volatile irq_offload_routine_t offload_routine;
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static const void *offload_param;
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@ -14,9 +14,9 @@
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#include <kernel_arch_interface.h>
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#include <kernel_internal.h>
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#include <logging/log.h>
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#include <arch/arm/aarch64/cpu.h>
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#include <arch/arm/aarch64/lib_helpers.h>
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#include <arch/arm/aarch64/arm_mmu.h>
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#include <arch/arm64/cpu.h>
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#include <arch/arm64/lib_helpers.h>
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#include <arch/arm64/arm_mmu.h>
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#include <linker/linker-defs.h>
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#include <spinlock.h>
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#include <sys/util.h>
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@ -25,6 +25,7 @@
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#ifndef _ARM_OFFSETS_INC_
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#define _ARM_OFFSETS_INC_
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#include <gen_offset.h>
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#include <kernel.h>
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#include <kernel_arch_data.h>
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#include <kernel_offsets.h>
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@ -61,7 +62,7 @@ GEN_ABSOLUTE_SYM(___esf_t_SIZEOF, sizeof(_esf_t));
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#ifdef CONFIG_HAS_ARM_SMCCC
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#include <arch/arm/arm-smccc.h>
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#include <arch/arm64/arm-smccc.h>
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GEN_NAMED_OFFSET_SYM(arm_smccc_res_t, a0, a0_a1);
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GEN_NAMED_OFFSET_SYM(arm_smccc_res_t, a2, a2_a3);
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#endif /* CONFIG_HAS_ARM_SMCCC */
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GEN_ABS_SYM_END
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#endif /* _ARM_OFFSETS_INC_ */
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@ -17,7 +17,7 @@
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#include <ksched.h>
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#include <soc.h>
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#include <init.h>
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#include <arch/arm/aarch64/arm_mmu.h>
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#include <arch/arm64/arm_mmu.h>
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#include <arch/cpu.h>
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#include <drivers/interrupt_controller/gic.h>
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#include <drivers/pm_cpu_ops.h>
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43
arch/arm64/core/tls.c
Normal file
43
arch/arm64/core/tls.c
Normal file
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/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <kernel_structs.h>
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#include <kernel_internal.h>
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#include <kernel_tls.h>
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#include <app_memory/app_memdomain.h>
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#include <sys/util.h>
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size_t arch_tls_stack_setup(struct k_thread *new_thread, char *stack_ptr)
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{
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/*
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* TLS area for ARM has some data fields following by
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* thread data and bss. These fields are supposed to be
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* used by toolchain and OS TLS code to aid in locating
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* the TLS data/bss. Zephyr currently has no use for
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* this so we can simply skip these. However, since GCC
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* is generating code assuming these fields are there,
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* we simply skip them when setting the TLS pointer.
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*/
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/*
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* Since we are populating things backwards,
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* setup the TLS data/bss area first.
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*/
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stack_ptr -= z_tls_data_size();
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z_tls_copy(stack_ptr);
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/* Skip two pointers due to toolchain */
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stack_ptr -= sizeof(uintptr_t) * 2;
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/*
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* Set thread TLS pointer which is used in
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* context switch to point to TLS area.
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*/
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new_thread->tls = POINTER_TO_UINT(stack_ptr);
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return (z_tls_data_size() + (sizeof(uintptr_t) * 2));
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}
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48
arch/arm64/include/kernel_arch_data.h
Normal file
48
arch/arm64/include/kernel_arch_data.h
Normal file
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@ -0,0 +1,48 @@
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/*
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* Copyright (c) 2013-2016 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Private kernel definitions (ARM)
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*
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* This file contains private kernel structures definitions and various
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* other definitions for the ARM Cortex-A/R/M processor architecture family.
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*
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* This file is also included by assembly language files which must #define
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* _ASMLANGUAGE before including this header file. Note that kernel
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* assembly source files obtains structure offset values via "absolute symbols"
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* in the offsets.o module.
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*/
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#ifndef ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_DATA_H_
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#define ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_DATA_H_
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <arch/cpu.h>
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#include <exc.h>
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#ifndef _ASMLANGUAGE
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#include <kernel.h>
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#include <zephyr/types.h>
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#include <sys/dlist.h>
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#include <sys/atomic.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct __esf _esf_t;
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typedef struct __basic_sf _basic_sf_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_DATA_H_ */
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@ -35,7 +35,7 @@ zephyr_linker_sources_ifdef(CONFIG_NOCACHE_MEMORY
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)
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# Only ARM, X86 and OPENISA_RV32M1_RISCV32 use ROM_START_OFFSET.
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if (DEFINED CONFIG_ARM OR DEFINED CONFIG_X86
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if (DEFINED CONFIG_ARM OR DEFINED CONFIG_X86 OR DEFINED CONFIG_ARM64
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OR DEFINED CONFIG_SOC_OPENISA_RV32M1_RISCV32)
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zephyr_linker_sources(ROM_START SORT_KEY 0x0 rom_start_offset.ld)
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endif()
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@ -1,7 +1,7 @@
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identifier: bcm958402m2_a72
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name: Broadcom BCM958402M2_A72
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type: mcu
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arch: arm
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arch: arm64
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toolchain:
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- zephyr
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- cross-compile
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Before Width: | Height: | Size: 4.8 KiB After Width: | Height: | Size: 4.8 KiB |
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@ -6,7 +6,7 @@
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*/
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/dts-v1/;
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#include <arm/qemu-virt/qemu-virt-a53.dtsi>
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#include <arm64/qemu-virt/qemu-virt-a53.dtsi>
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/ {
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model = "QEMU Cortex-A53";
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@ -2,7 +2,7 @@ identifier: qemu_cortex_a53
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name: QEMU Emulation for Cortex-A53
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type: qemu
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simulation: qemu
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arch: arm
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arch: arm64
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toolchain:
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- zephyr
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- cross-compile
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@ -2,7 +2,7 @@ identifier: qemu_cortex_a53_smp
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name: QEMU Emulation for Cortex-A53 SMP
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type: qemu
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simulation: qemu
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arch: arm
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arch: arm64
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toolchain:
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- zephyr
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- cross-compile
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@ -6,7 +6,7 @@
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*/
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/dts-v1/;
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#include <arm/qemu-virt/qemu-virt-a53.dtsi>
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#include <arm64/qemu-virt/qemu-virt-a53.dtsi>
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/ {
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model = "QEMU Cortex-A53";
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@ -2,7 +2,7 @@ identifier: qemu_cortex_a53_xip
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name: QEMU Emulation for Cortex-A53 (XIP)
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type: qemu
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simulation: qemu
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arch: arm
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arch: arm64
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toolchain:
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- zephyr
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- cross-compile
|
Before Width: | Height: | Size: 66 KiB After Width: | Height: | Size: 66 KiB |
|
@ -14,7 +14,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <mem.h>
|
||||
#include <arm/armv8-a.dtsi>
|
||||
#include <arm64/armv8-a.dtsi>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
|
@ -47,6 +47,8 @@ include(${ZEPHYR_BASE}/cmake/gcc-m-cpu.cmake)
|
|||
|
||||
if("${ARCH}" STREQUAL "arm")
|
||||
include(${ZEPHYR_BASE}/cmake/compiler/gcc/target_arm.cmake)
|
||||
elseif("${ARCH}" STREQUAL "arm64")
|
||||
include(${ZEPHYR_BASE}/cmake/compiler/gcc/target_arm64.cmake)
|
||||
elseif("${ARCH}" STREQUAL "arc")
|
||||
list(APPEND TOOLCHAIN_C_FLAGS
|
||||
-mcpu=${GCC_M_CPU}
|
||||
|
|
|
@ -1,43 +1,35 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
if(CONFIG_ARM64)
|
||||
list(APPEND TOOLCHAIN_C_FLAGS -mcpu=${GCC_M_CPU})
|
||||
list(APPEND TOOLCHAIN_LD_FLAGS -mcpu=${GCC_M_CPU})
|
||||
list(APPEND TOOLCHAIN_C_FLAGS -mcpu=${GCC_M_CPU})
|
||||
list(APPEND TOOLCHAIN_LD_FLAGS -mcpu=${GCC_M_CPU})
|
||||
|
||||
list(APPEND TOOLCHAIN_C_FLAGS -mabi=lp64)
|
||||
list(APPEND TOOLCHAIN_LD_FLAGS -mabi=lp64)
|
||||
if(CONFIG_COMPILER_ISA_THUMB2)
|
||||
list(APPEND TOOLCHAIN_C_FLAGS -mthumb)
|
||||
list(APPEND TOOLCHAIN_LD_FLAGS -mthumb)
|
||||
endif()
|
||||
|
||||
list(APPEND TOOLCHAIN_C_FLAGS -mabi=aapcs)
|
||||
list(APPEND TOOLCHAIN_LD_FLAGS -mabi=aapcs)
|
||||
|
||||
# Defines a mapping from GCC_M_CPU to FPU
|
||||
|
||||
if(CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION)
|
||||
set(PRECISION_TOKEN)
|
||||
else()
|
||||
list(APPEND TOOLCHAIN_C_FLAGS -mcpu=${GCC_M_CPU})
|
||||
list(APPEND TOOLCHAIN_LD_FLAGS -mcpu=${GCC_M_CPU})
|
||||
set(PRECISION_TOKEN sp-)
|
||||
endif()
|
||||
|
||||
if(CONFIG_COMPILER_ISA_THUMB2)
|
||||
list(APPEND TOOLCHAIN_C_FLAGS -mthumb)
|
||||
list(APPEND TOOLCHAIN_LD_FLAGS -mthumb)
|
||||
endif()
|
||||
set(FPU_FOR_cortex-m4 fpv4-${PRECISION_TOKEN}d16)
|
||||
set(FPU_FOR_cortex-m7 fpv5-${PRECISION_TOKEN}d16)
|
||||
set(FPU_FOR_cortex-m33 fpv5-${PRECISION_TOKEN}d16)
|
||||
|
||||
list(APPEND TOOLCHAIN_C_FLAGS -mabi=aapcs)
|
||||
list(APPEND TOOLCHAIN_LD_FLAGS -mabi=aapcs)
|
||||
|
||||
# Defines a mapping from GCC_M_CPU to FPU
|
||||
|
||||
if(CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION)
|
||||
set(PRECISION_TOKEN)
|
||||
else()
|
||||
set(PRECISION_TOKEN sp-)
|
||||
endif()
|
||||
|
||||
set(FPU_FOR_cortex-m4 fpv4-${PRECISION_TOKEN}d16)
|
||||
set(FPU_FOR_cortex-m7 fpv5-${PRECISION_TOKEN}d16)
|
||||
set(FPU_FOR_cortex-m33 fpv5-${PRECISION_TOKEN}d16)
|
||||
|
||||
if(CONFIG_FPU)
|
||||
list(APPEND TOOLCHAIN_C_FLAGS -mfpu=${FPU_FOR_${GCC_M_CPU}})
|
||||
list(APPEND TOOLCHAIN_LD_FLAGS -mfpu=${FPU_FOR_${GCC_M_CPU}})
|
||||
if (CONFIG_FP_SOFTABI)
|
||||
list(APPEND TOOLCHAIN_C_FLAGS -mfloat-abi=softfp)
|
||||
list(APPEND TOOLCHAIN_LD_FLAGS -mfloat-abi=softfp)
|
||||
elseif(CONFIG_FP_HARDABI)
|
||||
list(APPEND TOOLCHAIN_C_FLAGS -mfloat-abi=hard)
|
||||
list(APPEND TOOLCHAIN_LD_FLAGS -mfloat-abi=hard)
|
||||
endif()
|
||||
if(CONFIG_FPU)
|
||||
list(APPEND TOOLCHAIN_C_FLAGS -mfpu=${FPU_FOR_${GCC_M_CPU}})
|
||||
list(APPEND TOOLCHAIN_LD_FLAGS -mfpu=${FPU_FOR_${GCC_M_CPU}})
|
||||
if (CONFIG_FP_SOFTABI)
|
||||
list(APPEND TOOLCHAIN_C_FLAGS -mfloat-abi=softfp)
|
||||
list(APPEND TOOLCHAIN_LD_FLAGS -mfloat-abi=softfp)
|
||||
elseif(CONFIG_FP_HARDABI)
|
||||
list(APPEND TOOLCHAIN_C_FLAGS -mfloat-abi=hard)
|
||||
list(APPEND TOOLCHAIN_LD_FLAGS -mfloat-abi=hard)
|
||||
endif()
|
||||
endif()
|
||||
|
|
6
cmake/compiler/gcc/target_arm64.cmake
Normal file
6
cmake/compiler/gcc/target_arm64.cmake
Normal file
|
@ -0,0 +1,6 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
list(APPEND TOOLCHAIN_C_FLAGS -mcpu=${GCC_M_CPU})
|
||||
list(APPEND TOOLCHAIN_LD_FLAGS -mcpu=${GCC_M_CPU})
|
||||
|
||||
list(APPEND TOOLCHAIN_C_FLAGS -mabi=lp64)
|
||||
list(APPEND TOOLCHAIN_LD_FLAGS -mabi=lp64)
|
|
@ -36,12 +36,14 @@ if("${ARCH}" STREQUAL "arm")
|
|||
set(GCC_M_CPU cortex-r5)
|
||||
elseif(CONFIG_CPU_CORTEX_R7)
|
||||
set(GCC_M_CPU cortex-r7)
|
||||
elseif(CONFIG_CPU_CORTEX_A53)
|
||||
else()
|
||||
message(FATAL_ERROR "Expected CONFIG_CPU_CORTEX_x to be defined")
|
||||
endif()
|
||||
elseif("${ARCH}" STREQUAL "arm64")
|
||||
if(CONFIG_CPU_CORTEX_A53)
|
||||
set(GCC_M_CPU cortex-a53)
|
||||
elseif(CONFIG_CPU_CORTEX_A72)
|
||||
set(GCC_M_CPU cortex-a72)
|
||||
else()
|
||||
message(FATAL_ERROR "Expected CONFIG_CPU_CORTEX_x to be defined")
|
||||
endif()
|
||||
elseif("${ARCH}" STREQUAL "arc")
|
||||
if(CONFIG_CPU_EM4_FPUS)
|
||||
|
|
|
@ -1,10 +1,7 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if(CONFIG_ARM64)
|
||||
set(CROSS_COMPILE_TARGET_arm aarch64-zephyr-elf)
|
||||
else()
|
||||
set(CROSS_COMPILE_TARGET_arm arm-zephyr-eabi)
|
||||
endif()
|
||||
set(CROSS_COMPILE_TARGET_arm arm-zephyr-eabi)
|
||||
set(CROSS_COMPILE_TARGET_arm64 aarch64-zephyr-elf)
|
||||
set(CROSS_COMPILE_TARGET_nios2 nios2-zephyr-elf)
|
||||
set(CROSS_COMPILE_TARGET_riscv riscv64-zephyr-elf)
|
||||
set(CROSS_COMPILE_TARGET_mips mipsel-zephyr-elf)
|
||||
|
|
|
@ -1,10 +1,7 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if(CONFIG_ARM64)
|
||||
set(CROSS_COMPILE_TARGET_arm aarch64-zephyr-elf)
|
||||
else()
|
||||
set(CROSS_COMPILE_TARGET_arm arm-zephyr-eabi)
|
||||
endif()
|
||||
set(CROSS_COMPILE_TARGET_arm64 arm-zephyr-eabi)
|
||||
set(CROSS_COMPILE_TARGET_arm aarch64-zephyr-elf)
|
||||
set(CROSS_COMPILE_TARGET_nios2 nios2-zephyr-elf)
|
||||
set(CROSS_COMPILE_TARGET_riscv riscv64-zephyr-elf)
|
||||
set(CROSS_COMPILE_TARGET_mips mipsel-zephyr-elf)
|
||||
|
|
67
dts/arm64/broadcom/viper-a72.dtsi
Normal file
67
dts/arm64/broadcom/viper-a72.dtsi
Normal file
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* Copyright 2020 Broadcom
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm64/armv8-a.dtsi>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "viper-common.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
|
||||
IRQ_DEFAULT_PRIORITY>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL
|
||||
IRQ_DEFAULT_PRIORITY>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL
|
||||
IRQ_DEFAULT_PRIORITY>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL
|
||||
IRQ_DEFAULT_PRIORITY>;
|
||||
label = "arch_timer";
|
||||
};
|
||||
|
||||
soc {
|
||||
gic: interrupt-controller@42700000 {
|
||||
compatible = "arm,gic";
|
||||
reg = <0x42700000 0x010000>,
|
||||
<0x42780000 0x600000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <4>;
|
||||
label = "GIC";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL
|
||||
IRQ_DEFAULT_PRIORITY>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL
|
||||
IRQ_DEFAULT_PRIORITY>;
|
||||
};
|
||||
|
||||
&paxdma {
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL
|
||||
IRQ_DEFAULT_PRIORITY>;
|
||||
};
|
75
dts/arm64/broadcom/viper-common.dtsi
Normal file
75
dts/arm64/broadcom/viper-common.dtsi
Normal file
|
@ -0,0 +1,75 @@
|
|||
/*
|
||||
* Copyright 2020 Broadcom
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/ {
|
||||
soc {
|
||||
sram0: memory@400000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00400000 0x80000>;
|
||||
};
|
||||
|
||||
uart0: uart@40020000 {
|
||||
compatible = "ns16550";
|
||||
reg = <0x40020000 0x400>;
|
||||
clock-frequency = <25000000>;
|
||||
label = "CRMU_UART";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: uart@48100000 {
|
||||
compatible = "ns16550";
|
||||
reg = <0x48100000 0x400>;
|
||||
clock-frequency = <100000000>;
|
||||
label = "CCG_UART0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pl330: pl330@48300000 {
|
||||
compatible = "arm,dma-pl330";
|
||||
reg = <0x48300000 0x2000>,
|
||||
<0x482f005c 0x20>;
|
||||
reg-names = "pl330_regs",
|
||||
"control_regs";
|
||||
microcode = <0x63b00000 0x1000>;
|
||||
dma-channels = <8>;
|
||||
#dma-cells = <1>;
|
||||
label = "DMA_0";
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie0_ep: pcie@4e100000 {
|
||||
compatible = "brcm,iproc-pcie-ep";
|
||||
reg = <0x0 0x4e100000 0x0 0x2100>,
|
||||
<0x0 0x50000000 0x0 0x8000000>,
|
||||
<0x4 0x0 0x0 0x8000000>;
|
||||
reg-names = "iproc_pcie_regs", "map_lowmem",
|
||||
"map_highmem";
|
||||
label = "PCIE_0";
|
||||
dmas = <&pl330 0>, <&pl330 1>;
|
||||
dma-names = "txdma", "rxdma";
|
||||
};
|
||||
|
||||
paxdma: paxdma@4e100800 {
|
||||
compatible = "brcm,iproc-pax-dma-v2";
|
||||
label = "DMA_1";
|
||||
reg = <0x0 0x4e100800 0x0 0x2100>,
|
||||
<0x0 0x4f000000 0x0 0x200000>,
|
||||
<0x0 0x4f200000 0x0 0x10000>;
|
||||
reg-names = "dme_regs", "rm_ring_regs",
|
||||
"rm_comm_regs";
|
||||
dma-channels = <4>;
|
||||
#dma-cells = <1>;
|
||||
bd-memory = <0x63b00000 0x100000>;
|
||||
scr-addr-loc = <0x200061f0>;
|
||||
scr-size-loc = <0x200061f8>;
|
||||
pcie-ep = <&pcie0_ep>;
|
||||
};
|
||||
};
|
||||
};
|
|
@ -14,7 +14,7 @@
|
|||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <arm/armv8-a.dtsi>
|
||||
#include <arm64/armv8-a.dtsi>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
|
@ -77,7 +77,7 @@ struct z_app_region {
|
|||
* specific: "aw" indicates section is allocatable and writable,
|
||||
* and "@progbits" indicates the section has data.
|
||||
*/
|
||||
#ifdef CONFIG_ARM
|
||||
#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
|
||||
/* ARM has a quirk in that '@' denotes a comment, so we have to send
|
||||
* %progbits to the assembler instead.
|
||||
*/
|
||||
|
|
|
@ -15,7 +15,7 @@
|
|||
#if defined(CONFIG_X86) || defined(CONFIG_X86_64)
|
||||
#include <arch/x86/arch_inlines.h>
|
||||
#elif defined(CONFIG_ARM64)
|
||||
#include <arch/arm/aarch64/arch_inlines.h>
|
||||
#include <arch/arm64/arch_inlines.h>
|
||||
#elif defined(CONFIG_ARC)
|
||||
#include <arch/arc/arch_inlines.h>
|
||||
#elif defined(CONFIG_XTENSA)
|
||||
|
|
|
@ -19,18 +19,18 @@
|
|||
/* Add include for DTS generated information */
|
||||
#include <devicetree.h>
|
||||
|
||||
#include <arch/arm/aarch64/thread.h>
|
||||
#include <arch/arm/aarch64/exc.h>
|
||||
#include <arch/arm/aarch64/irq.h>
|
||||
#include <arch/arm/aarch64/misc.h>
|
||||
#include <arch/arm/aarch64/asm_inline.h>
|
||||
#include <arch/arm/aarch64/cpu.h>
|
||||
#include <arch/arm/aarch64/macro.inc>
|
||||
#include <arch/arm/aarch64/sys_io.h>
|
||||
#include <arch/arm/aarch64/timer.h>
|
||||
#include <arch/arm/aarch64/error.h>
|
||||
#include <arch/arm/aarch64/arm_mmu.h>
|
||||
#include <arch/arm/aarch64/thread_stack.h>
|
||||
#include <arch/arm64/thread.h>
|
||||
#include <arch/arm64/exc.h>
|
||||
#include <arch/arm64/irq.h>
|
||||
#include <arch/arm64/misc.h>
|
||||
#include <arch/arm64/asm_inline.h>
|
||||
#include <arch/arm64/cpu.h>
|
||||
#include <arch/arm64/macro.inc>
|
||||
#include <arch/arm64/sys_io.h>
|
||||
#include <arch/arm64/timer.h>
|
||||
#include <arch/arm64/error.h>
|
||||
#include <arch/arm64/arm_mmu.h>
|
||||
#include <arch/arm64/thread_stack.h>
|
||||
#include <arch/common/addr_types.h>
|
||||
#include <arch/common/sys_bitops.h>
|
||||
#include <arch/common/ffs.h>
|
|
@ -11,7 +11,7 @@
|
|||
|
||||
#include <kernel_structs.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <arch/arm/aarch64/lib_helpers.h>
|
||||
#include <arch/arm64/lib_helpers.h>
|
||||
|
||||
static ALWAYS_INLINE _cpu_t *arch_curr_cpu(void)
|
||||
{
|
|
@ -13,7 +13,7 @@
|
|||
*/
|
||||
|
||||
#if defined(__GNUC__)
|
||||
#include <arch/arm/aarch64/asm_inline_gcc.h>
|
||||
#include <arch/arm64/asm_inline_gcc.h>
|
||||
#else
|
||||
#include <arch/arm/asm_inline_other.h>
|
||||
#endif
|
|
@ -16,7 +16,7 @@
|
|||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include <arch/arm/aarch64/lib_helpers.h>
|
||||
#include <arch/arm64/lib_helpers.h>
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#ifdef __cplusplus
|
|
@ -14,8 +14,8 @@
|
|||
#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_ERROR_H_
|
||||
#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_ERROR_H_
|
||||
|
||||
#include <arch/arm/aarch64/syscall.h>
|
||||
#include <arch/arm/aarch64/exc.h>
|
||||
#include <arch/arm64/syscall.h>
|
||||
#include <arch/arm64/exc.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef __cplusplus
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include <arch/arm/aarch64/cpu.h>
|
||||
#include <arch/arm64/cpu.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/* All the macros need a memory clobber */
|
|
@ -26,7 +26,7 @@
|
|||
|
||||
#include <zephyr/types.h>
|
||||
#include <stdbool.h>
|
||||
#include <arch/arm/aarch64/cpu.h>
|
||||
#include <arch/arm64/cpu.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Add a link
Reference in a new issue