dts: arm: remove DT_NUM_IRQ_PRIO_BITS and DT_NUM_MPU_REGIONS
We don't need to define DT_NUM_IRQ_PRIO_BITS or DT_NUM_MPU_REGIONS in dts_fixup.h files anymore, so we can remove them. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
parent
5648df39ac
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fbdeda9df2
63 changed files with 0 additions and 209 deletions
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@ -2,8 +2,6 @@
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_FPGAIO_LED0_GPIO_NAME DT_ARM_MPS2_FPGAIO_GPIO_40028000_LABEL
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#define DT_FPGAIO_LED0_NUM DT_ARM_MPS2_FPGAIO_GPIO_40028000_NGPIOS
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#define DT_FPGAIO_LED0 DT_ARM_MPS2_FPGAIO_GPIO_40028000_BASE_ADDRESS
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@ -1,7 +0,0 @@
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/* SPDX-License-Identifier: Apache-2.0 */
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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/* End of SoC Level DTS fixup file */
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@ -7,9 +7,6 @@
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#if defined(CONFIG_SOC_MPS2_AN521)
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V8M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_NUM_MPU_REGIONS DT_ARM_ARMV8M_MPU_E000ED90_ARM_NUM_MPU_REGIONS
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#if defined (CONFIG_ARM_NONSECURE_FIRMWARE)
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/* CMSDK APB Timers */
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@ -6,10 +6,6 @@
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V8M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_NUM_MPU_REGIONS DT_ARM_ARMV8M_MPU_E000ED90_ARM_NUM_MPU_REGIONS
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#if defined (CONFIG_ARM_NONSECURE_FIRMWARE)
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/* SCC */
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@ -6,10 +6,6 @@
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V8M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_NUM_MPU_REGIONS DT_ARM_ARMV8M_MPU_E000ED90_ARM_NUM_MPU_REGIONS
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#if defined (CONFIG_ARM_NONSECURE_FIRMWARE)
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/* SCC */
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@ -8,8 +8,6 @@
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_GPIO_SAM_PORTA_LABEL DT_ATMEL_SAM_GPIO_400E0E00_LABEL
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#define DT_GPIO_SAM_PORTA_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E0E00_BASE_ADDRESS
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#define DT_GPIO_SAM_PORTA_IRQ DT_ATMEL_SAM_GPIO_400E0E00_IRQ_0
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@ -11,8 +11,6 @@
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_GPIO_SAM_PORTA_LABEL DT_ATMEL_SAM_GPIO_400E0E00_LABEL
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#define DT_GPIO_SAM_PORTA_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E0E00_BASE_ADDRESS
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#define DT_GPIO_SAM_PORTA_IRQ DT_ATMEL_SAM_GPIO_400E0E00_IRQ_0
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@ -12,8 +12,6 @@
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_GPIO_SAM_PORTA_LABEL DT_ATMEL_SAM_GPIO_400E0E00_LABEL
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#define DT_GPIO_SAM_PORTA_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E0E00_BASE_ADDRESS
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#define DT_GPIO_SAM_PORTA_IRQ DT_ATMEL_SAM_GPIO_400E0E00_IRQ_0
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@ -8,11 +8,8 @@
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M7_0_CLOCK_FREQUENCY
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#define DT_NUM_MPU_REGIONS DT_ARM_ARMV7M_MPU_E000ED90_ARM_NUM_MPU_REGIONS
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#define DT_GPIO_SAM_PORTA_LABEL DT_ATMEL_SAM_GPIO_400E0E00_LABEL
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#define DT_GPIO_SAM_PORTA_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E0E00_BASE_ADDRESS
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#define DT_GPIO_SAM_PORTA_IRQ DT_ATMEL_SAM_GPIO_400E0E00_IRQ_0
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M7_0_CLOCK_FREQUENCY
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#define DT_NUM_MPU_REGIONS DT_ARM_ARMV7M_MPU_E000ED90_ARM_NUM_MPU_REGIONS
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#define DT_GPIO_SAM_PORTA_LABEL DT_ATMEL_SAM_GPIO_400E0E00_LABEL
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#define DT_GPIO_SAM_PORTA_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E0E00_BASE_ADDRESS
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#define DT_GPIO_SAM_PORTA_IRQ DT_ATMEL_SAM_GPIO_400E0E00_IRQ_0
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@ -4,6 +4,4 @@
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#define DT_FLASH_DEV_NAME DT_ATMEL_SAM0_NVMCTRL_41004000_LABEL
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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/* End of SoC Level DTS fixup file */
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@ -4,6 +4,4 @@
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#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, atmel_sam0_nvmctrl))
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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/* End of SoC Level DTS fixup file */
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#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, atmel_sam0_nvmctrl))
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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/* End of SoC Level DTS fixup file */
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#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, atmel_sam0_nvmctrl))
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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/* End of SoC Level DTS fixup file */
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#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, atmel_sam0_nvmctrl))
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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/* End of SoC Level DTS fixup file */
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#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, atmel_sam0_nvmctrl))
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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/* End of SoC Level DTS fixup file */
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#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, atmel_sam0_nvmctrl))
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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/* End of SoC Level DTS fixup file */
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/* SPDX-License-Identifier: Apache-2.0 */
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/*
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* Copyright 2018 Broadcom.
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*/
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_NUM_MPU_REGIONS DT_ARM_ARMV7M_MPU_E000ED90_ARM_NUM_MPU_REGIONS
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/* End of SoC Level DTS fixup file */
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@ -6,12 +6,6 @@
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/* SoC level DTS fixup file */
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#if defined(CONFIG_SOC_PSOC6_M0)
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#else
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#endif
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#define DT_UART_PSOC6_UART_5_NAME "uart_5"
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#define DT_UART_PSOC6_UART_5_BASE_ADDRESS SCB5
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#define DT_UART_PSOC6_UART_5_PORT P5_0_PORT
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* generated data matches the driver definitions.
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*/
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#define DT_NUM_IRQ_PRIO_BITS \
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DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#if defined(DT_NS16550_400F2400_REG_SHIFT)
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#define DT_NS16550_REG_SHIFT DT_NS16550_400F2400_REG_SHIFT
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#elif defined(DT_NS16550_400F2800_REG_SHIFT)
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/* SPDX-License-Identifier: Apache-2.0 */
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/* This file is a temporary workaround for mapping of the generated information
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* to the current driver definitions. This will be removed when the drivers
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* are modified to handle the generated information, or the mapping of
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* generated data matches the driver definitions.
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*/
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_ADC_0_NAME DT_NORDIC_NRF_ADC_ADC_0_LABEL
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#define DT_UART_0_NAME DT_NORDIC_NRF_UART_UART_0_LABEL
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_ADC_0_NAME DT_NORDIC_NRF_SAADC_ADC_0_LABEL
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#ifdef DT_NORDIC_NRF_UART_UART_0_LABEL
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS \
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DT_ARM_V8M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_NUM_MPU_REGIONS \
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DT_ARM_ARMV8M_MPU_E000ED90_ARM_NUM_MPU_REGIONS
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#define DT_ADC_0_NAME DT_NORDIC_NRF_SAADC_ADC_0_LABEL
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#define DT_UART_0_NAME DT_NORDIC_NRF_UARTE_UART_0_LABEL
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V8M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_NUM_MPU_REGIONS DT_ARM_ARMV8M_MPU_E000ED90_ARM_NUM_MPU_REGIONS
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#define DT_ADC_0_NAME DT_NORDIC_NRF_SAADC_ADC_0_LABEL
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#define DT_UART_0_NAME DT_NORDIC_NRF_UARTE_UART_0_LABEL
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/*
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* Copyright (c) 2018, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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/*
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* Copyright (c) 2018, Diego Sueiro <diego.sueiro@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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/* End of SoC Level DTS fixup file */
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_NUM_MPU_REGIONS DT_ARM_ARMV7M_MPU_E000ED90_ARM_NUM_MPU_REGIONS
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#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, nxp_imx_gpt))
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#define DT_RTC_1_NAME DT_LABEL(DT_INST(1, nxp_imx_gpt))
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*/
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_ADC_0_BASE_ADDRESS DT_NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS
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#define DT_ADC_0_IRQ DT_NXP_KINETIS_ADC16_4003B000_IRQ_0
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#define DT_ADC_0_IRQ_PRI DT_NXP_KINETIS_ADC16_4003B000_IRQ_0_PRIORITY
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/* SPDX-License-Identifier: Apache-2.0 */
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_ADC_0_BASE_ADDRESS DT_NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS
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#define DT_ADC_0_IRQ DT_NXP_KINETIS_ADC16_4003B000_IRQ_0
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#define DT_ADC_0_IRQ_PRI DT_NXP_KINETIS_ADC16_4003B000_IRQ_0_PRIORITY
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*/
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_FLASH_DEV_BASE_ADDRESS DT_NXP_KINETIS_FTFA_40020000_BASE_ADDRESS
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#define DT_FLASH_DEV_NAME DT_NXP_KINETIS_FTFA_40020000_LABEL
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*/
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, nxp_kinetis_rtc))
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#define DT_FLASH_DEV_BASE_ADDRESS DT_NXP_KINETIS_FTFE_40020000_BASE_ADDRESS
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/* SPDX-License-Identifier: Apache-2.0 */
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_ADC_0_BASE_ADDRESS DT_NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS
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#define DT_ADC_0_IRQ DT_NXP_KINETIS_ADC16_4003B000_IRQ_0
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#define DT_ADC_0_IRQ_PRI DT_NXP_KINETIS_ADC16_4003B000_IRQ_0_PRIORITY
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*/
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_FLASH_DEV_BASE_ADDRESS DT_NXP_KINETIS_FTFE_40020000_BASE_ADDRESS
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#define DT_FLASH_DEV_NAME DT_NXP_KINETIS_FTFE_40020000_LABEL
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#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, nxp_kinetis_rtc))
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#if defined(CONFIG_SOC_MKW22D5) || defined(CONFIG_SOC_MKW24D5)
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_FLASH_DEV_BASE_ADDRESS DT_NXP_KINETIS_FTFL_40020000_BASE_ADDRESS
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#define DT_FLASH_DEV_NAME DT_NXP_KINETIS_FTFL_40020000_LABEL
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#endif /* CONFIG_SOC_MKW22D5 || CONFIG_SOC_MKW24D5 */
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#if defined(CONFIG_SOC_MKW40Z4) || defined(CONFIG_SOC_MKW41Z4)
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_FLASH_DEV_BASE_ADDRESS DT_NXP_KINETIS_FTFA_40020000_BASE_ADDRESS
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#define DT_FLASH_DEV_NAME DT_NXP_KINETIS_FTFA_40020000_LABEL
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/* SoC level DTS fixup file */
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#if defined(CONFIG_SOC_LPC54114_M0)
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#else
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#endif
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|
||||
#define DT_MAILBOX_MCUX_MAILBOX_0_IRQ DT_NXP_LPC_MAILBOX_4008B000_IRQ_0
|
||||
#define DT_MAILBOX_MCUX_MAILBOX_0_IRQ_PRI DT_NXP_LPC_MAILBOX_4008B000_IRQ_0_PRIORITY
|
||||
#define DT_MAILBOX_MCUX_MAILBOX_0_NAME DT_NXP_LPC_MAILBOX_4008B000_LABEL
|
||||
|
|
|
@ -6,9 +6,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V8M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
#define DT_NUM_MPU_REGIONS DT_PROP(DT_INST(0, arm_armv8m_mpu), arm_num_mpu_regions)
|
||||
|
||||
#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, nxp_lpc_iap))
|
||||
|
||||
/* End of SoC Level DTS fixup file */
|
||||
|
|
|
@ -7,8 +7,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_40000000_BASE_ADDRESS
|
||||
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_40000000_LABEL
|
||||
|
||||
|
|
|
@ -8,7 +8,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M0PLUS_0_CLOCK_FREQUENCY
|
||||
|
||||
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS
|
||||
|
|
|
@ -6,7 +6,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY
|
||||
|
||||
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
|
||||
|
|
|
@ -6,7 +6,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY
|
||||
|
||||
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
|
||||
|
|
|
@ -8,7 +8,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY
|
||||
|
||||
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS
|
||||
|
|
|
@ -12,7 +12,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY
|
||||
|
||||
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
|
||||
|
|
|
@ -8,7 +8,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY
|
||||
|
||||
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
|
||||
|
|
|
@ -8,7 +8,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY
|
||||
|
||||
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
|
||||
|
|
|
@ -2,8 +2,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_CAN_1_BASE_ADDRESS DT_ST_STM32_CAN_40006400_BASE_ADDRESS
|
||||
#define DT_CAN_1_BUS_SPEED DT_ST_STM32_CAN_40006400_BUS_SPEED
|
||||
#define DT_CAN_1_NAME DT_ST_STM32_CAN_40006400_LABEL
|
||||
|
|
|
@ -2,8 +2,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
|
||||
|
||||
#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012400_LABEL
|
||||
|
|
|
@ -2,8 +2,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
|
||||
|
||||
#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012000_LABEL
|
||||
|
|
|
@ -2,8 +2,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, st_stm32f3_flash_controller))
|
||||
|
||||
#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))
|
||||
|
|
|
@ -2,8 +2,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_I2S_1_BASE_ADDRESS DT_ST_STM32_I2S_40013000_BASE_ADDRESS
|
||||
#define DT_I2S_1_IRQ_PRI DT_ST_STM32_I2S_40013000_IRQ_0_PRIORITY
|
||||
#define DT_I2S_1_NAME DT_ST_STM32_I2S_40013000_LABEL
|
||||
|
|
|
@ -2,10 +2,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_NUM_MPU_REGIONS DT_ARM_ARMV7M_MPU_E000ED90_ARM_NUM_MPU_REGIONS
|
||||
|
||||
#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))
|
||||
|
||||
#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, st_stm32f7_flash_controller))
|
||||
|
|
|
@ -6,8 +6,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, st_stm32g0_flash_controller))
|
||||
|
||||
#define DT_PWM_STM32_3_DEV_NAME DT_ST_STM32_PWM_40000400_PWM_LABEL
|
||||
|
|
|
@ -6,8 +6,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_ADC_0_NAME DT_LABEL(DT_INST(0, st_stm32_adc))
|
||||
#define DT_ADC_1_NAME DT_LABEL(DT_INST(1, st_stm32_adc))
|
||||
|
||||
|
|
|
@ -6,10 +6,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_NUM_MPU_REGIONS DT_ARM_ARMV7M_MPU_E000ED90_ARM_NUM_MPU_REGIONS
|
||||
|
||||
#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))
|
||||
|
||||
/* End of SoC Level DTS fixup file */
|
||||
|
|
|
@ -2,8 +2,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
|
||||
|
||||
#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012400_LABEL
|
||||
|
|
|
@ -6,8 +6,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
|
||||
|
||||
#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012400_LABEL
|
||||
|
|
|
@ -2,8 +2,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))
|
||||
|
||||
#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, st_stm32l4_flash_controller))
|
||||
|
|
|
@ -1,11 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2019 STMicroelectronics
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
/* End of SoC Level DTS fixup file */
|
|
@ -6,8 +6,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))
|
||||
|
||||
#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, st_stm32wb_flash_controller))
|
||||
|
|
|
@ -1,7 +0,0 @@
|
|||
/* SPDX-License-Identifier: Apache-2.0 */
|
||||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
/* End of SoC Level DTS fixup file */
|
|
@ -6,8 +6,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4_0_CLOCK_FREQUENCY
|
||||
|
||||
/* End of SoC Level DTS fixup file */
|
||||
|
|
|
@ -2,7 +2,6 @@
|
|||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
#define DT_UART_CC32XX_NAME DT_TI_CC32XX_UART_4000C000_LABEL
|
||||
|
||||
#define DT_I2C_0_LABEL DT_TI_CC32XX_I2C_40020000_LABEL
|
||||
|
|
|
@ -1,13 +0,0 @@
|
|||
/* SPDX-License-Identifier: Apache-2.0 */
|
||||
|
||||
/* This file is a temporary workaround for mapping of the generated information
|
||||
* to the current driver definitions. This will be removed when the drivers
|
||||
* are modified to handle the generated information, or the mapping of
|
||||
* generated data matches the driver definitions.
|
||||
*/
|
||||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
/* End of SoC Level DTS fixup file */
|
Loading…
Add table
Add a link
Reference in a new issue