config: Rename TEXT_SECTION_OFFSET to ROM_START_OFFSET
The `TEXT_SECTION_OFFSET` symbol is used to specify the offset between the beginning of the ROM area and the address of the first ROM section. This commit renames `TEXT_SECTION_OFFSET` to `ROM_START_OFFSET` because the first ROM section is not always the `.text` section. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit is contained in:
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4e43e00c4c
commit
3322489d22
14 changed files with 19 additions and 19 deletions
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@ -118,15 +118,15 @@ config FLASH_LOAD_SIZE
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endif # HAS_FLASH_LOAD_OFFSET
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config TEXT_SECTION_OFFSET
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config ROM_START_OFFSET
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hex
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prompt "TEXT section offset" if !BOOTLOADER_MCUBOOT
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prompt "ROM start offset" if !BOOTLOADER_MCUBOOT
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default 0x200 if BOOTLOADER_MCUBOOT
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default 0
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help
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If the application is built for chain-loading by a bootloader this
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variable is required to be set to value that leaves sufficient
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space between the beginning of the image and the start of the .text
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space between the beginning of the image and the start of the first
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section to store an image header or any other metadata.
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In the particular case of the MCUboot bootloader this reserves enough
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space to store the image header, which should also meet vector table
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@ -385,7 +385,7 @@ config BOOTLOADER_MCUBOOT
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order for the image generated to be bootable using the MCUboot open
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source bootloader. Currently this includes:
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* Setting TEXT_SECTION_OFFSET to a default value that allows space
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* Setting ROM_START_OFFSET to a default value that allows space
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for the MCUboot image header
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* Activating SW_VECTOR_RELAY_CLIENT on Cortex-M0
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(or Armv8-M baseline) targets with no built-in vector relocation
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@ -34,8 +34,8 @@ zephyr_linker_sources_ifdef(CONFIG_NOCACHE_MEMORY
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nocache.ld
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)
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# Only ARM, X86 and OPENISA_RV32M1_RISCV32 use TEXT_SECTION_OFFSET.
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# Only ARM, X86 and OPENISA_RV32M1_RISCV32 use ROM_START_OFFSET.
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if (DEFINED CONFIG_ARM OR DEFINED CONFIG_X86
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OR DEFINED CONFIG_SOC_OPENISA_RV32M1_RISCV32)
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zephyr_linker_sources(ROM_START SORT_KEY 0x0 text_section_offset.ld)
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zephyr_linker_sources(ROM_START SORT_KEY 0x0 rom_start_offset.ld)
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endif()
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@ -4,5 +4,5 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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. = CONFIG_TEXT_SECTION_OFFSET;
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. = CONFIG_ROM_START_OFFSET;
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. = ALIGN(4);
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@ -49,7 +49,7 @@ config HEAP_MEM_POOL_SIZE
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default 1024
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depends on DMA_DW
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config TEXT_SECTION_OFFSET
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config ROM_START_OFFSET
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default 0x100
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depends on BOOTLOADER_MCUBOOT
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@ -205,7 +205,7 @@ class ImgtoolSigner(Signer):
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tool_path = self.find_imgtool(command, args)
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# The vector table offset is set in Kconfig:
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vtoff = self.get_cfg(command, bcfg, 'CONFIG_TEXT_SECTION_OFFSET')
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vtoff = self.get_cfg(command, bcfg, 'CONFIG_ROM_START_OFFSET')
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# Flash device write alignment and the partition's slot size
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# come from devicetree:
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flash = self.edt_flash_node(b, cache)
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@ -228,7 +228,7 @@ class ImgtoolSigner(Signer):
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log.banner('image configuration:')
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log.inf('partition offset: {0} (0x{0:x})'.format(addr))
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log.inf('partition size: {0} (0x{0:x})'.format(size))
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log.inf('text section offset: {0} (0x{0:x})'.format(vtoff))
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log.inf('rom start offset: {0} (0x{0:x})'.format(vtoff))
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# Base sign command.
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#
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@ -8,7 +8,7 @@ if SOC_SERIES_IMX_RT
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config SOC_SERIES
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default "rt"
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config TEXT_SECTION_OFFSET
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config ROM_START_OFFSET
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default 0x2000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
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config CLOCK_CONTROL_MCUX_CCM
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@ -85,7 +85,7 @@ const __imx_boot_data_section BOOT_DATA_T boot_data = {
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const __imx_boot_ivt_section ivt image_vector_table = {
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.hdr = IVT_HEADER,
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.entry = CONFIG_FLASH_BASE_ADDRESS + CONFIG_TEXT_SECTION_OFFSET,
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.entry = CONFIG_FLASH_BASE_ADDRESS + CONFIG_ROM_START_OFFSET,
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.reserved1 = IVT_RSVD,
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#ifdef CONFIG_DEVICE_CONFIGURATION_DATA
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.dcd = (uint32_t) dcd_data,
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@ -15,7 +15,7 @@ config NUM_IRQS
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 80000000
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config TEXT_SECTION_OFFSET
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config ROM_START_OFFSET
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default 0x800 if XIP
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default 0x0 if !XIP
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@ -16,7 +16,7 @@ config NUM_IRQS
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 80000000
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config TEXT_SECTION_OFFSET
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config ROM_START_OFFSET
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default 0x800 if XIP
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default 0x0 if !XIP
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@ -7,4 +7,4 @@ CC3235 Info taken from:
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Notes for CC32XXSF:
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* Text must start at 0x800 offset in flash. The first 0x800 bytes are
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reserved for the flash header.
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* See CONFIG_TEXT_SECTION_OFFSET.
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* See CONFIG_ROM_START_OFFSET.
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@ -36,7 +36,7 @@
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#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_code_partition)))
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#define ROM_SIZE (DT_REG_SIZE(DT_CHOSEN(zephyr_code_partition)))
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#define VECTOR_BASE (ROM_BASE + CONFIG_TEXT_SECTION_OFFSET)
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#define VECTOR_BASE (ROM_BASE + CONFIG_ROM_START_OFFSET)
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#else
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@ -6,7 +6,7 @@
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*/
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/*
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* Respect for CONFIG_TEXT_SECTION_OFFSET is mandatory
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* Respect for CONFIG_ROM_START_OFFSET is mandatory
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* for MCUboot support, so .reset.* and .exception.*
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* must come after that offset from ROM_BASE.
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*/
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@ -201,7 +201,7 @@ SECTIONS
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.ResetVector.text : ALIGN(4)
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{
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. = CONFIG_TEXT_SECTION_OFFSET;
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. = CONFIG_ROM_START_OFFSET;
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_ResetVector_text_start = ABSOLUTE(.);
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KEEP (*(.ResetVector.text))
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_ResetVector_text_end = ABSOLUTE(.);
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@ -446,7 +446,7 @@ static int boot_read_v1_header(uint8_t area_id,
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*
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* Larger values in header_size than BOOT_HEADER_SIZE_V1 are
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* possible, e.g. if Zephyr was linked with
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* CONFIG_TEXT_SECTION_OFFSET > BOOT_HEADER_SIZE_V1.
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* CONFIG_ROM_START_OFFSET > BOOT_HEADER_SIZE_V1.
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*/
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if ((v1_raw->header_magic != BOOT_HEADER_MAGIC_V1) ||
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(v1_raw->header_size < BOOT_HEADER_SIZE_V1)) {
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