Microchip: MEC172x: eSPI driver
Updates to MEC172x eSPI driver to support ACPI shared memory region and EC Host Command Subsystem through ACPI_EC1 and Embedded Memory Interface (EMI). Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
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9d815e5251
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5 changed files with 204 additions and 2 deletions
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@ -97,6 +97,10 @@
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status = "okay";
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};
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&emi0 {
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status = "okay";
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};
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&p80bd0 {
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status = "okay";
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};
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@ -10,6 +10,22 @@ config ESPI_XEC_V2
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help
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Enable the Microchip XEC ESPI driver for MEC172x series.
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config ESPI_XEC_PERIPHERAL_ACPI_SHD_MEM_SIZE
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int "Host I/O peripheral port size for shared memory in MEC172X series"
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depends on ESPI_XEC_V2 || ESPI_PERIPHERAL_ACPI_SHM_REGION
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default 256
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help
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This is the port size used by the Host and EC to communicate over
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the shared memory region to return the ACPI response data.
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config ESPI_XEC_PERIPHERAL_HOST_CMD_PARAM_SIZE
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int "Host I/O peripheral port size for ec host command in MEC172X series"
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depends on ESPI_XEC_V2 || ESPI_PERIPHERAL_EC_HOST_CMD
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default 256
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help
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This is the port size used by the Host and EC to communicate over
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the shared memory region to return the host command parameter data.
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if ESPI_XEC_V2
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config ESPI_OOB_CHANNEL
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@ -448,7 +448,8 @@ static int init_acpi_ec0(const struct device *dev)
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#endif /* CONFIG_ESPI_PERIPHERAL_HOST_IO */
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#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT
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#if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD) || \
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defined(CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT)
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static const struct xec_acpi_ec_config xec_acpi_ec1_cfg = {
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.regbase = DT_REG_ADDR(DT_NODELABEL(acpi_ec1)),
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@ -462,7 +463,11 @@ static void acpi_ec1_ibf_isr(const struct device *dev)
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(struct espi_xec_data *const)dev->data;
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struct espi_event evt = {
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.evt_type = ESPI_BUS_PERIPHERAL_NOTIFICATION,
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#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
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.evt_details = ESPI_PERIPHERAL_EC_HOST_CMD,
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#else
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.evt_details = ESPI_PERIPHERAL_HOST_IO_PVT,
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#endif
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.evt_data = ESPI_PERIPHERAL_NODATA
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};
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@ -509,11 +514,17 @@ static int init_acpi_ec1(const struct device *dev)
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struct espi_xec_config *const cfg = ESPI_XEC_CONFIG(dev);
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struct espi_iom_regs *regs = (struct espi_iom_regs *)cfg->base_addr;
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#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
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regs->IOHBAR[IOB_ACPI_EC1] =
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(CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM << 16) |
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MCHP_ESPI_IO_BAR_HOST_VALID;
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#else
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regs->IOHBAR[IOB_ACPI_EC1] =
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CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT_PORT_NUM |
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MCHP_ESPI_IO_BAR_HOST_VALID;
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regs->IOHBAR[IOB_MBOX] = ESPI_XEC_MBOX_BAR_ADDRESS |
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MCHP_ESPI_IO_BAR_HOST_VALID;
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#endif
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return 0;
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}
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@ -523,7 +534,123 @@ static int init_acpi_ec1(const struct device *dev)
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#undef INIT_ACPI_EC1
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#define INIT_ACPI_EC1 init_acpi_ec1
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#endif /* CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT */
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#endif /* CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD || CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT */
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#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
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BUILD_ASSERT(DT_NODE_HAS_STATUS(DT_NODELABEL(emi0), okay),
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"XEC EMI0 DT node is disabled!");
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struct xec_emi_config {
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uintptr_t regbase;
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};
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static const struct xec_emi_config xec_emi0_cfg = {
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.regbase = DT_REG_ADDR(DT_NODELABEL(emi0)),
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};
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#ifdef CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION
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static uint8_t ec_host_cmd_sram[CONFIG_ESPI_XEC_PERIPHERAL_HOST_CMD_PARAM_SIZE +
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CONFIG_ESPI_XEC_PERIPHERAL_ACPI_SHD_MEM_SIZE];
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#else
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static uint8_t ec_host_cmd_sram[CONFIG_ESPI_XEC_PERIPHERAL_HOST_CMD_PARAM_SIZE];
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#endif
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static int init_emi0(const struct device *dev)
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{
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struct espi_xec_config *const cfg = ESPI_XEC_CONFIG(dev);
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struct espi_iom_regs *regs = (struct espi_iom_regs *)cfg->base_addr;
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struct emi_regs *emi_hw =
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(struct emi_regs *)xec_emi0_cfg.regbase;
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regs->IOHBAR[IOB_EMI0] =
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(CONFIG_ESPI_PERIPHERAL_HOST_CMD_PARAM_PORT_NUM << 16) |
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MCHP_ESPI_IO_BAR_HOST_VALID;
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emi_hw->MEM_BA_0 = (uint32_t)ec_host_cmd_sram;
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#ifdef CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION
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emi_hw->MEM_RL_0 = CONFIG_ESPI_XEC_PERIPHERAL_HOST_CMD_PARAM_SIZE +
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CONFIG_ESPI_XEC_PERIPHERAL_ACPI_SHD_MEM_SIZE;
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#else
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emi_hw->MEM_RL_0 = CONFIG_ESPI_XEC_PERIPHERAL_HOST_CMD_PARAM_SIZE;
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#endif
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emi_hw->MEM_WL_0 = CONFIG_ESPI_XEC_PERIPHERAL_HOST_CMD_PARAM_SIZE;
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return 0;
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}
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#undef INIT_EMI0
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#define INIT_EMI0 init_emi0
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#endif /* CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD */
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#ifdef CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE
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static int ecust_rd_req(const struct device *dev,
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enum lpc_peripheral_opcode op,
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uint32_t *data)
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{
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ARG_UNUSED(dev);
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switch (op) {
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#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
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case ECUSTOM_HOST_CMD_GET_PARAM_MEMORY:
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*data = (uint32_t)ec_host_cmd_sram;
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break;
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#endif
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int ecust_wr_req(const struct device *dev,
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enum lpc_peripheral_opcode op,
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uint32_t *data)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(op);
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ARG_UNUSED(data);
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return -EINVAL;
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}
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#endif /* CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE */
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#if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD) && \
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defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
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static int eacpi_shm_rd_req(const struct device *dev,
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enum lpc_peripheral_opcode op,
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uint32_t *data)
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{
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ARG_UNUSED(dev);
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switch (op) {
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case EACPI_GET_SHARED_MEMORY:
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*data = (uint32_t)&ec_host_cmd_sram[CONFIG_ESPI_XEC_PERIPHERAL_HOST_CMD_PARAM_SIZE];
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int eacpi_shm_wr_req(const struct device *dev,
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enum lpc_peripheral_opcode op,
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uint32_t *data)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(op);
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ARG_UNUSED(data);
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return -EINVAL;
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}
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#endif /* CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION */
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#ifdef CONFIG_ESPI_PERIPHERAL_DEBUG_PORT_80
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@ -754,6 +881,10 @@ static const struct espi_lpc_req espi_lpc_req_tbl[] = {
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#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO
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{ EACPI_START_OPCODE, EACPI_MAX_OPCODE, eacpi_rd_req, eacpi_wr_req },
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#endif
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#if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD) && \
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defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
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{ EACPI_GET_SHARED_MEMORY, EACPI_GET_SHARED_MEMORY, eacpi_shm_rd_req, eacpi_shm_wr_req},
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#endif
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#ifdef CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE
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{ ECUSTOM_START_OPCODE, ECUSTOM_MAX_OPCODE, ecust_rd_req, ecust_wr_req},
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#endif
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50
soc/arm/microchip_mec/mec172x/reg/mec172x_emi.h
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50
soc/arm/microchip_mec/mec172x/reg/mec172x_emi.h
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@ -0,0 +1,50 @@
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/*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _MEC172X_EMI_H
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#define _MEC172X_EMI_H
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#include <stdint.h>
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#include <stddef.h>
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/** @brief Embedded Memory Interface (EMI) Registers */
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struct emi_regs {
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volatile uint8_t RT_HOST_TO_EC;
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volatile uint8_t RT_EC_TO_HOST;
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volatile uint8_t EC_ADDR_LSB;
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volatile uint8_t EC_ADDR_MSB;
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volatile uint8_t EC_DATA_0; /* +0x04 */
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volatile uint8_t EC_DATA_1;
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volatile uint8_t EC_DATA_2;
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volatile uint8_t EC_DATA_3;
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volatile uint8_t INTR_SRC_LSB; /* +0x08 */
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volatile uint8_t INTR_SRC_MSB;
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volatile uint8_t INTR_MSK_LSB;
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volatile uint8_t INTR_MSK_MSB;
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volatile uint8_t APPID; /* +0x0C */
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uint16_t RSVD1[3];
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volatile uint8_t APPID_ASSGN; /* +0x10 */
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uint16_t RSVD2[3];
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uint32_t RSVD3[(0x100 - 0x14) / 4];
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volatile uint8_t HOST_TO_EC; /* +0x100 */
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volatile uint8_t EC_TO_HOST;
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uint16_t RSVD4[1];
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volatile uint32_t MEM_BA_0; /* +0x104 */
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volatile uint16_t MEM_RL_0; /* +0x108 */
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volatile uint16_t MEM_WL_0;
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volatile uint32_t MEM_BA_1; /* +0x10C */
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volatile uint16_t MEM_RL_1; /* +0x110 */
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volatile uint16_t MEM_WL_1;
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volatile uint16_t INTR_SET; /* +0x114 */
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volatile uint16_t HOST_CLR_EN; /* +0x116 */
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uint32_t RSVD5[2];
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volatile uint32_t APPID_STS_1; /* +0x120 */
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volatile uint32_t APPID_STS_2;
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volatile uint32_t APPID_STS_3;
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volatile uint32_t APPID_STS_4;
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};
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#endif /* #ifndef _MEC172X_EMI_H */
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@ -39,6 +39,7 @@
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#include "reg/mec172x_pcr.h"
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#include "reg/mec172x_qspi.h"
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#include "reg/mec172x_vbat.h"
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#include "reg/mec172x_emi.h"
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/* common peripheral register defines */
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#include "../common/reg/mec_acpi_ec.h"
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