soc: arm: nxp_imx: rt: refactor flexspi boot config
* Move definition of flexspi_nor_config_t into soc/ dir so it can be shared by all i.MX RT based boards. * Use Kconfig symbol CONFIG_NXP_IMX_RT_BOOT_HEADER instead of HAL define (which is set based on the Kconfig symbol) * Rename board files to flexspi_nor_config.c since they are already namespaced by the board dir. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
parent
094a8ac132
commit
40fcb1ce9b
6 changed files with 99 additions and 306 deletions
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@ -6,5 +6,5 @@
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zephyr_library()
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zephyr_library_sources(pinmux.c)
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zephyr_sources_ifdef(CONFIG_BOOT_FLEXSPI_NOR mmswiftio_flexspi_nor_config.c)
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zephyr_sources_ifdef(CONFIG_BOOT_FLEXSPI_NOR flexspi_nor_config.c)
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zephyr_sources_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA mmswiftio_sdram_ini_dcd.c)
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@ -6,9 +6,9 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "mmswiftio_flexspi_nor_config.h"
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#include <flexspi_nor_config.h>
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#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
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#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
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__attribute__((section(".boot_hdr.conf")))
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#elif defined(__ICCARM__)
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@ -40,4 +40,4 @@ const struct flexspi_nor_config_t Qspiflash_config = {
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.blockSize = 256u * 1024u,
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.isUniformBlockSize = false,
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};
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#endif /* XIP_BOOT_HEADER_ENABLE */
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#endif /* CONFIG_NXP_IMX_RT_BOOT_HEADER */
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@ -10,5 +10,5 @@ if(CONFIG_PINMUX)
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zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
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endif()
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zephyr_library_sources(teensy4_flexspi_nor_config.c)
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zephyr_library_sources(flexspi_nor_config.c)
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zephyr_library_sources_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA teensy4_sdram_ini_dcd.c)
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@ -7,9 +7,9 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "teensy4_flexspi_nor_config.h"
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#include <flexspi_nor_config.h>
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#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
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#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
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__attribute__((section(".boot_hdr.conf")))
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#elif defined(__ICCARM__)
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@ -41,4 +41,4 @@ const struct flexspi_nor_config_t Qspiflash_config = {
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.blockSize = 256u * 1024u,
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.isUniformBlockSize = false,
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};
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#endif /* XIP_BOOT_HEADER_ENABLE */
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#endif /* CONFIG_NXP_IMX_RT_BOOT_HEADER */
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@ -1,241 +0,0 @@
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/*
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* Copyright (c) 2019, MADMACHINE LIMITED
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* Copyright (c) 2021, Bernhard Kraemer
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*
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* refer to hal_nxp board file
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __TEENSY4_FLEXSPI_NOR_CONFIG__
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#define __TEENSY4_FLEXSPI_NOR_CONFIG__
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#include <zephyr/types.h>
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#include "fsl_common.h"
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#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)
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#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL)
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#define FLEXSPI_CFG_BLK_SIZE (512)
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#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
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#define CMD_INDEX_READ 0
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#define CMD_INDEX_READSTATUS 1
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#define CMD_INDEX_WRITEENABLE 2
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#define CMD_INDEX_WRITE 4
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#define CMD_LUT_SEQ_IDX_READ 0
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#define CMD_LUT_SEQ_IDX_READSTATUS 1
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#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
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#define CMD_LUT_SEQ_IDX_WRITE 9
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#define CMD_SDR 0x01
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#define CMD_DDR 0x21
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#define RADDR_SDR 0x02
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#define RADDR_DDR 0x22
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#define CADDR_SDR 0x03
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#define CADDR_DDR 0x23
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#define MODE1_SDR 0x04
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#define MODE1_DDR 0x24
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#define MODE2_SDR 0x05
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#define MODE2_DDR 0x25
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#define MODE4_SDR 0x06
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#define MODE4_DDR 0x26
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#define MODE8_SDR 0x07
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#define MODE8_DDR 0x27
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#define WRITE_SDR 0x08
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#define WRITE_DDR 0x28
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#define READ_SDR 0x09
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#define READ_DDR 0x29
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#define LEARN_SDR 0x0A
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#define LEARN_DDR 0x2A
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#define DATSZ_SDR 0x0B
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#define DATSZ_DDR 0x2B
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#define DUMMY_SDR 0x0C
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#define DUMMY_DDR 0x2C
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#define DUMMY_RWDS_SDR 0x0D
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#define DUMMY_RWDS_DDR 0x2D
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#define JMP_ON_CS 0x1F
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#define STOP 0
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#define FLEXSPI_1PAD 0
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#define FLEXSPI_2PAD 1
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#define FLEXSPI_4PAD 2
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#define FLEXSPI_8PAD 3
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#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
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(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | \
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FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
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FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
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enum {
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kFlexSpiSerialClk_30MHz = 1,
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kFlexSpiSerialClk_50MHz = 2,
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kFlexSpiSerialClk_60MHz = 3,
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kFlexSpiSerialClk_75MHz = 4,
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kFlexSpiSerialClk_80MHz = 5,
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kFlexSpiSerialClk_100MHz = 6,
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kFlexSpiSerialClk_133MHz = 7,
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kFlexSpiSerialClk_166MHz = 8,
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kFlexSpiSerialClk_200MHz = 9,
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};
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enum {
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kFlexSpiClk_SDR,
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kFlexSpiClk_DDR, };
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enum {
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kFlexSPIReadSampleClk_LoopbackInternally = 0,
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kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
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kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
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kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
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};
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enum { kFlexSpiMiscOffset_DiffClkEnable = 0,
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kFlexSpiMiscOffset_Ck2Enable = 1,
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kFlexSpiMiscOffset_ParallelEnable = 2,
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kFlexSpiMiscOffset_WordAddressableEnable = 3,
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kFlexSpiMiscOffset_SafeConfigFreqEnable = 4,
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kFlexSpiMiscOffset_PadSettingOverrideEnable = 5,
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kFlexSpiMiscOffset_DdrModeEnable = 6, };
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enum { kFlexSpiDeviceType_SerialNOR = 1,
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kFlexSpiDeviceType_SerialNAND = 2,
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kFlexSpiDeviceType_SerialRAM = 3,
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kFlexSpiDeviceType_MCP_NOR_NAND = 0x12,
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kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, };
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enum { kSerialFlash_1Pad = 1,
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kSerialFlash_2Pads = 2,
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kSerialFlash_4Pads = 4,
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kSerialFlash_8Pads = 8, };
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struct flexspi_lut_seq_t {
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uint8_t seqNum;
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uint8_t seqId;
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uint16_t reserved;
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};
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enum { kDeviceConfigCmdType_Generic,
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kDeviceConfigCmdType_QuadEnable,
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kDeviceConfigCmdType_Spi2Xpi,
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kDeviceConfigCmdType_Xpi2Spi,
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kDeviceConfigCmdType_Spi2NoCmd,
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kDeviceConfigCmdType_Reset, };
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struct flexspi_mem_config_t {
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uint32_t tag;
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uint32_t version;
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uint32_t reserved0;
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uint8_t readSampleClkSrc;
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uint8_t csHoldTime;
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uint8_t csSetupTime;
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uint8_t columnAddressWidth;
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uint8_t deviceModeCfgEnable;
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uint8_t deviceModeType;
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uint16_t waitTimeCfgCommands;
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struct flexspi_lut_seq_t deviceModeSeq;
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uint32_t deviceModeArg;
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uint8_t configCmdEnable;
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uint8_t configModeType[3];
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struct flexspi_lut_seq_t configCmdSeqs[3];
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uint32_t reserved1;
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uint32_t configCmdArgs[3];
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uint32_t reserved2;
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uint32_t controllerMiscOption;
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uint8_t deviceType;
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uint8_t sflashPadType;
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uint8_t serialClkFreq;
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uint8_t lutCustomSeqEnable;
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uint32_t reserved3[2];
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uint32_t sflashA1Size;
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uint32_t sflashA2Size;
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uint32_t sflashB1Size;
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uint32_t sflashB2Size;
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uint32_t csPadSettingOverride;
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uint32_t sclkPadSettingOverride;
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uint32_t dataPadSettingOverride;
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uint32_t dqsPadSettingOverride;
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uint32_t timeoutInMs;
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uint32_t commandInterval;
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uint16_t dataValidTime[2];
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uint16_t busyOffset;
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uint16_t busyBitPolarity;
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uint32_t lookupTable[64];
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struct flexspi_lut_seq_t lutCustomSeq[12];
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uint32_t reserved4[4];
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};
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#define NOR_CMD_INDEX_READ CMD_INDEX_READ
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#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS
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#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE
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#define NOR_CMD_INDEX_ERASESECTOR 3
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#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE
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#define NOR_CMD_INDEX_CHIPERASE 5
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#define NOR_CMD_INDEX_DUMMY 6
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#define NOR_CMD_INDEX_ERASEBLOCK 7
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#define NOR_CMD_LUT_SEQ_IDX_READ \
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CMD_LUT_SEQ_IDX_READ
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#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
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CMD_LUT_SEQ_IDX_READSTATUS
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#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
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2
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#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
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CMD_LUT_SEQ_IDX_WRITEENABLE
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#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
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4
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#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR \
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5
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#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK \
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8
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#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
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CMD_LUT_SEQ_IDX_WRITE
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#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE \
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11
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#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP \
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13
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#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
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14
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#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
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15
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struct flexspi_nor_config_t {
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struct flexspi_mem_config_t memConfig;
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uint32_t pageSize;
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uint32_t sectorSize;
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uint8_t ipcmdSerialClkFreq;
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uint8_t isUniformBlockSize;
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uint8_t reserved0[2];
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uint8_t serialNorType;
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uint8_t needExitNoCmdMode;
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uint8_t halfClkForNonReadCmd;
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uint8_t needRestoreNoCmdMode;
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uint32_t blockSize;
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uint32_t reserve2[11];
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};
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __TEENSY4_FLEXSPI_NOR_CONFIG__ */
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@ -6,8 +6,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __MMSWIFTIO_FLEXSPI_NOR_CONFIG__
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#define __MMSWIFTIO_FLEXSPI_NOR_CONFIG__
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#ifndef __FLEXSPI_NOR_CONFIG__
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#define __FLEXSPI_NOR_CONFIG__
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#include <zephyr/types.h>
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#include "fsl_common.h"
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FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
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FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
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/* For flexspi_mem_config.serialClkFreq */
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#if defined(CONFIG_SOC_MIMXRT1011)
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enum {
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kFlexSpiSerialClk_30MHz = 1,
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kFlexSpiSerialClk_50MHz = 2,
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kFlexSpiSerialClk_60MHz = 3,
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kFlexSpiSerialClk_75MHz = 4,
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kFlexSpiSerialClk_80MHz = 5,
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kFlexSpiSerialClk_100MHz = 6,
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kFlexSpiSerialClk_120MHz = 7,
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kFlexSpiSerialClk_133MHz = 8,
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};
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#elif defined(CONFIG_SOC_MIMXRT1015) || defined(CONFIG_SOC_MIMXRT1021) || \
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defined(CONFIG_SOC_MIMXRT1024)
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enum {
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kFlexSpiSerialClk_30MHz = 1,
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kFlexSpiSerialClk_50MHz = 2,
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kFlexSpiSerialClk_60MHz = 3,
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kFlexSpiSerialClk_75MHz = 4,
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kFlexSpiSerialClk_80MHz = 5,
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kFlexSpiSerialClk_100MHz = 6,
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kFlexSpiSerialClk_133MHz = 7,
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};
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#elif defined(CONFIG_SOC_MIMXRT1051) || defined(CONFIG_SOC_MIMXRT1052)
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enum {
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kFlexSpiSerialClk_30MHz = 1,
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kFlexSpiSerialClk_50MHz = 2,
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kFlexSpiSerialClk_166MHz = 8,
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kFlexSpiSerialClk_200MHz = 9,
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};
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#elif defined(CONFIG_SOC_MIMXRT1061) || defined(CONFIG_SOC_MIMXRT1062) || \
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defined(CONFIG_SOC_MIMXRT1062) || defined(CONFIG_SOC_MIMXRT1064)
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enum {
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kFlexSpiSerialClk_30MHz = 1,
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kFlexSpiSerialClk_50MHz = 2,
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kFlexSpiSerialClk_60MHz = 3,
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kFlexSpiSerialClk_75MHz = 4,
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kFlexSpiSerialClk_80MHz = 5,
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kFlexSpiSerialClk_100MHz = 6,
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kFlexSpiSerialClk_120MHz = 7,
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kFlexSpiSerialClk_133MHz = 8,
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kFlexSpiSerialClk_166MHz = 9,
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};
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#else
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#error "kFlexSpiSerialClk is not defined for this SoC"
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#endif
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/* For flexspi_mem_config.controllerMiscOption */
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enum {
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kFlexSpiClk_SDR,
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kFlexSpiClk_DDR, };
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kFlexSpiClk_DDR,
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};
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/* For flexspi_mem_config.readSampleClkSrc */
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enum {
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kFlexSPIReadSampleClk_LoopbackInternally = 0,
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kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
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kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
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};
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/* For flexspi_mem_config.controllerMiscOption */
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enum {
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kFlexSpiMiscOffset_DiffClkEnable = 0,
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kFlexSpiMiscOffset_Ck2Enable = 1,
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kFlexSpiMiscOffset_ParallelEnable = 2,
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kFlexSpiMiscOffset_WordAddressableEnable = 3,
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kFlexSpiMiscOffset_SafeConfigFreqEnable = 4,
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kFlexSpiMiscOffset_PadSettingOverrideEnable = 5,
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kFlexSpiMiscOffset_DdrModeEnable = 6,
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};
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enum { kFlexSpiMiscOffset_DiffClkEnable = 0,
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kFlexSpiMiscOffset_Ck2Enable = 1,
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kFlexSpiMiscOffset_ParallelEnable = 2,
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kFlexSpiMiscOffset_WordAddressableEnable = 3,
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kFlexSpiMiscOffset_SafeConfigFreqEnable = 4,
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kFlexSpiMiscOffset_PadSettingOverrideEnable = 5,
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kFlexSpiMiscOffset_DdrModeEnable = 6, };
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/* For flexspi_mem_config.deviceType */
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enum {
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kFlexSpiDeviceType_SerialNOR = 1,
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kFlexSpiDeviceType_SerialNAND = 2,
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kFlexSpiDeviceType_SerialRAM = 3,
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kFlexSpiDeviceType_MCP_NOR_NAND = 0x12,
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kFlexSpiDeviceType_MCP_NOR_RAM = 0x13,
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};
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/* For flexspi_mem_config.sflashPadType */
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enum {
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kSerialFlash_1Pad = 1,
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kSerialFlash_2Pads = 2,
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kSerialFlash_4Pads = 4,
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kSerialFlash_8Pads = 8,
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};
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enum { kFlexSpiDeviceType_SerialNOR = 1,
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kFlexSpiDeviceType_SerialNAND = 2,
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kFlexSpiDeviceType_SerialRAM = 3,
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kFlexSpiDeviceType_MCP_NOR_NAND = 0x12,
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kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, };
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enum { kSerialFlash_1Pad = 1,
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kSerialFlash_2Pads = 2,
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kSerialFlash_4Pads = 4,
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kSerialFlash_8Pads = 8, };
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enum {
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kDeviceConfigCmdType_Generic,
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kDeviceConfigCmdType_QuadEnable,
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kDeviceConfigCmdType_Spi2Xpi,
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||||
kDeviceConfigCmdType_Xpi2Spi,
|
||||
kDeviceConfigCmdType_Spi2NoCmd,
|
||||
kDeviceConfigCmdType_Reset,
|
||||
};
|
||||
|
||||
struct flexspi_lut_seq_t {
|
||||
uint8_t seqNum;
|
||||
|
@ -119,15 +176,6 @@ struct flexspi_lut_seq_t {
|
|||
uint16_t reserved;
|
||||
};
|
||||
|
||||
|
||||
enum { kDeviceConfigCmdType_Generic,
|
||||
kDeviceConfigCmdType_QuadEnable,
|
||||
kDeviceConfigCmdType_Spi2Xpi,
|
||||
kDeviceConfigCmdType_Xpi2Spi,
|
||||
kDeviceConfigCmdType_Spi2NoCmd,
|
||||
kDeviceConfigCmdType_Reset, };
|
||||
|
||||
|
||||
struct flexspi_mem_config_t {
|
||||
uint32_t tag;
|
||||
uint32_t version;
|
||||
|
@ -179,7 +227,6 @@ struct flexspi_mem_config_t {
|
|||
uint32_t reserved4[4];
|
||||
};
|
||||
|
||||
|
||||
#define NOR_CMD_INDEX_READ CMD_INDEX_READ
|
||||
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS
|
||||
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE
|
||||
|
@ -189,31 +236,18 @@ struct flexspi_mem_config_t {
|
|||
#define NOR_CMD_INDEX_DUMMY 6
|
||||
#define NOR_CMD_INDEX_ERASEBLOCK 7
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ \
|
||||
CMD_LUT_SEQ_IDX_READ
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
|
||||
CMD_LUT_SEQ_IDX_READSTATUS
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
|
||||
2
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
|
||||
CMD_LUT_SEQ_IDX_WRITEENABLE
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
|
||||
4
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR \
|
||||
5
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK \
|
||||
8
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
|
||||
CMD_LUT_SEQ_IDX_WRITE
|
||||
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE \
|
||||
11
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP \
|
||||
13
|
||||
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
|
||||
14
|
||||
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
|
||||
15
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE
|
||||
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13
|
||||
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14
|
||||
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15
|
||||
|
||||
struct flexspi_nor_config_t {
|
||||
struct flexspi_mem_config_t memConfig;
|
Loading…
Add table
Add a link
Reference in a new issue