intc: intc_cavs: Replace DT_CAVS_ICTL_BASE_ADDR with new macros
Replace various drivers and soc code that use DT_CAVS_ICTL_BASE_ADDR with DT_REG_ADDR(DT_NODELABEL(cavs0)). Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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492fbf7bba
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e53ddb5037
3 changed files with 4 additions and 4 deletions
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@ -193,7 +193,7 @@ static int cavs_idc_set_enabled(struct device *dev, int enable)
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idc_write(REG_IDCCTL, i, mask);
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/* FIXME: when we have API to enable IRQ on specific core. */
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sys_set_bit(DT_CAVS_ICTL_BASE_ADDR + 0x04 +
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sys_set_bit(DT_REG_ADDR(DT_NODELABEL(cavs0)) + 0x04 +
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CAVS_ICTL_INT_CPU_OFFSET(i),
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CAVS_IRQ_NUMBER(DT_INST_IRQN(0)));
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}
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@ -172,7 +172,7 @@ void smp_timer_init(void)
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* FIXME: Done in this way because we don't have an API
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* to enable interrupts per CPU.
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*/
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sys_set_bit(DT_CAVS_ICTL_BASE_ADDR
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sys_set_bit(DT_REG_ADDR(DT_NODELABEL(cavs0))
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+ CAVS_ICTL_INT_CPU_OFFSET(arch_curr_cpu()->id)
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+ 0x04,
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22 + TIMER);
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@ -185,7 +185,7 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
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idc_reg = idc_read(REG_IDCCTL, cpu_num);
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idc_reg |= REG_IDCCTL_IDCTBIE(0);
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idc_write(REG_IDCCTL, cpu_num, idc_reg);
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sys_set_bit(DT_CAVS_ICTL_BASE_ADDR + 0x04 +
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sys_set_bit(DT_REG_ADDR(DT_NODELABEL(cavs0)) + 0x04 +
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CAVS_ICTL_INT_CPU_OFFSET(cpu_num), 8);
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/* Send power up message to the other core */
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@ -198,7 +198,7 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
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idc_reg = idc_read(REG_IDCCTL, cpu_num);
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idc_reg &= ~REG_IDCCTL_IDCTBIE(0);
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idc_write(REG_IDCCTL, cpu_num, idc_reg);
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sys_clear_bit(DT_CAVS_ICTL_BASE_ADDR + 0x04 +
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sys_clear_bit(DT_REG_ADDR(DT_NODELABEL(cavs0)) + 0x04 +
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CAVS_ICTL_INT_CPU_OFFSET(cpu_num), 8);
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do {
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