michaelh/zephyr
1
0
Fork 0
Code Releases Activity

intc: intc_cavs: Replace DT_CAVS_ICTL_BASE_ADDR with new macros

Browse source 
Replace various drivers and soc code that use DT_CAVS_ICTL_BASE_ADDR
with DT_REG_ADDR(DT_NODELABEL(cavs0)).

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-04-20 10:39:35 -05:00 • committed by Kumar Gala
commit e53ddb5037
3 changed files with 4 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

2
drivers/ipm/ipm_cavs_idc.c
View file

@ -193,7 +193,7 @@ static int cavs_idc_set_enabled(struct device *dev, int enable)
idc_write(REG_IDCCTL, i, mask);
/* FIXME: when we have API to enable IRQ on specific core. */
sys_set_bit(DT_CAVS_ICTL_BASE_ADDR + 0x04 +
sys_set_bit(DT_REG_ADDR(DT_NODELABEL(cavs0)) + 0x04 +
CAVS_ICTL_INT_CPU_OFFSET(i),
CAVS_IRQ_NUMBER(DT_INST_IRQN(0)));
}

2
drivers/timer/cavs_timer.c
View file

@ -172,7 +172,7 @@ void smp_timer_init(void)
* FIXME: Done in this way because we don't have an API
* to enable interrupts per CPU.
*/
sys_set_bit(DT_CAVS_ICTL_BASE_ADDR
sys_set_bit(DT_REG_ADDR(DT_NODELABEL(cavs0))
+ CAVS_ICTL_INT_CPU_OFFSET(arch_curr_cpu()->id)
+ 0x04,
22 + TIMER);

4
soc/xtensa/intel_apl_adsp/soc_mp.c
View file

@ -185,7 +185,7 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
idc_reg = idc_read(REG_IDCCTL, cpu_num);
idc_reg |= REG_IDCCTL_IDCTBIE(0);
idc_write(REG_IDCCTL, cpu_num, idc_reg);
sys_set_bit(DT_CAVS_ICTL_BASE_ADDR + 0x04 +
sys_set_bit(DT_REG_ADDR(DT_NODELABEL(cavs0)) + 0x04 +
CAVS_ICTL_INT_CPU_OFFSET(cpu_num), 8);
/* Send power up message to the other core */
@ -198,7 +198,7 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
idc_reg = idc_read(REG_IDCCTL, cpu_num);
idc_reg &= ~REG_IDCCTL_IDCTBIE(0);
idc_write(REG_IDCCTL, cpu_num, idc_reg);
sys_clear_bit(DT_CAVS_ICTL_BASE_ADDR + 0x04 +
sys_clear_bit(DT_REG_ADDR(DT_NODELABEL(cavs0)) + 0x04 +
CAVS_ICTL_INT_CPU_OFFSET(cpu_num), 8);
do {