soc: nrf53: Add handling of secure-only code in init with TFM enabled
Add handling of secure-only code with TF-M enabled that can only be done from secure processing environment. Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
This commit is contained in:
Joakim Andersson
Carles Cufí
parent
17f8932f16
commit
aef46a8e51
5 changed files with 83 additions and 11 deletions
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@ -11,3 +11,9 @@ zephyr_library_sources_ifdef(CONFIG_PM
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zephyr_library_sources_ifdef(CONFIG_NRF53_SYNC_RTC
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sync_rtc.c
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)
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if (CONFIG_BUILD_WITH_TFM)
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zephyr_library_include_directories(
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$<TARGET_PROPERTY:tfm,TFM_BINARY_DIR>/install/interface/include
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)
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endif()
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@ -144,7 +144,7 @@ config SOC_DCDC_NRF53X_HV
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help
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Enable nRF53 series System on Chip High Voltage DC/DC converter.
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if !TRUSTED_EXECUTION_NONSECURE
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if !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM
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config SOC_ENABLE_LFXO
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bool "Enable LFXO"
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@ -206,14 +206,14 @@ config SOC_HFXO_CAP_INT_VALUE_X2
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capacitance value for the two capacitors. Set it to 14 to get 7.0 pF
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for each capacitor, 15 to get 7.5 pF, and so on.
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endif # !TRUSTED_EXECUTION_NONSECURE
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endif # !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM
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endif # SOC_NRF5340_CPUAPP
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config NRF_ENABLE_CACHE
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bool "Enable cache"
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depends on (SOC_NRF5340_CPUAPP && !TRUSTED_EXECUTION_NONSECURE) \
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depends on (SOC_NRF5340_CPUAPP && (!TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM)) \
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|| SOC_NRF5340_CPUNET
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default y
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help
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@ -223,6 +223,10 @@ config NRF_ENABLE_CACHE
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Instruction cache only (I-Cache) is available in nRF5340
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CPUNET (Network MCU).
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config BUILD_WITH_TFM
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# TF-M nRF53 platform enables the cache unconditionally.
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select NRF_ENABLE_CACHE if SOC_NRF5340_CPUAPP
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config NRF53_SYNC_RTC
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bool "Enable RTC clock synchronization"
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default y if LOG && !LOG_MODE_MINIMAL
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@ -26,6 +26,7 @@
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#elif defined(CONFIG_SOC_NRF5340_CPUNET)
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#include <hal/nrf_nvmc.h>
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#endif
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#include <soc_secure.h>
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#define PIN_XL1 0
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#define PIN_XL2 1
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@ -57,14 +58,18 @@ static int nordicsemi_nrf53_init(const struct device *arg)
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key = irq_lock();
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#if defined(CONFIG_SOC_NRF5340_CPUAPP) && defined(CONFIG_NRF_ENABLE_CACHE)
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/* Enable the instruction & data cache */
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#if !defined(CONFIG_BUILD_WITH_TFM)
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/* Enable the instruction & data cache.
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* This can only be done from secure code.
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* This is handled by the TF-M platform so we skip it when TF-M is
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* enabled.
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*/
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nrf_cache_enable(NRF_CACHE);
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#endif
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#elif defined(CONFIG_SOC_NRF5340_CPUNET) && defined(CONFIG_NRF_ENABLE_CACHE)
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nrf_nvmc_icache_config_set(NRF_NVMC, NRF_NVMC_ICACHE_ENABLE);
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#endif
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#if defined(CONFIG_SOC_NRF5340_CPUAPP) && \
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!defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
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#if defined(CONFIG_SOC_ENABLE_LFXO)
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nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS,
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IS_ENABLED(CONFIG_SOC_LFXO_CAP_INT_6PF) ?
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@ -74,13 +79,18 @@ static int nordicsemi_nrf53_init(const struct device *arg)
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IS_ENABLED(CONFIG_SOC_LFXO_CAP_INT_9PF) ?
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NRF_OSCILLATORS_LFXO_CAP_9PF :
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NRF_OSCILLATORS_LFXO_CAP_EXTERNAL);
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/* This can only be done from secure code. */
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#if !defined(CONFIG_BUILD_WITH_TFM)
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/* This can only be done from secure code.
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* This is handled by the TF-M platform so we skip it when TF-M is
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* enabled.
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*/
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nrf_gpio_pin_mcu_select(PIN_XL1, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
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nrf_gpio_pin_mcu_select(PIN_XL2, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
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#endif
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#endif /* !defined(CONFIG_BUILD_WITH_TFM) */
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#endif /* defined(CONFIG_SOC_ENABLE_LFXO) */
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#if defined(CONFIG_SOC_HFXO_CAP_INTERNAL)
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/* This register is only accessible from secure code. */
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uint32_t xosc32mtrim = NRF_FICR->XOSC32MTRIM;
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uint32_t xosc32mtrim = soc_secure_read_xosc32mtrim();
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/* As specified in the nRF5340 PS:
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* CAPVALUE = (((FICR->XOSC32MTRIM.SLOPE+56)*(CAPACITANCE*2-14))
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* +((FICR->XOSC32MTRIM.OFFSET-8)<<4)+32)>>6;
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@ -99,7 +109,6 @@ static int nordicsemi_nrf53_init(const struct device *arg)
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#elif defined(CONFIG_SOC_HFXO_CAP_EXTERNAL)
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nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS, false, 0);
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#endif
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#endif /* defined(CONFIG_SOC_NRF5340_CPUAPP) && ... */
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#if defined(CONFIG_SOC_DCDC_NRF53X_APP)
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nrf_regulators_dcdcen_set(NRF_REGULATORS, true);
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53
soc/arm/nordic_nrf/nrf53/soc_secure.h
Normal file
53
soc/arm/nordic_nrf/nrf53/soc_secure.h
Normal file
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@ -0,0 +1,53 @@
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/*
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* Copyright (c) 2019 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <hal/nrf_gpio.h>
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#if defined(CONFIG_SOC_NRF5340_CPUAPP)
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#if defined(CONFIG_BUILD_WITH_TFM)
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/* Use TF-M platform services */
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#include "tfm_ioctl_api.h"
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#include "hal/nrf_gpio.h"
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static inline void soc_secure_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin_mcusel_t mcu)
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{
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uint32_t result;
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enum tfm_platform_err_t err;
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err = tfm_platform_gpio_pin_mcu_select(pin_number, mcu, &result);
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__ASSERT(err == TFM_PLATFORM_ERR_SUCCESS, "TFM platform error (%d)", err);
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__ASSERT(result == 0, "GPIO service error (%d)", result);
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}
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#if defined(CONFIG_SOC_HFXO_CAP_INTERNAL)
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static inline uint32_t soc_secure_read_xosc32mtrim(void)
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{
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uintptr_t ptr = (uintptr_t)&NRF_FICR_S->XOSC32MTRIM;
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enum tfm_platform_err_t err;
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uint32_t result;
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uint32_t xosc32mtrim;
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err = tfm_platform_mem_read(&xosc32mtrim, ptr, 4, &result);
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__ASSERT(err == TFM_PLATFORM_ERR_SUCCESS, "TFM platform error (%d)", err);
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__ASSERT(result == 0, "Read service error (%d)", result);
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return xosc32mtrim;
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}
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#endif /* defined(CONFIG_SOC_HFXO_CAP_INTERNAL) */
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#else
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#include <nrf.h>
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/* Do this directly from secure processing environment. */
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static inline void soc_secure_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin_mcusel_t mcu)
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{
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nrf_gpio_pin_mcu_select(pin_number, mcu);
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}
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static inline uint32_t soc_secure_read_xosc32mtrim(void)
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{
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return NRF_FICR_S->XOSC32MTRIM;
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}
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#endif /* defined CONFIG_BUILD_WITH_TFM */
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#endif /* defined(CONFIG_SOC_NRF5340_CPUAPP) */
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2
west.yml
2
west.yml
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@ -218,7 +218,7 @@ manifest:
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groups:
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- debug
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- name: trusted-firmware-m
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revision: c8134809a9439571c54d36ef39210270dbee8f67
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revision: 5d32c3e64b3d589548e881eeeeb37d84944c90af
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path: modules/tee/tf-m/trusted-firmware-m
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groups:
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- tee
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