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ARC: boards: nSIM: memory layout overhaul

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Currently we use incorrect memory layout for SMP boards as
we put data (which need do be accessible from all cores) to
DCCM which is private for each CPU core.

This works for nSIM which doesn't simulate CCMs (as we don't pass
corresponding nSIM options for SMP configurations) however
it won't work if we run that code on real HW (we want to achieve
that nSIM configurations are also runnable on HAPS - FPGA platform).

Let's fix that issue by using DDR instead of CCMs for SMP
configurations (nsim_hs_smp and nsim_hs6x_smp).

While I'm at it - switch UP HS6x configuration (nsim_hs6x)
for DDR usage instead of CCMs - to make that configuration closer
to the HAPS config we have.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
This commit is contained in:
Evgeniy Paltsev 2022-05-02 19:24:41 +04:00 • committed by Carles Cufí
commit 38c24cd5aa
13 changed files with 79 additions and 36 deletions
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40
boards/arc/nsim/nsim-ccm-mem.dtsi Normal file
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@ -0,0 +1,40 @@
/*
* Copyright (c) 2022, Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "skeleton.dtsi"
#include <mem.h>
#ifndef ICCM_ADDR
#define ICCM_ADDR 0
#endif
#ifndef ICCM_SIZE
#define ICCM_SIZE DT_SIZE_M(1)
#endif
#ifndef DCCM_ADDR
#define DCCM_ADDR 80000000
#endif
#ifndef DCCM_SIZE
#define DCCM_SIZE DT_SIZE_M(1)
#endif
/ {
iccm0: iccm@ICCM_ADDR {
compatible = "arc,iccm";
reg = <DT_ADDR(ICCM_ADDR) ICCM_SIZE>;
};
dccm0: dccm@DCCM_ADDR {
compatible = "arc,dccm";
reg = <DT_ADDR(DCCM_ADDR) DCCM_SIZE>;
};
chosen {
zephyr,sram = &dccm0;
};
};

27
boards/arc/nsim/nsim-flat-mem.dtsi Normal file
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@ -0,0 +1,27 @@
/*
* Copyright (c) 2022, Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "skeleton.dtsi"
#include <mem.h>
#ifndef DDR_ADDR
#define DDR_ADDR 80000000
#endif
#ifndef DDR_SIZE
#define DDR_SIZE DT_SIZE_M(1)
#endif
/ {
ddr0: memory@DDR_ADDR {
device_type = "memory";
reg = <DT_ADDR(DDR_ADDR) DDR_SIZE>;
};
chosen {
zephyr,sram = &ddr0;
};
};

27
boards/arc/nsim/nsim.dtsi
View file

@ -9,22 +9,6 @@
#include "skeleton.dtsi"
#include <mem.h>
#ifndef ICCM_ADDR
#define ICCM_ADDR 0
#endif
#ifndef ICCM_SIZE
#define ICCM_SIZE DT_SIZE_K(1024)
#endif
#ifndef DCCM_ADDR
#define DCCM_ADDR 80000000
#endif
#ifndef DCCM_SIZE
#define DCCM_SIZE DT_SIZE_K(1024)
#endif
/ {
cpus {
#address-cells = <1>;
@ -37,16 +21,6 @@
};
};
iccm0: iccm@ICCM_ADDR {
compatible = "arc,iccm";
reg = <DT_ADDR(ICCM_ADDR) ICCM_SIZE>;
};
dccm0: dccm@DCCM_ADDR {
compatible = "arc,dccm";
reg = <DT_ADDR(DCCM_ADDR) DCCM_SIZE>;
};
uart0: uart@f0000000 {
compatible = "ns16550";
clock-frequency = <50000000>;
@ -58,7 +32,6 @@
};
chosen {
zephyr,sram = &dccm0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};

1
boards/arc/nsim/nsim_em.dtsi
View file

@ -7,6 +7,7 @@
/dts-v1/;
#include "nsim.dtsi"
#include "nsim-ccm-mem.dtsi"
/ {
cpus {

1
boards/arc/nsim/nsim_hs.dts
View file

@ -7,6 +7,7 @@
/dts-v1/;
#include "nsim.dtsi"
#include "nsim-ccm-mem.dtsi"
/ {
model = "snps,nsim_hs";

1
boards/arc/nsim/nsim_hs6x.dts
View file

@ -7,6 +7,7 @@
/dts-v1/;
#include "nsim.dtsi"
#include "nsim-flat-mem.dtsi"
/ {
model = "snps,nsim_hs";

1
boards/arc/nsim/nsim_hs6x_smp.dts
View file

@ -7,6 +7,7 @@
/dts-v1/;
#include "nsim.dtsi"
#include "nsim-flat-mem.dtsi"
/ {
model = "snps,nsim_hs";

1
boards/arc/nsim/nsim_hs_mpuv6.dts
View file

@ -7,6 +7,7 @@
/dts-v1/;
#include "nsim.dtsi"
#include "nsim-ccm-mem.dtsi"
/ {
model = "snps,nsim_hs";

1
boards/arc/nsim/nsim_hs_smp.dts
View file

@ -7,6 +7,7 @@
/dts-v1/;
#include "nsim.dtsi"
#include "nsim-flat-mem.dtsi"
/ {
model = "snps,nsim_hs";

3
soc/arc/snps_nsim/Kconfig.defconfig.hs6x
View file

@ -17,9 +17,6 @@ config NUM_IRQS
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 50000000
config HARVARD
default y
config CACHE_MANAGEMENT
default y

3
soc/arc/snps_nsim/Kconfig.defconfig.hs6x_smp
View file

@ -21,9 +21,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config CACHE_MANAGEMENT
default y
config HARVARD
default y
config ARC_CONNECT
default y

3
soc/arc/snps_nsim/Kconfig.defconfig.hs_smp
View file

@ -22,9 +22,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
# SMP simulation is slower than single core, 1 Mhz seems reasonable match with wallclock
default 1000000
config HARVARD
default y
config ARC_FIRQ
default y

6
soc/arc/snps_nsim/linker.ld
View file

@ -27,4 +27,10 @@
#define DCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_dccm))
#endif
/* SRAM - memory available for all cores in cluster. Can be used for both instructions and data */
#if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
#define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
#define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
#endif
#include <arch/arc/v2/linker.ld>