ITE: drivers/serial: add the UART driver for the PM callback function
IT8XXX2 uses shared ns16550.c driver which does not provide a power management callback(pm_action_cb), so create driver to handle IT8XXX2 specific UART features. note: pm_action_cb(old name: pm_control_fn) Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
parent
1b416f7fd1
commit
e29a15c0e3
10 changed files with 206 additions and 114 deletions
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@ -344,6 +344,8 @@
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/drivers/serial/serial_test.c @str4t0m
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/drivers/serial/Kconfig.xen @lorc @firscity
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/drivers/serial/uart_hvc_xen.c @lorc @firscity
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/drivers/serial/Kconfig.it8xxx2 @GTLin08
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/drivers/serial/uart_ite_it8xxx2.c @GTLin08
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/drivers/disk/ @jfischer-no
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/drivers/disk/sdmmc_sdhc.h @JunYangNXP
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/drivers/disk/sdmmc_spi.c @JunYangNXP
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@ -78,6 +78,12 @@
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current-speed = <460800>;
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clock-frequency = <1804800>;
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};
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&ite_uart1_wrapper {
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status = "okay";
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};
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&ite_uart2_wrapper {
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status = "okay";
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};
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&pwm0 {
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status = "okay";
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prescaler-cx = <PWM_PRESCALER_C6>;
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@ -4,6 +4,7 @@ zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_UART_ALTERA_JTAG uart_altera_jtag_hal.c)
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zephyr_library_sources_ifdef(CONFIG_UART_TELINK_B91 uart_b91.c)
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zephyr_library_sources_ifdef(CONFIG_UART_IMX uart_imx.c)
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zephyr_library_sources_ifdef(CONFIG_UART_ITE_IT8XXX2 uart_ite_it8xxx2.c)
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zephyr_library_sources_ifdef(CONFIG_UART_CC13XX_CC26XX uart_cc13xx_cc26xx.c)
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zephyr_library_sources_ifdef(CONFIG_UART_CC32XX uart_cc32xx.c)
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zephyr_library_sources_ifdef(CONFIG_UART_CMSDK_APB uart_cmsdk_apb.c)
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@ -117,6 +117,8 @@ source "drivers/serial/Kconfig.miv"
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source "drivers/serial/Kconfig.imx"
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source "drivers/serial/Kconfig.it8xxx2"
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source "drivers/serial/Kconfig.stellaris"
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source "drivers/serial/Kconfig.native_posix"
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11
drivers/serial/Kconfig.it8xxx2
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11
drivers/serial/Kconfig.it8xxx2
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@ -0,0 +1,11 @@
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# Copyright (c) 2021 ITE Corporation. All Rights Reserved.
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# SPDX-License-Identifier: Apache-2.0
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config UART_ITE_IT8XXX2
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bool "ITE IT8XXX2 UART driver"
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help
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IT8XXX2 uses shared ns16550.c driver which does not
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provide a power management callback, so create driver
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to handle IT8XXX2 specific UART features. In addition
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to use pm_action_cb, we also need to make some setting
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at uart_it8xxx2_init.
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139
drivers/serial/uart_ite_it8xxx2.c
Normal file
139
drivers/serial/uart_ite_it8xxx2.c
Normal file
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@ -0,0 +1,139 @@
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/*
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* Copyright (c) 2021 ITE Corporation. All Rights Reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ite_it8xxx2_uart
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#include <device.h>
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#include <drivers/gpio.h>
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#include <drivers/uart.h>
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#include <kernel.h>
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#include <pm/device.h>
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#include <soc.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(uart_ite_it8xxx2, LOG_LEVEL_ERR);
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struct uart_it8xxx2_config {
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uint8_t port;
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/* GPIO cells */
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struct gpio_dt_spec gpio_wui;
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};
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enum uart_port_num {
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UART1 = 1,
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UART2,
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};
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#ifdef CONFIG_PM_DEVICE
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__weak void uart1_wui_isr_late(void) { }
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__weak void uart2_wui_isr_late(void) { }
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void uart1_wui_isr(const struct device *gpio, struct gpio_callback *cb,
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uint32_t pins)
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{
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/* Disable interrupts on UART1 RX pin to avoid repeated interrupts. */
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(void)gpio_pin_interrupt_configure(gpio, (find_msb_set(pins) - 1),
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GPIO_INT_DISABLE);
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if (uart1_wui_isr_late) {
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uart1_wui_isr_late();
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}
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}
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void uart2_wui_isr(const struct device *gpio, struct gpio_callback *cb,
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uint32_t pins)
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{
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/* Disable interrupts on UART2 RX pin to avoid repeated interrupts. */
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(void)gpio_pin_interrupt_configure(gpio, (find_msb_set(pins) - 1),
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GPIO_INT_DISABLE);
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if (uart2_wui_isr_late) {
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uart2_wui_isr_late();
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}
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}
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static inline int uart_it8xxx2_pm_action(const struct device *dev,
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enum pm_device_action action)
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{
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const struct uart_it8xxx2_config *const config = dev->config;
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int ret = 0;
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switch (action) {
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/* Next device power state is in active. */
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case PM_DEVICE_ACTION_RESUME:
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/* Nothing to do. */
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break;
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/* Next device power state is deep doze mode */
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case PM_DEVICE_ACTION_SUSPEND:
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/* Enable UART WUI */
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ret = gpio_pin_interrupt_configure_dt(&config->gpio_wui,
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GPIO_INT_TRIG_LOW);
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if (ret < 0) {
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LOG_ERR("Failed to configure UART%d WUI (ret %d)",
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config->port, ret);
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return ret;
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}
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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#endif /* CONFIG_PM_DEVICE */
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static int uart_it8xxx2_init(const struct device *dev)
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{
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#ifdef CONFIG_PM_DEVICE
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const struct uart_it8xxx2_config *const config = dev->config;
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int ret = 0;
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/*
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* When the system enters deep doze, all clocks are gated only the
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* 32.768k clock is active. We need to wakeup EC by configuring
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* UART Rx interrupt as a wakeup source. When the interrupt of UART
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* Rx falling, EC will be woken.
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*/
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if (config->port == UART1) {
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static struct gpio_callback uart1_wui_cb;
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gpio_init_callback(&uart1_wui_cb, uart1_wui_isr,
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BIT(config->gpio_wui.pin));
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ret = gpio_add_callback(config->gpio_wui.port, &uart1_wui_cb);
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} else if (config->port == UART2) {
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static struct gpio_callback uart2_wui_cb;
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gpio_init_callback(&uart2_wui_cb, uart2_wui_isr,
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BIT(config->gpio_wui.pin));
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ret = gpio_add_callback(config->gpio_wui.port, &uart2_wui_cb);
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}
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if (ret < 0) {
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LOG_ERR("Failed to add UART%d callback (err %d)",
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config->port, ret);
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return ret;
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}
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#endif /* CONFIG_PM_DEVICE */
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return 0;
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}
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#define UART_ITE_IT8XXX2_INIT(inst) \
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static const struct uart_it8xxx2_config uart_it8xxx2_cfg_##inst = { \
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.port = DT_INST_PROP(inst, port_num), \
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.gpio_wui = GPIO_DT_SPEC_INST_GET(inst, gpios), \
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}; \
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DEVICE_DT_INST_DEFINE(inst, &uart_it8xxx2_init, \
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uart_it8xxx2_pm_action, \
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NULL, &uart_it8xxx2_cfg_##inst, \
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PRE_KERNEL_1, \
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CONFIG_SERIAL_INIT_PRIORITY, \
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NULL);
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DT_INST_FOREACH_STATUS_OKAY(UART_ITE_IT8XXX2_INIT)
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21
dts/bindings/serial/ite,it8xxx2-uart.yaml
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21
dts/bindings/serial/ite,it8xxx2-uart.yaml
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@ -0,0 +1,21 @@
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# Copyright (c) 2021 ITE Corporation. All Rights Reserved.
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# SPDX-License-Identifier: Apache-2.0
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description: ITE, IT8XXX2-UART node
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compatible: "ite,it8xxx2-uart"
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include: uart-controller.yaml
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properties:
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reg:
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required: true
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port-num:
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type: int
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required: true
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description: Ordinal identifying the port
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gpios:
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type: phandle-array
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required: true
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@ -276,6 +276,24 @@
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interrupt-parent = <&intc>;
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};
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ite_uart1_wrapper: uartwrapper@f02720 {
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compatible = "ite,it8xxx2-uart";
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reg = <0x00f02720 0x0020>;
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status = "disabled";
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label = "UART1_WRAPPER";
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port-num = <1>;
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gpios = <&gpiob 0 0>;
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};
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ite_uart2_wrapper: uartwrapper@f02820 {
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compatible = "ite,it8xxx2-uart";
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reg = <0x00f02820 0x0020>;
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status = "disabled";
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label = "UART2_WRAPPER";
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port-num = <2>;
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gpios = <&gpioh 1 0>;
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};
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twd0: watchdog@f01f00 {
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compatible = "ite,it8xxx2-watchdog";
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reg = <0x00f01f00 0x0062>;
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IT8XXX2_IRQ_WU105 IRQ_TYPE_LEVEL_HIGH
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IT8XXX2_IRQ_WU106 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&intc>;
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wakeup-source; /* WUI53 */
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#gpio-cells = <2>;
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};
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IT8XXX2_IRQ_WU90 IRQ_TYPE_LEVEL_HIGH
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0 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&intc>;
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wakeup-source; /* WUI17 */
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#gpio-cells = <2>;
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};
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@ -4,81 +4,14 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/gpio.h>
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#include <drivers/uart.h>
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#include <kernel.h>
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#include <pm/pm.h>
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#include <soc.h>
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#include <zephyr.h>
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#include <logging/log.h>
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LOG_MODULE_DECLARE(power, CONFIG_PM_LOG_LEVEL);
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__weak void uart1_wui_isr_late(void) { }
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__weak void uart2_wui_isr_late(void) { }
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
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static const struct device *uart1_dev;
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void uart1_wui_isr(const struct device *gpio, struct gpio_callback *cb,
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uint32_t pins)
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{
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/* Disable interrupts on UART1 RX pin to avoid repeated interrupts. */
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gpio_pin_interrupt_configure(gpio, (find_msb_set(pins) - 1),
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GPIO_INT_DISABLE);
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if (uart1_wui_isr_late) {
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uart1_wui_isr_late();
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}
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}
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
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static const struct device *uart2_dev;
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void uart2_wui_isr(const struct device *gpio, struct gpio_callback *cb,
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uint32_t pins)
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{
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/* Disable interrupts on UART2 RX pin to avoid repeated interrupts. */
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gpio_pin_interrupt_configure(gpio, (find_msb_set(pins) - 1),
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GPIO_INT_DISABLE);
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if (uart2_wui_isr_late) {
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uart2_wui_isr_late();
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}
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}
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) */
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/* Handle when enter deep doze mode. */
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static void ite_power_soc_deep_doze(void)
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{
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int ret;
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
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/* Enable UART1 WUI */
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ret = gpio_pin_interrupt_configure(DEVICE_DT_GET(DT_NODELABEL(gpiob)),
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0, GPIO_INT_TRIG_LOW);
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if (ret) {
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LOG_ERR("Failed to configure UART1 WUI (ret %d)", ret);
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return;
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}
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/* If nothing remains to be transmitted. */
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while (!uart_irq_tx_complete(uart1_dev))
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;
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
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/* Enable UART2 WUI */
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ret = gpio_pin_interrupt_configure(DEVICE_DT_GET(DT_NODELABEL(gpioh)),
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1, GPIO_INT_TRIG_LOW);
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if (ret) {
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LOG_ERR("Failed to configure UART2 WUI (ret %d)", ret);
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return;
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}
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/* If nothing remains to be transmitted. */
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while (!uart_irq_tx_complete(uart2_dev))
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;
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) */
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/* Enter deep doze mode */
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riscv_idle(CHIP_PLL_DEEP_DOZE, MSTATUS_IEN);
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}
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{
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ARG_UNUSED(info);
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}
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static int power_it8xxx2_init(const struct device *arg)
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{
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ARG_UNUSED(arg);
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int ret;
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
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static struct gpio_callback uart1_wui_cb;
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uart1_dev = device_get_binding(DT_LABEL(DT_NODELABEL(uart1)));
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if (!uart1_dev) {
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LOG_ERR("Fail to find %s", DT_LABEL(DT_NODELABEL(uart1)));
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return -ENODEV;
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}
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gpio_init_callback(&uart1_wui_cb, uart1_wui_isr, BIT(0));
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ret = gpio_add_callback(DEVICE_DT_GET(DT_NODELABEL(gpiob)),
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&uart1_wui_cb);
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if (ret) {
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LOG_ERR("Failed to add callback (err %d)", ret);
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return ret;
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}
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
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static struct gpio_callback uart2_wui_cb;
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uart2_dev = device_get_binding(DT_LABEL(DT_NODELABEL(uart2)));
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if (!uart2_dev) {
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LOG_ERR("Fail to find %s", DT_LABEL(DT_NODELABEL(uart2)));
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return -ENODEV;
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}
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gpio_init_callback(&uart2_wui_cb, uart2_wui_isr, BIT(1));
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ret = gpio_add_callback(DEVICE_DT_GET(DT_NODELABEL(gpioh)),
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&uart2_wui_cb);
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if (ret) {
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LOG_ERR("Failed to add callback (err %d)", ret);
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return ret;
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}
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) */
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return 0;
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}
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SYS_INIT(power_it8xxx2_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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@ -33,6 +33,10 @@ config UART_NS16550_WA_ISR_REENABLE_INTERRUPT
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default y
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depends on UART_NS16550
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config UART_ITE_IT8XXX2
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default y
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depends on UART_NS16550
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config RISCV_HAS_CPU_IDLE
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default y
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