arch: arm: cortex_m: align vector table based on VTOR requirements
Enforce VTOR table offset alignment requirements on Cortex-M vector table start address. Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
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2 changed files with 50 additions and 2 deletions
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/*
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* Copyright (c) 2019 Nordic Semiconductor ASA
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* Copyright (c) 2019 - 2020 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#if defined(CONFIG_CPU_CORTEX_M_HAS_VTOR)
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/*
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* In an MCU with VTOR, the VTOR.TBLOFF is set to the start address of the
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* vector_relay_table, when building with support for interrupt relaying.
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* Therefore, vector_relay_table must respect the alignment requirements
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* of VTOR.TBLOFF described below.
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*/
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/* VTOR bits 0:6 are reserved (RES0). This requires that the base address
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* of the vector table is 32-word aligned.
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*/
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. = ALIGN( 1 << LOG2CEIL(4 * 32) );
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/* When setting TBLOFF in VTOR we must align the offset to the number of
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* exception entries in the vector table. The minimum alignment of 32 words
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* is sufficient for the 16 ARM Core exceptions and up to 16 HW interrupts.
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* For more than 16 HW interrupts, we adjust the alignment by rounding up
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* to the next power of two; this restriction guarantees a functional VTOR
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* setting in any Cortex-M implementation (might not be required in every
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* Cortex-M processor).
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*/
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. = ALIGN( 1 << LOG2CEIL(4 * (16 + CONFIG_NUM_IRQS)) );
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#endif
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KEEP(*(.vector_relay_table))
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KEEP(*(".vector_relay_table.*"))
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KEEP(*(.vector_relay_handler))
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@ -1,9 +1,33 @@
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/*
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* Copyright (c) 2019 Nordic Semiconductor ASA
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* Copyright (c) 2019 - 2020 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#if defined(CONFIG_CPU_CORTEX_M_HAS_VTOR)
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/*
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* In an MCU with VTOR, the VTOR.TBLOFF is set to the start address of the
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* exc_vector_table (i.e. _vector_start) during initialization. Therefore,
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* exc_vector_table must respect the alignment requirements of VTOR.TBLOFF
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* described below.
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*/
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/* VTOR bits 0:6 are reserved (RES0). This requires that the base address
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* of the vector table is 32-word aligned.
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*/
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. = ALIGN( 1 << LOG2CEIL(4 * 32) );
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/* When setting TBLOFF in VTOR we must align the offset to the number of
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* exception entries in the vector table. The minimum alignment of 32 words
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* is sufficient for the 16 ARM Core exceptions and up to 16 HW interrupts.
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* For more than 16 HW interrupts, we adjust the alignment by rounding up
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* to the next power of two; this restriction guarantees a functional VTOR
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* setting in any Cortex-M implementation (might not be required in every
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* Cortex-M processor).
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*/
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. = ALIGN( 1 << LOG2CEIL(4 * (16 + CONFIG_NUM_IRQS)) );
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#endif
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_vector_start = .;
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KEEP(*(.exc_vector_table))
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KEEP(*(".exc_vector_table.*"))
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