soc: riscv: andes_v5: initial support of Andes L2 cache controller
This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
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3 changed files with 89 additions and 0 deletions
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@ -8,6 +8,7 @@ zephyr_sources(
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)
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zephyr_sources_ifdef(CONFIG_SOC_ANDES_V5_PMA pma.c)
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zephyr_sources_ifdef(CONFIG_SOC_ANDES_V5_L2_CACHE l2_cache.c)
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# Note: AndeStar V5 DSP needs custom Andes V5 toolchain
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if(CONFIG_SOC_ANDES_V5_HWDSP)
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@ -47,6 +47,11 @@ config CACHE_ENABLE
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bool "Enable cache"
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default n
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config SOC_ANDES_V5_L2_CACHE
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bool "Enable Andes V5 L2 cache controller"
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depends on CACHE_ENABLE
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default y
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config SOC_ANDES_V5_HWDSP
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bool "Enable AndeStar V5 DSP ISA"
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select RISCV_SOC_CONTEXT_SAVE
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83
soc/riscv/riscv-privilege/andes_v5/l2_cache.c
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83
soc/riscv/riscv-privilege/andes_v5/l2_cache.c
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@ -0,0 +1,83 @@
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/*
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* Copyright (c) 2021 Andes Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT andestech_l2c
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/**
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* @brief Andes V5 L2 Cache Controller driver
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*/
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#include <init.h>
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <soc.h>
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/*
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* L2C Register Base Address
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*/
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#define AMDES_V5_L2C_BASE DT_INST_REG_ADDR(0)
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/*
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* L2C Register Offset
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*/
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#define L2C_CTRL 0x08
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/*
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* L2C Helper Constant
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*/
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/* enable L2C */
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#define L2C_CTRL_CEN BIT(0)
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/* instruction prefetch depth */
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#define IPFDPT_FIELD(x) (x << 3)
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#define L2C_CTRL_IPFDPT_0 IPFDPT_FIELD(0)
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#define L2C_CTRL_IPFDPT_1 IPFDPT_FIELD(1)
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#define L2C_CTRL_IPFDPT_2 IPFDPT_FIELD(2)
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#define L2C_CTRL_IPFDPT_3 IPFDPT_FIELD(3)
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/* data prefetch depth */
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#define DPFDPT_FIELD(x) (x << 5)
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#define L2C_CTRL_DPFDPT_0 DPFDPT_FIELD(0)
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#define L2C_CTRL_DPFDPT_2 DPFDPT_FIELD(1)
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#define L2C_CTRL_DPFDPT_4 DPFDPT_FIELD(2)
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#define L2C_CTRL_DPFDPT_8 DPFDPT_FIELD(3)
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static void andes_v5_l2c_enable(void)
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{
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volatile uint64_t *l2c_ctrl =
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INT_TO_POINTER(AMDES_V5_L2C_BASE + L2C_CTRL);
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/* Use largest instr/data prefetch depth by default */
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uint64_t l2c_config = L2C_CTRL_IPFDPT_3 | L2C_CTRL_DPFDPT_8;
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/* Configure L2 cache */
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*l2c_ctrl = l2c_config;
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/* Enable L2 cache */
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*l2c_ctrl = (l2c_config | L2C_CTRL_CEN);
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}
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static int andes_v5_l2c_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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#ifdef SMU_BASE
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volatile uint32_t *system_cfg = INT_TO_POINTER(SMU_BASE + SMU_SYSTEMCFG);
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if (!(*system_cfg & SMU_SYSTEMCFG_L2C)) {
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/* This SoC doesn't have L2 cache */
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return -1;
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}
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#endif /* SMU_BASE */
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andes_v5_l2c_enable();
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return 0;
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}
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SYS_INIT(andes_v5_l2c_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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