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drivers: gpio: cmsdk_ahb: Convert driver to be full DTS based

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Convert driver to utilize the new DT_INST macros completely and remove
associated Kconfig symbols that now come from devicetree.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-02-14 14:36:31 -06:00 • committed by Kumar Gala
commit 1951c79db4
12 changed files with 41 additions and 340 deletions
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12
boards/arm/mps2_an385/Kconfig.defconfig
View file

@ -11,18 +11,6 @@ if GPIO
config GPIO_CMSDK_AHB
default y
config GPIO_CMSDK_AHB_PORT0
default y
config GPIO_CMSDK_AHB_PORT1
default y
config GPIO_CMSDK_AHB_PORT2
default y
config GPIO_CMSDK_AHB_PORT3
default y
endif # GPIO
if SERIAL

13
boards/arm/mps2_an385/dts_fixup.h
View file

@ -4,19 +4,6 @@
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
/* CMSDK AHB General Purpose Input/Output (GPIO) */
#define DT_CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_40010000_BASE_ADDRESS
#define DT_IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_40010000_IRQ_0
#define DT_CMSDK_AHB_GPIO1 DT_ARM_CMSDK_GPIO_40011000_BASE_ADDRESS
#define DT_IRQ_PORT1_ALL DT_ARM_CMSDK_GPIO_40011000_IRQ_0
#define DT_CMSDK_AHB_GPIO2 DT_ARM_CMSDK_GPIO_40012000_BASE_ADDRESS
#define DT_IRQ_PORT2_ALL DT_ARM_CMSDK_GPIO_40012000_IRQ_0
#define DT_CMSDK_AHB_GPIO3 DT_ARM_CMSDK_GPIO_40013000_BASE_ADDRESS
#define DT_IRQ_PORT3_ALL DT_ARM_CMSDK_GPIO_40013000_IRQ_0
#define DT_FPGAIO_LED0_GPIO_NAME DT_ARM_MPS2_FPGAIO_GPIO_40028000_LABEL
#define DT_FPGAIO_LED0_NUM DT_ARM_MPS2_FPGAIO_GPIO_40028000_NGPIOS
#define DT_FPGAIO_LED0 DT_ARM_MPS2_FPGAIO_GPIO_40028000_BASE_ADDRESS

12
boards/arm/mps2_an521/Kconfig.defconfig
View file

@ -12,18 +12,6 @@ if GPIO
config GPIO_CMSDK_AHB
default y
config GPIO_CMSDK_AHB_PORT0
default y
config GPIO_CMSDK_AHB_PORT1
default y
config GPIO_CMSDK_AHB_PORT2
default y
config GPIO_CMSDK_AHB_PORT3
default y
endif # GPIO
if SERIAL

12
boards/arm/v2m_beetle/Kconfig.defconfig
View file

@ -13,18 +13,6 @@ if GPIO
config GPIO_CMSDK_AHB
default y
config GPIO_CMSDK_AHB_PORT0
default y
config GPIO_CMSDK_AHB_PORT1
default y
config GPIO_CMSDK_AHB_PORT2
default y
config GPIO_CMSDK_AHB_PORT3
default y
endif # GPIO
config PINMUX_BEETLE

3
boards/arm/v2m_musca/Kconfig.defconfig
View file

@ -12,9 +12,6 @@ if GPIO
config GPIO_CMSDK_AHB
default y
config GPIO_CMSDK_AHB_PORT0
default y
endif
if SERIAL

3
boards/arm/v2m_musca_b1/Kconfig.defconfig
View file

@ -12,9 +12,6 @@ if GPIO
config GPIO_CMSDK_AHB
default y
config GPIO_CMSDK_AHB_PORT0
default y
endif
if SERIAL

92
drivers/gpio/Kconfig.cmsdk_ahb
View file

@ -3,98 +3,10 @@
# Copyright (c) 2016 Linaro Limited
# SPDX-License-Identifier: Apache-2.0
menuconfig GPIO_CMSDK_AHB
config GPIO_CMSDK_AHB
bool "ARM CMSDK (Cortex-M System Design Kit) AHB GPIO Controllers"
depends on SOC_SERIES_BEETLE
depends on SOC_FAMILY_ARM
help
Enable config options to support the ARM CMSDK GPIO controllers.
Says n if not sure.
if GPIO_CMSDK_AHB
# ---------- Port 0 ----------
config GPIO_CMSDK_AHB_PORT0
bool "Enable driver for GPIO Port 0"
help
Build the driver to utilize GPIO controller Port 0.
config GPIO_CMSDK_AHB_PORT0_DEV_NAME
string "Device name for Port 0"
depends on GPIO_CMSDK_AHB_PORT0
default "GPIO_0"
help
Device name for Port 0.
config GPIO_CMSDK_AHB_PORT0_IRQ_PRI
int "Interrupt Priority for Port 0"
depends on GPIO_CMSDK_AHB_PORT0
default 3
help
Interrupt priority for Port 0.
# ---------- Port 1 ----------
config GPIO_CMSDK_AHB_PORT1
bool "Enable driver for GPIO Port 1"
help
Build the driver to utilize GPIO controller Port 1.
config GPIO_CMSDK_AHB_PORT1_DEV_NAME
string "Device name for Port 1"
depends on GPIO_CMSDK_AHB_PORT1
default "GPIO_1"
help
Device name for Port 1.
config GPIO_CMSDK_AHB_PORT1_IRQ_PRI
int "Interrupt Priority for Port 1"
depends on GPIO_CMSDK_AHB_PORT1
default 3
help
Interrupt priority for Port 1.
# ---------- Port 2 ----------
config GPIO_CMSDK_AHB_PORT2
bool "Enable driver for GPIO Port 2"
help
Build the driver to utilize GPIO controller Port 2.
config GPIO_CMSDK_AHB_PORT2_DEV_NAME
string "Device name for Port 2"
depends on GPIO_CMSDK_AHB_PORT2
default "GPIO_2"
help
Device name for Port 2.
config GPIO_CMSDK_AHB_PORT2_IRQ_PRI
int "Interrupt Priority for Port 2"
depends on GPIO_CMSDK_AHB_PORT2
default 3
help
Interrupt priority for Port 2.
# ---------- Port 3 ----------
config GPIO_CMSDK_AHB_PORT3
bool "Enable driver for GPIO Port 3"
help
Build the driver to utilize GPIO controller Port 3.
config GPIO_CMSDK_AHB_PORT3_DEV_NAME
string "Device name for Port 3"
depends on GPIO_CMSDK_AHB_PORT3
default "GPIO_3"
help
Device name for Port 3.
config GPIO_CMSDK_AHB_PORT3_IRQ_PRI
int "Interrupt Priority for Port 3"
depends on GPIO_CMSDK_AHB_PORT3
default 3
help
Interrupt priority for Port 3.
endif # GPIO_CMSDK_AHB

180
drivers/gpio/gpio_cmsdk_ahb.c
View file

@ -269,146 +269,44 @@ static int gpio_cmsdk_ahb_init(struct device *dev)
return 0;
}
/* Port 0 */
#ifdef CONFIG_GPIO_CMSDK_AHB_PORT0
static void gpio_cmsdk_ahb_config_0(struct device *dev);
#define PORT_PIN_MASK(n) \
GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_PROP(n, ngpios))
static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_0_cfg = {
.common = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_PROP(0, ngpios)),
},
.port = ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO0),
.gpio_config_func = gpio_cmsdk_ahb_config_0,
.gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE,
.device = DT_CMSDK_AHB_GPIO0,},
.gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP,
.device = DT_CMSDK_AHB_GPIO0,},
.gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP,
.device = DT_CMSDK_AHB_GPIO0,},
};
#define CMSDK_AHB_GPIO_DEVICE(n) \
static void gpio_cmsdk_port_##n##_config_func(struct device *dev); \
\
static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_port_##n##_config = { \
.common = { \
.port_pin_mask = PORT_PIN_MASK(n), \
}, \
.port = ((volatile struct gpio_cmsdk_ahb *)DT_INST_REG_ADDR(n)),\
.gpio_config_func = gpio_cmsdk_port_##n##_config_func, \
.gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE, \
.device = DT_INST_REG_ADDR(n),}, \
.gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP, \
.device = DT_INST_REG_ADDR(n),}, \
.gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP, \
.device = DT_INST_REG_ADDR(n),}, \
}; \
\
static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_port_##n##_data; \
\
DEVICE_AND_API_INIT(gpio_cmsdk_port_## n, \
DT_INST_LABEL(n), \
gpio_cmsdk_ahb_init, \
&gpio_cmsdk_port_##n##_data, \
&gpio_cmsdk_port_## n ##_config, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
&gpio_cmsdk_ahb_drv_api_funcs); \
\
static void gpio_cmsdk_port_##n##_config_func(struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), \
gpio_cmsdk_ahb_isr, \
DEVICE_GET(gpio_cmsdk_port_## n), 0); \
\
irq_enable(DT_INST_IRQN(n)); \
}
static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_0_data;
DEVICE_AND_API_INIT(gpio_cmsdk_ahb_0,
CONFIG_GPIO_CMSDK_AHB_PORT0_DEV_NAME,
gpio_cmsdk_ahb_init, &gpio_cmsdk_ahb_0_data,
&gpio_cmsdk_ahb_0_cfg, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&gpio_cmsdk_ahb_drv_api_funcs);
static void gpio_cmsdk_ahb_config_0(struct device *dev)
{
IRQ_CONNECT(DT_IRQ_PORT0_ALL, CONFIG_GPIO_CMSDK_AHB_PORT0_IRQ_PRI,
gpio_cmsdk_ahb_isr,
DEVICE_GET(gpio_cmsdk_ahb_0), 0);
irq_enable(DT_IRQ_PORT0_ALL);
}
#endif /* CONFIG_GPIO_CMSDK_AHB_PORT0 */
/* Port 1 */
#ifdef CONFIG_GPIO_CMSDK_AHB_PORT1
static void gpio_cmsdk_ahb_config_1(struct device *dev);
static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_1_cfg = {
.common = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_PROP(1, ngpios)),
},
.port = ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO1),
.gpio_config_func = gpio_cmsdk_ahb_config_1,
.gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE,
.device = DT_CMSDK_AHB_GPIO1,},
.gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP,
.device = DT_CMSDK_AHB_GPIO1,},
.gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP,
.device = DT_CMSDK_AHB_GPIO1,},
};
static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_1_data;
DEVICE_AND_API_INIT(gpio_cmsdk_ahb_1,
CONFIG_GPIO_CMSDK_AHB_PORT1_DEV_NAME,
gpio_cmsdk_ahb_init, &gpio_cmsdk_ahb_1_data,
&gpio_cmsdk_ahb_1_cfg, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&gpio_cmsdk_ahb_drv_api_funcs);
static void gpio_cmsdk_ahb_config_1(struct device *dev)
{
IRQ_CONNECT(DT_IRQ_PORT1_ALL, CONFIG_GPIO_CMSDK_AHB_PORT1_IRQ_PRI,
gpio_cmsdk_ahb_isr,
DEVICE_GET(gpio_cmsdk_ahb_1), 0);
irq_enable(DT_IRQ_PORT1_ALL);
}
#endif /* CONFIG_GPIO_CMSDK_AHB_PORT1 */
/* Port 2 */
#ifdef CONFIG_GPIO_CMSDK_AHB_PORT2
static void gpio_cmsdk_ahb_config_2(struct device *dev);
static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_2_cfg = {
.common = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_PROP(2, ngpios)),
},
.port = ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO2),
.gpio_config_func = gpio_cmsdk_ahb_config_2,
.gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE,
.device = DT_CMSDK_AHB_GPIO2,},
.gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP,
.device = DT_CMSDK_AHB_GPIO2,},
.gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP,
.device = DT_CMSDK_AHB_GPIO2,},
};
static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_2_data;
DEVICE_AND_API_INIT(gpio_cmsdk_ahb_2,
CONFIG_GPIO_CMSDK_AHB_PORT2_DEV_NAME,
gpio_cmsdk_ahb_init, &gpio_cmsdk_ahb_2_data,
&gpio_cmsdk_ahb_2_cfg, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&gpio_cmsdk_ahb_drv_api_funcs);
static void gpio_cmsdk_ahb_config_2(struct device *dev)
{
IRQ_CONNECT(DT_IRQ_PORT2_ALL, CONFIG_GPIO_CMSDK_AHB_PORT2_IRQ_PRI,
gpio_cmsdk_ahb_isr,
DEVICE_GET(gpio_cmsdk_ahb_2), 0);
irq_enable(DT_IRQ_PORT2_ALL);
}
#endif /* CONFIG_GPIO_CMSDK_AHB_PORT2 */
/* Port 3 */
#ifdef CONFIG_GPIO_CMSDK_AHB_PORT3
static void gpio_cmsdk_ahb_config_3(struct device *dev);
static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_3_cfg = {
.common = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_PROP(3, ngpios)),
},
.port = ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO3),
.gpio_config_func = gpio_cmsdk_ahb_config_3,
.gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE,
.device = DT_CMSDK_AHB_GPIO3,},
.gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP,
.device = DT_CMSDK_AHB_GPIO3,},
.gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP,
.device = DT_CMSDK_AHB_GPIO3,},
};
static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_3_data;
DEVICE_AND_API_INIT(gpio_cmsdk_ahb_3,
CONFIG_GPIO_CMSDK_AHB_PORT3_DEV_NAME,
gpio_cmsdk_ahb_init, &gpio_cmsdk_ahb_3_data,
&gpio_cmsdk_ahb_3_cfg, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&gpio_cmsdk_ahb_drv_api_funcs);
static void gpio_cmsdk_ahb_config_3(struct device *dev)
{
IRQ_CONNECT(DT_IRQ_PORT3_ALL, CONFIG_GPIO_CMSDK_AHB_PORT3_IRQ_PRI,
gpio_cmsdk_ahb_isr,
DEVICE_GET(gpio_cmsdk_ahb_3), 0);
irq_enable(DT_IRQ_PORT3_ALL);
}
#endif /* CONFIG_GPIO_CMSDK_AHB_PORT3 */
DT_INST_FOREACH(CMSDK_AHB_GPIO_DEVICE)

13
soc/arm/arm/beetle/dts_fixup.h
View file

@ -4,17 +4,4 @@
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
/* CMSDK AHB General Purpose Input/Output (GPIO) */
#define DT_CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_40010000_BASE_ADDRESS
#define DT_IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_40010000_IRQ_0
#define DT_CMSDK_AHB_GPIO1 DT_ARM_CMSDK_GPIO_40011000_BASE_ADDRESS
#define DT_IRQ_PORT1_ALL DT_ARM_CMSDK_GPIO_40011000_IRQ_0
#define DT_CMSDK_AHB_GPIO2 DT_ARM_CMSDK_GPIO_40012000_BASE_ADDRESS
#define DT_IRQ_PORT2_ALL DT_ARM_CMSDK_GPIO_40012000_IRQ_0
#define DT_CMSDK_AHB_GPIO3 DT_ARM_CMSDK_GPIO_40013000_BASE_ADDRESS
#define DT_IRQ_PORT3_ALL DT_ARM_CMSDK_GPIO_40013000_IRQ_0
/* End of SoC Level DTS fixup file */

26
soc/arm/arm/mps2/dts_fixup.h
View file

@ -23,19 +23,6 @@
#define DT_CMSDK_APB_DTIMER DT_ARM_CMSDK_DTIMER_40002000_BASE_ADDRESS
#define DT_CMSDK_APB_DUALTIMER_IRQ DT_ARM_CMSDK_DTIMER_40002000_IRQ_0
/* CMSDK AHB General Purpose Input/Output (GPIO) */
#define DT_CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_40100000_BASE_ADDRESS
#define DT_IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_40100000_IRQ_0
#define DT_CMSDK_AHB_GPIO1 DT_ARM_CMSDK_GPIO_40101000_BASE_ADDRESS
#define DT_IRQ_PORT1_ALL DT_ARM_CMSDK_GPIO_40101000_IRQ_0
#define DT_CMSDK_AHB_GPIO2 DT_ARM_CMSDK_GPIO_40102000_BASE_ADDRESS
#define DT_IRQ_PORT2_ALL DT_ARM_CMSDK_GPIO_40102000_IRQ_0
#define DT_CMSDK_AHB_GPIO3 DT_ARM_CMSDK_GPIO_40103000_BASE_ADDRESS
#define DT_IRQ_PORT3_ALL DT_ARM_CMSDK_GPIO_40103000_IRQ_0
#define DT_FPGAIO_LED0_GPIO_NAME DT_ARM_MPS2_FPGAIO_GPIO_40302000_LABEL
#define DT_FPGAIO_LED0_NUM DT_ARM_MPS2_FPGAIO_GPIO_40302000_NGPIOS
#define DT_FPGAIO_LED0 DT_ARM_MPS2_FPGAIO_GPIO_40302000_BASE_ADDRESS
@ -61,19 +48,6 @@
#define DT_CMSDK_APB_DTIMER DT_ARM_CMSDK_DTIMER_50002000_BASE_ADDRESS
#define DT_CMSDK_APB_DUALTIMER_IRQ DT_ARM_CMSDK_DTIMER_50002000_IRQ_0
/* CMSDK AHB General Purpose Input/Output (GPIO) */
#define DT_CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_50100000_BASE_ADDRESS
#define DT_IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_50100000_IRQ_0
#define DT_CMSDK_AHB_GPIO1 DT_ARM_CMSDK_GPIO_50101000_BASE_ADDRESS
#define DT_IRQ_PORT1_ALL DT_ARM_CMSDK_GPIO_50101000_IRQ_0
#define DT_CMSDK_AHB_GPIO2 DT_ARM_CMSDK_GPIO_50102000_BASE_ADDRESS
#define DT_IRQ_PORT2_ALL DT_ARM_CMSDK_GPIO_50102000_IRQ_0
#define DT_CMSDK_AHB_GPIO3 DT_ARM_CMSDK_GPIO_50103000_BASE_ADDRESS
#define DT_IRQ_PORT3_ALL DT_ARM_CMSDK_GPIO_50103000_IRQ_0
#define DT_FPGAIO_LED0_GPIO_NAME DT_ARM_MPS2_FPGAIO_GPIO_50302000_LABEL
#define DT_FPGAIO_LED0_NUM DT_ARM_MPS2_FPGAIO_GPIO_50302000_NGPIOS
#define DT_FPGAIO_LED0 DT_ARM_MPS2_FPGAIO_GPIO_50302000_BASE_ADDRESS

8
soc/arm/arm/musca_a/dts_fixup.h
View file

@ -15,19 +15,11 @@
/* SCC */
#define DT_ARM_SCC_BASE_ADDRESS DT_ARM_SCC_4010C000_BASE_ADDRESS
/* CMSDK AHB General Purpose Input/Output (GPIO) */
#define DT_CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_40110000_BASE_ADDRESS
#define DT_IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_40110000_IRQ_0
#else
/* SCC */
#define DT_ARM_SCC_BASE_ADDRESS DT_ARM_SCC_5010C000_BASE_ADDRESS
/* CMSDK AHB General Purpose Input/Output (GPIO) */
#define DT_CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_50110000_BASE_ADDRESS
#define DT_IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_50110000_IRQ_0
#endif
/* End of SoC Level DTS fixup file */

7
soc/arm/arm/musca_b1/dts_fixup.h
View file

@ -15,18 +15,11 @@
/* SCC */
#define DT_ARM_SCC_BASE_ADDRESS DT_ARM_SCC_4010B000_BASE_ADDRESS
/* CMSDK AHB General Purpose Input/Output (GPIO) */
#define DT_CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_41000000_BASE_ADDRESS
#define DT_IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_41000000_IRQ_0
#else
/* SCC */
#define DT_ARM_SCC_BASE_ADDRESS DT_ARM_SCC_5010B000_BASE_ADDRESS
/* CMSDK AHB General Purpose Input/Output (GPIO) */
#define DT_CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_51000000_BASE_ADDRESS
#define DT_IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_51000000_IRQ_0
#endif
/* End of SoC Level DTS fixup file */