drivers: serial: uart_psoc6: Convert to new dt macros
Convert the driver to use the new dt macros. As part of this change we remove a bunch of defines that happened in dts_fixup.h that didn't belong there. Some of these should be converted to devicetree properties at some point. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala
Kumar Gala
parent
be84c4ebbf
commit
7b2fde91d8
2 changed files with 42 additions and 68 deletions
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@ -22,6 +22,22 @@
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#include "cy_gpio.h"
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#include "cy_scb_uart.h"
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/* UART desired baud rate is 115200 bps (Standard mode).
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* The UART baud rate = (SCB clock frequency / Oversample).
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* For PeriClk = 50 MHz, select divider value 36 and get
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* SCB clock = (50 MHz / 36) = 1,389 MHz.
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* Select Oversample = 12.
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* These setting results UART data rate = 1,389 MHz / 12 = 115750 bps.
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*/
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#define UART_PSOC6_CONFIG_OVERSAMPLE (12UL)
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#define UART_PSOC6_CONFIG_BREAKWIDTH (11UL)
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#define UART_PSOC6_CONFIG_DATAWIDTH (8UL)
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/* Assign divider type and number for UART */
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#define UART_PSOC6_UART_CLK_DIV_TYPE (CY_SYSCLK_DIV_8_BIT)
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#define UART_PSOC6_UART_CLK_DIV_NUMBER (PERI_DIV_8_NR - 1u)
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#define UART_PSOC6_UART_CLK_DIV_VAL (35UL)
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/*
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* Verify Kconfig configuration
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*/
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@ -44,14 +60,14 @@ static const cy_stc_scb_uart_config_t uartConfig = {
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.irdaInvertRx = false,
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.irdaEnableLowPowerReceiver = false,
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.oversample = DT_UART_PSOC6_CONFIG_OVERSAMPLE,
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.oversample = UART_PSOC6_CONFIG_OVERSAMPLE,
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.enableMsbFirst = false,
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.dataWidth = DT_UART_PSOC6_CONFIG_DATAWIDTH,
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.dataWidth = UART_PSOC6_CONFIG_DATAWIDTH,
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.parity = CY_SCB_UART_PARITY_NONE,
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.stopBits = CY_SCB_UART_STOP_BITS_1,
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.enableInputFilter = false,
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.breakWidth = DT_UART_PSOC6_CONFIG_BREAKWIDTH,
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.breakWidth = UART_PSOC6_CONFIG_BREAKWIDTH,
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.dropOnFrameError = false,
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.dropOnParityError = false,
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@ -91,14 +107,14 @@ static int uart_psoc6_init(struct device *dev)
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/* Connect assigned divider to be a clock source for UART */
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Cy_SysClk_PeriphAssignDivider(config->scb_clock,
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DT_UART_PSOC6_UART_CLK_DIV_TYPE,
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DT_UART_PSOC6_UART_CLK_DIV_NUMBER);
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UART_PSOC6_UART_CLK_DIV_TYPE,
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UART_PSOC6_UART_CLK_DIV_NUMBER);
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Cy_SysClk_PeriphSetDivider(DT_UART_PSOC6_UART_CLK_DIV_TYPE,
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DT_UART_PSOC6_UART_CLK_DIV_NUMBER,
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DT_UART_PSOC6_UART_CLK_DIV_VAL);
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Cy_SysClk_PeriphEnableDivider(DT_UART_PSOC6_UART_CLK_DIV_TYPE,
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DT_UART_PSOC6_UART_CLK_DIV_NUMBER);
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Cy_SysClk_PeriphSetDivider(UART_PSOC6_UART_CLK_DIV_TYPE,
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UART_PSOC6_UART_CLK_DIV_NUMBER,
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UART_PSOC6_UART_CLK_DIV_VAL);
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Cy_SysClk_PeriphEnableDivider(UART_PSOC6_UART_CLK_DIV_TYPE,
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UART_PSOC6_UART_CLK_DIV_NUMBER);
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/* Configure UART to operate */
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(void) Cy_SCB_UART_Init(config->base, &uartConfig, NULL);
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@ -133,16 +149,16 @@ static const struct uart_driver_api uart_psoc6_driver_api = {
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#ifdef CONFIG_UART_PSOC6_UART_5
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static const struct cypress_psoc6_config cypress_psoc6_uart5_config = {
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.base = DT_UART_PSOC6_UART_5_BASE_ADDRESS,
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.port = DT_UART_PSOC6_UART_5_PORT,
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.rx_num = DT_UART_PSOC6_UART_5_RX_NUM,
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.tx_num = DT_UART_PSOC6_UART_5_TX_NUM,
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.rx_val = DT_UART_PSOC6_UART_5_RX_VAL,
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.tx_val = DT_UART_PSOC6_UART_5_TX_VAL,
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.scb_clock = DT_UART_PSOC6_UART_5_CLOCK,
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.base = (CySCB_Type *)DT_REG_ADDR(DT_NODELABEL(uart5)),
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.port = P5_0_PORT,
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.rx_num = P5_0_NUM,
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.tx_num = P5_1_NUM,
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.rx_val = P5_0_SCB5_UART_RX,
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.tx_val = P5_1_SCB5_UART_TX,
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.scb_clock = PCLK_SCB5_CLOCK,
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};
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DEVICE_AND_API_INIT(uart_5, DT_UART_PSOC6_UART_5_NAME,
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DEVICE_AND_API_INIT(uart_5, DT_LABEL(DT_NODELABEL(uart5)),
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uart_psoc6_init, NULL,
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&cypress_psoc6_uart5_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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@ -151,16 +167,16 @@ DEVICE_AND_API_INIT(uart_5, DT_UART_PSOC6_UART_5_NAME,
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#ifdef CONFIG_UART_PSOC6_UART_6
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static const struct cypress_psoc6_config cypress_psoc6_uart6_config = {
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.base = DT_UART_PSOC6_UART_6_BASE_ADDRESS,
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.port = DT_UART_PSOC6_UART_6_PORT,
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.rx_num = DT_UART_PSOC6_UART_6_RX_NUM,
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.tx_num = DT_UART_PSOC6_UART_6_TX_NUM,
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.rx_val = DT_UART_PSOC6_UART_6_RX_VAL,
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.tx_val = DT_UART_PSOC6_UART_6_TX_VAL,
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.scb_clock = DT_UART_PSOC6_UART_6_CLOCK,
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.base = (CySCB_Type *)DT_REG_ADDR(DT_NODELABEL(uart6)),
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.port = P12_0_PORT,
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.rx_num = P12_0_NUM,
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.tx_num = P12_1_NUM,
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.rx_val = P12_0_SCB6_UART_RX,
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.tx_val = P12_1_SCB6_UART_TX,
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.scb_clock = PCLK_SCB6_CLOCK,
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};
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DEVICE_AND_API_INIT(uart_6, DT_UART_PSOC6_UART_6_NAME,
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DEVICE_AND_API_INIT(uart_6, DT_LABEL(DT_NODELABEL(uart6)),
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uart_psoc6_init, NULL,
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&cypress_psoc6_uart6_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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@ -1,42 +0,0 @@
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/*
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* Copyright (c) 2018, Cypress
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* SoC level DTS fixup file */
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#define DT_UART_PSOC6_UART_5_NAME "uart_5"
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#define DT_UART_PSOC6_UART_5_BASE_ADDRESS SCB5
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#define DT_UART_PSOC6_UART_5_PORT P5_0_PORT
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#define DT_UART_PSOC6_UART_5_RX_NUM P5_0_NUM
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#define DT_UART_PSOC6_UART_5_TX_NUM P5_1_NUM
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#define DT_UART_PSOC6_UART_5_RX_VAL P5_0_SCB5_UART_RX
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#define DT_UART_PSOC6_UART_5_TX_VAL P5_1_SCB5_UART_TX
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#define DT_UART_PSOC6_UART_5_CLOCK PCLK_SCB5_CLOCK
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#define DT_UART_PSOC6_UART_6_NAME "uart_6"
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#define DT_UART_PSOC6_UART_6_BASE_ADDRESS SCB6
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#define DT_UART_PSOC6_UART_6_PORT P12_0_PORT
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#define DT_UART_PSOC6_UART_6_RX_NUM P12_0_NUM
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#define DT_UART_PSOC6_UART_6_TX_NUM P12_1_NUM
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#define DT_UART_PSOC6_UART_6_RX_VAL P12_0_SCB6_UART_RX
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#define DT_UART_PSOC6_UART_6_TX_VAL P12_1_SCB6_UART_TX
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#define DT_UART_PSOC6_UART_6_CLOCK PCLK_SCB6_CLOCK
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/* UART desired baud rate is 115200 bps (Standard mode).
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* The UART baud rate = (SCB clock frequency / Oversample).
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* For PeriClk = 50 MHz, select divider value 36 and get SCB clock = (50 MHz / 36) = 1,389 MHz.
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* Select Oversample = 12. These setting results UART data rate = 1,389 MHz / 12 = 115750 bps.
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*/
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#define DT_UART_PSOC6_CONFIG_OVERSAMPLE (12UL)
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#define DT_UART_PSOC6_CONFIG_BREAKWIDTH (11UL)
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#define DT_UART_PSOC6_CONFIG_DATAWIDTH (8UL)
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/* Assign divider type and number for UART */
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#define DT_UART_PSOC6_UART_CLK_DIV_TYPE (CY_SYSCLK_DIV_8_BIT)
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#define DT_UART_PSOC6_UART_CLK_DIV_NUMBER (PERI_DIV_8_NR - 1u)
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#define DT_UART_PSOC6_UART_CLK_DIV_VAL (35UL)
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/* End of SoC Level DTS fixup file */
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