drivers: serial: uart_psoc6: Convert to new dt macros

Convert the driver to use the new dt macros.  As part of this change we
remove a bunch of defines that happened in dts_fixup.h that didn't
belong there.  Some of these should be converted to devicetree
properties at some point.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-04-22 05:39:25 -05:00 committed by Kumar Gala
commit 7b2fde91d8
2 changed files with 42 additions and 68 deletions

View file

@ -22,6 +22,22 @@
#include "cy_gpio.h"
#include "cy_scb_uart.h"
/* UART desired baud rate is 115200 bps (Standard mode).
* The UART baud rate = (SCB clock frequency / Oversample).
* For PeriClk = 50 MHz, select divider value 36 and get
* SCB clock = (50 MHz / 36) = 1,389 MHz.
* Select Oversample = 12.
* These setting results UART data rate = 1,389 MHz / 12 = 115750 bps.
*/
#define UART_PSOC6_CONFIG_OVERSAMPLE (12UL)
#define UART_PSOC6_CONFIG_BREAKWIDTH (11UL)
#define UART_PSOC6_CONFIG_DATAWIDTH (8UL)
/* Assign divider type and number for UART */
#define UART_PSOC6_UART_CLK_DIV_TYPE (CY_SYSCLK_DIV_8_BIT)
#define UART_PSOC6_UART_CLK_DIV_NUMBER (PERI_DIV_8_NR - 1u)
#define UART_PSOC6_UART_CLK_DIV_VAL (35UL)
/*
* Verify Kconfig configuration
*/
@ -44,14 +60,14 @@ static const cy_stc_scb_uart_config_t uartConfig = {
.irdaInvertRx = false,
.irdaEnableLowPowerReceiver = false,
.oversample = DT_UART_PSOC6_CONFIG_OVERSAMPLE,
.oversample = UART_PSOC6_CONFIG_OVERSAMPLE,
.enableMsbFirst = false,
.dataWidth = DT_UART_PSOC6_CONFIG_DATAWIDTH,
.dataWidth = UART_PSOC6_CONFIG_DATAWIDTH,
.parity = CY_SCB_UART_PARITY_NONE,
.stopBits = CY_SCB_UART_STOP_BITS_1,
.enableInputFilter = false,
.breakWidth = DT_UART_PSOC6_CONFIG_BREAKWIDTH,
.breakWidth = UART_PSOC6_CONFIG_BREAKWIDTH,
.dropOnFrameError = false,
.dropOnParityError = false,
@ -91,14 +107,14 @@ static int uart_psoc6_init(struct device *dev)
/* Connect assigned divider to be a clock source for UART */
Cy_SysClk_PeriphAssignDivider(config->scb_clock,
DT_UART_PSOC6_UART_CLK_DIV_TYPE,
DT_UART_PSOC6_UART_CLK_DIV_NUMBER);
UART_PSOC6_UART_CLK_DIV_TYPE,
UART_PSOC6_UART_CLK_DIV_NUMBER);
Cy_SysClk_PeriphSetDivider(DT_UART_PSOC6_UART_CLK_DIV_TYPE,
DT_UART_PSOC6_UART_CLK_DIV_NUMBER,
DT_UART_PSOC6_UART_CLK_DIV_VAL);
Cy_SysClk_PeriphEnableDivider(DT_UART_PSOC6_UART_CLK_DIV_TYPE,
DT_UART_PSOC6_UART_CLK_DIV_NUMBER);
Cy_SysClk_PeriphSetDivider(UART_PSOC6_UART_CLK_DIV_TYPE,
UART_PSOC6_UART_CLK_DIV_NUMBER,
UART_PSOC6_UART_CLK_DIV_VAL);
Cy_SysClk_PeriphEnableDivider(UART_PSOC6_UART_CLK_DIV_TYPE,
UART_PSOC6_UART_CLK_DIV_NUMBER);
/* Configure UART to operate */
(void) Cy_SCB_UART_Init(config->base, &uartConfig, NULL);
@ -133,16 +149,16 @@ static const struct uart_driver_api uart_psoc6_driver_api = {
#ifdef CONFIG_UART_PSOC6_UART_5
static const struct cypress_psoc6_config cypress_psoc6_uart5_config = {
.base = DT_UART_PSOC6_UART_5_BASE_ADDRESS,
.port = DT_UART_PSOC6_UART_5_PORT,
.rx_num = DT_UART_PSOC6_UART_5_RX_NUM,
.tx_num = DT_UART_PSOC6_UART_5_TX_NUM,
.rx_val = DT_UART_PSOC6_UART_5_RX_VAL,
.tx_val = DT_UART_PSOC6_UART_5_TX_VAL,
.scb_clock = DT_UART_PSOC6_UART_5_CLOCK,
.base = (CySCB_Type *)DT_REG_ADDR(DT_NODELABEL(uart5)),
.port = P5_0_PORT,
.rx_num = P5_0_NUM,
.tx_num = P5_1_NUM,
.rx_val = P5_0_SCB5_UART_RX,
.tx_val = P5_1_SCB5_UART_TX,
.scb_clock = PCLK_SCB5_CLOCK,
};
DEVICE_AND_API_INIT(uart_5, DT_UART_PSOC6_UART_5_NAME,
DEVICE_AND_API_INIT(uart_5, DT_LABEL(DT_NODELABEL(uart5)),
uart_psoc6_init, NULL,
&cypress_psoc6_uart5_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
@ -151,16 +167,16 @@ DEVICE_AND_API_INIT(uart_5, DT_UART_PSOC6_UART_5_NAME,
#ifdef CONFIG_UART_PSOC6_UART_6
static const struct cypress_psoc6_config cypress_psoc6_uart6_config = {
.base = DT_UART_PSOC6_UART_6_BASE_ADDRESS,
.port = DT_UART_PSOC6_UART_6_PORT,
.rx_num = DT_UART_PSOC6_UART_6_RX_NUM,
.tx_num = DT_UART_PSOC6_UART_6_TX_NUM,
.rx_val = DT_UART_PSOC6_UART_6_RX_VAL,
.tx_val = DT_UART_PSOC6_UART_6_TX_VAL,
.scb_clock = DT_UART_PSOC6_UART_6_CLOCK,
.base = (CySCB_Type *)DT_REG_ADDR(DT_NODELABEL(uart6)),
.port = P12_0_PORT,
.rx_num = P12_0_NUM,
.tx_num = P12_1_NUM,
.rx_val = P12_0_SCB6_UART_RX,
.tx_val = P12_1_SCB6_UART_TX,
.scb_clock = PCLK_SCB6_CLOCK,
};
DEVICE_AND_API_INIT(uart_6, DT_UART_PSOC6_UART_6_NAME,
DEVICE_AND_API_INIT(uart_6, DT_LABEL(DT_NODELABEL(uart6)),
uart_psoc6_init, NULL,
&cypress_psoc6_uart6_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,

View file

@ -1,42 +0,0 @@
/*
* Copyright (c) 2018, Cypress
*
* SPDX-License-Identifier: Apache-2.0
*/
/* SoC level DTS fixup file */
#define DT_UART_PSOC6_UART_5_NAME "uart_5"
#define DT_UART_PSOC6_UART_5_BASE_ADDRESS SCB5
#define DT_UART_PSOC6_UART_5_PORT P5_0_PORT
#define DT_UART_PSOC6_UART_5_RX_NUM P5_0_NUM
#define DT_UART_PSOC6_UART_5_TX_NUM P5_1_NUM
#define DT_UART_PSOC6_UART_5_RX_VAL P5_0_SCB5_UART_RX
#define DT_UART_PSOC6_UART_5_TX_VAL P5_1_SCB5_UART_TX
#define DT_UART_PSOC6_UART_5_CLOCK PCLK_SCB5_CLOCK
#define DT_UART_PSOC6_UART_6_NAME "uart_6"
#define DT_UART_PSOC6_UART_6_BASE_ADDRESS SCB6
#define DT_UART_PSOC6_UART_6_PORT P12_0_PORT
#define DT_UART_PSOC6_UART_6_RX_NUM P12_0_NUM
#define DT_UART_PSOC6_UART_6_TX_NUM P12_1_NUM
#define DT_UART_PSOC6_UART_6_RX_VAL P12_0_SCB6_UART_RX
#define DT_UART_PSOC6_UART_6_TX_VAL P12_1_SCB6_UART_TX
#define DT_UART_PSOC6_UART_6_CLOCK PCLK_SCB6_CLOCK
/* UART desired baud rate is 115200 bps (Standard mode).
* The UART baud rate = (SCB clock frequency / Oversample).
* For PeriClk = 50 MHz, select divider value 36 and get SCB clock = (50 MHz / 36) = 1,389 MHz.
* Select Oversample = 12. These setting results UART data rate = 1,389 MHz / 12 = 115750 bps.
*/
#define DT_UART_PSOC6_CONFIG_OVERSAMPLE (12UL)
#define DT_UART_PSOC6_CONFIG_BREAKWIDTH (11UL)
#define DT_UART_PSOC6_CONFIG_DATAWIDTH (8UL)
/* Assign divider type and number for UART */
#define DT_UART_PSOC6_UART_CLK_DIV_TYPE (CY_SYSCLK_DIV_8_BIT)
#define DT_UART_PSOC6_UART_CLK_DIV_NUMBER (PERI_DIV_8_NR - 1u)
#define DT_UART_PSOC6_UART_CLK_DIV_VAL (35UL)
/* End of SoC Level DTS fixup file */