soc: riscv: add initial support of andes_v5 soc series
Add andes_v5 SoC series and andes_ae350 SoC. It includes soc initialization code, linker script, and custom CSR encoding. Signed-off-by: Jim Shu <cwshu@andestech.com>
This commit is contained in:
parent
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commit
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11 changed files with 691 additions and 0 deletions
7
soc/riscv/riscv-privilege/andes_v5/CMakeLists.txt
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7
soc/riscv/riscv-privilege/andes_v5/CMakeLists.txt
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(${CONFIG_SOC})
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zephyr_sources(
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start.S
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)
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21
soc/riscv/riscv-privilege/andes_v5/Kconfig.defconfig.ae350
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21
soc/riscv/riscv-privilege/andes_v5/Kconfig.defconfig.ae350
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# Copyright (c) 2021 Andes Technology Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_RISCV_ANDES_AE350
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config SOC
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default "ae350"
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config SYS_CLOCK_TICKS_PER_SEC
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default 100 if !CACHE_ENABLE
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config MAIN_STACK_SIZE
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default 2048
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config IDLE_STACK_SIZE
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default 1536
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config TEST_EXTRA_STACKSIZE
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default 1024
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endif # SOC_RISCV_ANDES_AE350
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44
soc/riscv/riscv-privilege/andes_v5/Kconfig.defconfig.series
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44
soc/riscv/riscv-privilege/andes_v5/Kconfig.defconfig.series
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# Copyright (c) 2021 Andes Technology Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_RISCV_ANDES_V5
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# Kconfig picks the first default with a satisfied condition.
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# SoC defaults should be parsed before SoC Series defaults, because SoCs usually
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# overrides SoC Series values.
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source "soc/riscv/riscv-privilege/andes_v5/Kconfig.defconfig.ae*"
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config SOC_SERIES
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default "andes_v5"
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 60000000
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config KERNEL_ENTRY
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default "entry"
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config RISCV_SOC_INTERRUPT_INIT
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default y
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config RISCV_HAS_CPU_IDLE
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default y
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config RISCV_HAS_PLIC
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default y
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config RISCV_GP
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default y
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config 2ND_LVL_ISR_TBL_OFFSET
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default 12
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config 2ND_LVL_INTR_00_OFFSET
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default 11
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config MAX_IRQ_PER_AGGREGATOR
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default 52
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config NUM_IRQS
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default 64
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endif # SOC_SERIES_RISCV_ANDES_V5
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9
soc/riscv/riscv-privilege/andes_v5/Kconfig.series
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9
soc/riscv/riscv-privilege/andes_v5/Kconfig.series
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# Copyright (c) 2021 Andes Technology Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RISCV_ANDES_V5
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bool "Andes V5 SoC Series Implementation"
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select RISCV
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select SOC_FAMILY_RISCV_PRIVILEGE
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help
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Enable support for Andes V5 SoC Series
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50
soc/riscv/riscv-privilege/andes_v5/Kconfig.soc
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soc/riscv/riscv-privilege/andes_v5/Kconfig.soc
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# Copyright (c) 2021 Andes Technology Corporation
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "Andes V5 SoC Selection"
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depends on SOC_SERIES_RISCV_ANDES_V5
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config SOC_RISCV_ANDES_AE350
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bool "Andes AE350 SoC implementation"
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select ATOMIC_OPERATIONS_BUILTIN
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endchoice
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if SOC_SERIES_RISCV_ANDES_V5
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choice
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prompt "Base CPU ISA options"
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default RV32I_CPU
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config RV32I_CPU
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bool "RISCV32 CPU ISA"
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config RV64I_CPU
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bool "RISCV64 CPU ISA"
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select 64BIT
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endchoice
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choice
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prompt "FPU options"
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default NO_FPU
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config NO_FPU
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bool "No FPU"
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config SINGLE_PRECISION_FPU
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bool "Single precision FPU"
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select CPU_HAS_FPU
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config DOUBLE_PRECISION_FPU
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bool "Double precision FPU"
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select CPU_HAS_FPU_DOUBLE_PRECISION
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endchoice
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config CACHE_ENABLE
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bool "Enable cache"
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default n
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endif # SOC_SERIES_RISCV_ANDES_V5
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358
soc/riscv/riscv-privilege/andes_v5/ae350/linker.ld
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358
soc/riscv/riscv-privilege/andes_v5/ae350/linker.ld
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/*
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* Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>
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* Copyright (c) 2021 Andes Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Linker command/script file
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*
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* Linker script for the ae350 platform
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*/
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#include <soc.h>
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#include <devicetree.h>
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#include <autoconf.h>
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#include <linker/sections.h>
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#include <linker/devicetree_regions.h>
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#include <linker/linker-defs.h>
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#include <linker/linker-tool.h>
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#ifdef CONFIG_XIP
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#define ROMABLE_REGION ROM
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#else
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#define ROMABLE_REGION RAM
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#endif
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#define RAMABLE_REGION RAM
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#define _VECTOR_SECTION_NAME vector
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#define _EXCEPTION_SECTION_NAME exceptions
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#define _RESET_SECTION_NAME reset
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#ifdef CONFIG_XIP
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#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)
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#ifdef CONFIG_FLASH_LOAD_OFFSET
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#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \
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CONFIG_FLASH_LOAD_OFFSET)
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#else /* !CONFIG_FLASH_LOAD_OFFSET */
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#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
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#endif /* CONFIG_FLASH_LOAD_OFFSET */
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#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
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#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)
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/* For jedec,spi-nor we expect the spi controller to memory map the flash
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* and for that mapping to be the second register property of the spi
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* controller.
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*/
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#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))
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#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)
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#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)
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#endif
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#else /* CONFIG_XIP */
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#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS
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#define ROM_SIZE KB(CONFIG_SRAM_SIZE)
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#endif /* CONFIG_XIP */
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#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS
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#define RAM_SIZE KB(CONFIG_SRAM_SIZE)
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MEMORY
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{
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#ifdef CONFIG_XIP
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ROM (rx) : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE
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#endif
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RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
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/* Data & Instruction Tightly Coupled Memory */
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LINKER_DT_REGION_FROM_NODE(ITCM, rw, DT_CHOSEN(zephyr_itcm))
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LINKER_DT_REGION_FROM_NODE(DTCM, rw, DT_CHOSEN(zephyr_dtcm))
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/* Used by and documented in include/linker/intlist.ld */
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IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
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}
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ENTRY(CONFIG_KERNEL_ENTRY)
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SECTIONS
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{
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#include <linker/rel-sections.ld>
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/*
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* The .plt and .iplt are here according to
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* 'riscv32-zephyr-elf-ld --verbose', before text section.
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*/
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SECTION_PROLOGUE(.plt,,)
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{
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*(.plt)
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}
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SECTION_PROLOGUE(.iplt,,)
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{
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*(.iplt)
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}
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GROUP_START(ROMABLE_REGION)
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_image_rom_start = ROM_BASE;
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SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)
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{
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/* In XIP mode, the .init section must be at the start of ROM */
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. = ALIGN(4);
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KEEP(*(.init.*))
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. = ALIGN(4);
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KEEP(*(.vectors.*))
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} GROUP_LINK_IN(ROMABLE_REGION)
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SECTION_PROLOGUE(rom_start,,)
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{
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. = ALIGN(16);
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/* Located in generated directory. This file is populated by calling
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* zephyr_linker_sources(ROM_START ...).
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*/
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#include <snippets-rom-start.ld>
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} GROUP_LINK_IN(ROMABLE_REGION)
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SECTION_PROLOGUE(_RESET_SECTION_NAME,,)
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{
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KEEP(*(.reset.*))
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} GROUP_LINK_IN(ROMABLE_REGION)
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SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)
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{
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KEEP(*(".exception.entry.*"))
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*(".exception.other.*")
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} GROUP_LINK_IN(ROMABLE_REGION)
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SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
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{
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. = ALIGN(4);
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KEEP(*(.openocd_debug))
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KEEP(*(".openocd_debug.*"))
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_image_text_start = .;
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*(.text)
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*(".text.*")
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*(.gnu.linkonce.t.*)
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#include <linker/kobject-text.ld>
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#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION
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. = ALIGN(0x1000);
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_ram_code_start = .;
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KEEP(*(.__ram_code))
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__ram_code_size = . - _ram_code_start;
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ASSERT((__ram_code_size <= 0x1000),
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"__ram_code_size <= 4k bytes");
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#endif
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} GROUP_LINK_IN(ROMABLE_REGION)
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_image_text_end = .;
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_image_rodata_start = .;
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#include <linker/common-rom.ld>
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#include <linker/thread-local-storage.ld>
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SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
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{
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. = ALIGN(4);
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*(.srodata)
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*(".srodata.*")
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*(.rodata)
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*(".rodata.*")
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*(.gnu.linkonce.r.*)
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*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-rodata.ld>
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#include <linker/kobject-rom.ld>
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. = ALIGN(4);
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} GROUP_LINK_IN(ROMABLE_REGION)
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#include <linker/cplusplus-rom.ld>
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_image_rodata_end = .;
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MPU_ALIGN(_image_rodata_end - _image_rom_start);
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GROUP_END(ROMABLE_REGION)
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GROUP_START(RAMABLE_REGION)
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#if defined(CONFIG_USERSPACE)
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#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN
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#define SMEM_PARTITION_ALIGN MPU_ALIGN
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#include <app_smem.ld>
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_image_ram_start = _app_smem_start;
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_app_smem_size = _app_smem_end - _app_smem_start;
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_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
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#endif /* CONFIG_USERSPACE */
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SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
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{
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MPU_MIN_SIZE_ALIGN
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/*
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* For performance, BSS section is assumed to be 4 byte aligned and
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* a multiple of 4 bytes
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*/
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. = ALIGN(4);
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__bss_start = .;
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_image_ram_start = .;
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__kernel_ram_start = .;
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*(.sbss)
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*(".sbss.*")
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*(.bss)
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*(".bss.*")
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COMMON_SYMBOLS
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/*
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* As memory is cleared in words only, it is simpler to ensure the BSS
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* section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
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*/
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__bss_end = ALIGN(4);
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
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#include <linker/common-noinit.ld>
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#include <linker/cplusplus-ram.ld>
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SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
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{
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. = ALIGN(4);
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/* _image_ram_start = .; */
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__data_ram_start = .;
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*(.data)
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*(".data.*")
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#ifdef CONFIG_RISCV_GP
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/*
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* RISC-V architecture has 12-bit signed immediate offsets in the
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* instructions. If we can put the most commonly accessed globals
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* in a special 4K span of memory addressed by the GP register, then
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* we can access those values in a single instruction, saving both
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* codespace and runtime.
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*
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* Since these immediate offsets are signed, place gp 0x800 past the
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* beginning of .sdata so that we can use both positive and negative
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* offsets.
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*/
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. = ALIGN(8);
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PROVIDE (__global_pointer$ = . + 0x800);
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#endif
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*(.sdata .sdata.* .gnu.linkonce.s.*)
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-rwdata.ld>
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
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__data_rom_start = LOADADDR(_DATA_SECTION_NAME);
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#include <linker/common-ram.ld>
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#include <linker/kobject-data.ld>
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-ram-sections.ld>
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-data-sections.ld>
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__data_ram_end = .;
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MPU_MIN_SIZE_ALIGN
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_image_ram_end = .;
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_end = .; /* end of image */
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|
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__kernel_ram_end = .;
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__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;
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|
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#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)
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GROUP_START(ITCM)
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SECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))
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{
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__itcm_start = .;
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*(.itcm)
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*(".itcm.*")
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__itcm_end = .;
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} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)
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__itcm_size = __itcm_end - __itcm_start;
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__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);
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GROUP_END(ITCM)
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#endif
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#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)
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GROUP_START(DTCM)
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SECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))
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{
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__dtcm_start = .;
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__dtcm_bss_start = .;
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*(.dtcm_bss)
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*(".dtcm_bss.*")
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__dtcm_bss_end = .;
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} GROUP_LINK_IN(DTCM)
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SECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))
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{
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__dtcm_noinit_start = .;
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*(.dtcm_noinit)
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*(".dtcm_noinit.*")
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__dtcm_noinit_end = .;
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} GROUP_LINK_IN(DTCM)
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SECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))
|
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{
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__dtcm_data_start = .;
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*(.dtcm_data)
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*(".dtcm_data.*")
|
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__dtcm_data_end = .;
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} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)
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__dtcm_end = .;
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|
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__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);
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GROUP_END(DTCM)
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#endif
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
|
||||
*/
|
||||
#include <snippets-sections.ld>
|
||||
|
||||
GROUP_END(RAMABLE_REGION)
|
||||
|
||||
#include <linker/debug-sections.ld>
|
||||
|
||||
/DISCARD/ : { *(.note.GNU-stack) }
|
||||
|
||||
SECTION_PROLOGUE(.riscv.attributes, 0,)
|
||||
{
|
||||
KEEP(*(.riscv.attributes))
|
||||
KEEP(*(.gnu.attributes))
|
||||
}
|
||||
|
||||
/* Must be last in romable region */
|
||||
SECTION_PROLOGUE(.last_section,(NOLOAD),)
|
||||
{
|
||||
} GROUP_LINK_IN(ROMABLE_REGION)
|
||||
|
||||
/* To provide the image size as a const expression,
|
||||
* calculate this value here. */
|
||||
_image_rom_end = LOADADDR(.last_section);
|
||||
_image_rom_size = _image_rom_end - _image_rom_start;
|
||||
|
||||
}
|
31
soc/riscv/riscv-privilege/andes_v5/ae350/soc.h
Normal file
31
soc/riscv/riscv-privilege/andes_v5/ae350/soc.h
Normal file
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Andes Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macros for the Andes AE350 platform
|
||||
*/
|
||||
|
||||
#ifndef __RISCV_ANDES_AE350_SOC_H_
|
||||
#define __RISCV_ANDES_AE350_SOC_H_
|
||||
|
||||
#include <soc_common.h>
|
||||
#include <devicetree.h>
|
||||
|
||||
/* Machine timer memory-mapped registers */
|
||||
#define RISCV_MTIME_BASE 0xE6000000
|
||||
#define RISCV_MTIMECMP_BASE 0xE6000008
|
||||
|
||||
/* lib-c hooks required RAM defined variables */
|
||||
#define RISCV_RAM_BASE CONFIG_SRAM_BASE_ADDRESS
|
||||
#define RISCV_RAM_SIZE KB(CONFIG_SRAM_SIZE)
|
||||
|
||||
/* Include CSRs available for Andes V5 SoCs */
|
||||
#include "soc_v5.h"
|
||||
|
||||
/* Include platform peripherals */
|
||||
#include "smu.h"
|
||||
|
||||
#endif /* __RISCV_ANDES_AE350_SOC_H_ */
|
18
soc/riscv/riscv-privilege/andes_v5/linker.ld
Normal file
18
soc/riscv/riscv-privilege/andes_v5/linker.ld
Normal file
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Andes Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Linker command/script file
|
||||
*
|
||||
* linker script for andes_v5 SoC Series
|
||||
*/
|
||||
|
||||
#include <autoconf.h>
|
||||
|
||||
#if defined(CONFIG_SOC_RISCV_ANDES_AE350)
|
||||
# include <ae350/linker.ld>
|
||||
#endif
|
57
soc/riscv/riscv-privilege/andes_v5/smu.h
Normal file
57
soc/riscv/riscv-privilege/andes_v5/smu.h
Normal file
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Andes Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macros for the Andes ATCSMU
|
||||
*/
|
||||
|
||||
#ifndef SOC_RISCV_ANDES_V5_SMU_H_
|
||||
#define SOC_RISCV_ANDES_V5_SMU_H_
|
||||
|
||||
/*
|
||||
* SMU Register Base Address
|
||||
*/
|
||||
|
||||
#if DT_NODE_EXISTS(DT_INST(0, andestech_atcsmu100))
|
||||
#define SMU_BASE DT_REG_ADDR(DT_INST(0, andestech_atcsmu100))
|
||||
#endif /* DT_NODE_EXISTS(DT_INST(0, andestech_atcsmu100)) */
|
||||
|
||||
/*
|
||||
* SMU register offset
|
||||
*/
|
||||
|
||||
/* Basic */
|
||||
#define SMU_SYSTEMVER 0x00
|
||||
#define SMU_BOARDVER 0x04
|
||||
#define SMU_SYSTEMCFG 0x08
|
||||
#define SMU_SMUVER 0x0C
|
||||
|
||||
/* Reset vectors */
|
||||
#define SMU_HARTn_RESET_VECTOR(n) (0x50 + 0x8 * (n))
|
||||
|
||||
/* Power control slot */
|
||||
#define SMU_PCSn_CFG(n) (0x80 + 0x20 * (n))
|
||||
#define SMU_PCSn_SCRATCH(n) (0x80 + 0x20 * (n))
|
||||
#define SMU_PCSn_MISC(n) (0x80 + 0x20 * (n))
|
||||
#define SMU_PCSn_MISC2(n) (0x80 + 0x20 * (n))
|
||||
#define SMU_PCSn_WE(n) (0x80 + 0x20 * (n))
|
||||
#define SMU_PCSn_CTL(n) (0x80 + 0x20 * (n))
|
||||
#define SMU_PCSn_STATUS(n) (0x80 + 0x20 * (n))
|
||||
|
||||
/* Pinmux */
|
||||
#define SMU_PINMUX_CTRL0 0x1000
|
||||
#define SMU_PINMUX_CTRL1 0x1004
|
||||
|
||||
/*
|
||||
* SMU helper constant
|
||||
*/
|
||||
|
||||
#define SMU_SYSTEMCFG_CORENUM_MASK 0xFF
|
||||
#define SMU_SYSTEMCFG_L2C BIT(8)
|
||||
#define SMU_SYSTEMCFG_DFS BIT(9)
|
||||
#define SMU_SYSTEMCFG_DC_COHEN BIT(10)
|
||||
|
||||
#endif /* SOC_RISCV_ANDES_V5_SMU_H_ */
|
39
soc/riscv/riscv-privilege/andes_v5/soc_v5.h
Normal file
39
soc/riscv/riscv-privilege/andes_v5/soc_v5.h
Normal file
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Andes Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __RISCV_ANDES_V5_SOC_V5_H_
|
||||
#define __RISCV_ANDES_V5_SOC_V5_H_
|
||||
|
||||
/* Control and Status Registers (CSRs) available for Andes V5 SoCs */
|
||||
#define NDS_MMISC_CTL 0x7D0
|
||||
#define NDS_MCACHE_CTL 0x7CA
|
||||
#define NDS_MMSC_CFG 0xFC2
|
||||
#define NDS_MXSTATUS 0x7C4
|
||||
#define NDS_UCODE 0x801
|
||||
|
||||
/* Control and Status Registers (CSRs) available for Andes V5 PMA */
|
||||
#define NDS_PMACFG0 0xBC0
|
||||
#define NDS_PMACFG1 0xBC1
|
||||
#define NDS_PMACFG2 0xBC2
|
||||
#define NDS_PMACFG3 0xBC3
|
||||
#define NDS_PMAADDR0 0xBD0
|
||||
#define NDS_PMAADDR1 0xBD1
|
||||
#define NDS_PMAADDR2 0xBD2
|
||||
#define NDS_PMAADDR3 0xBD3
|
||||
#define NDS_PMAADDR4 0xBD4
|
||||
#define NDS_PMAADDR5 0xBD5
|
||||
#define NDS_PMAADDR6 0xBD6
|
||||
#define NDS_PMAADDR7 0xBD7
|
||||
#define NDS_PMAADDR8 0xBD8
|
||||
#define NDS_PMAADDR9 0xBD9
|
||||
#define NDS_PMAADDR10 0xBDA
|
||||
#define NDS_PMAADDR11 0xBDB
|
||||
#define NDS_PMAADDR12 0xBDC
|
||||
#define NDS_PMAADDR13 0xBDD
|
||||
#define NDS_PMAADDR14 0xBDE
|
||||
#define NDS_PMAADDR15 0xBDF
|
||||
|
||||
#endif /* __RISCV_ANDES_V5_SOC_V5_H_ */
|
57
soc/riscv/riscv-privilege/andes_v5/start.S
Normal file
57
soc/riscv/riscv-privilege/andes_v5/start.S
Normal file
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Andes Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <toolchain.h>
|
||||
#include <soc.h>
|
||||
|
||||
/* exports */
|
||||
GTEXT(entry)
|
||||
|
||||
SECTION_FUNC(init, entry)
|
||||
/* Disable linker relaxation before GP register initialization. */
|
||||
.option push
|
||||
.option norelax
|
||||
|
||||
#ifdef __nds_execit
|
||||
/* Initialize EXECIT table */
|
||||
la t0, _ITB_BASE_
|
||||
csrw uitb, t0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CACHE_ENABLE
|
||||
/*
|
||||
* Enable I/D cache with HW prefetcher,
|
||||
* D-cache write-around (threshold: 4 cache lines),
|
||||
* and CM (Coherence Manager).
|
||||
*/
|
||||
li t0, (0x3 << 13)
|
||||
csrc NDS_MCACHE_CTL, t0
|
||||
li t0, (1 << 19) | (1 << 13) | (1 << 10) | (1 << 9) | (0x3)
|
||||
csrs NDS_MCACHE_CTL, t0
|
||||
|
||||
/* Check if CPU support CM or not. */
|
||||
csrr t0, NDS_MCACHE_CTL
|
||||
li t1, (1 << 19)
|
||||
and t0, t0, t1
|
||||
beqz t0, cache_enable_finish
|
||||
|
||||
/* If CPU support CM, check if CM is enabled. */
|
||||
li t1, (1 << 20)
|
||||
check_cm_enabled:
|
||||
csrr t0, NDS_MCACHE_CTL
|
||||
and t0, t0, t1
|
||||
beqz t0, check_cm_enabled
|
||||
|
||||
cache_enable_finish:
|
||||
#endif
|
||||
|
||||
/* Enable misaligned access and non-blocking load */
|
||||
li t0, (1 << 8) | (1 << 6)
|
||||
csrs NDS_MMISC_CTL, t0
|
||||
|
||||
j __start
|
||||
|
||||
.option pop
|
Loading…
Add table
Add a link
Reference in a new issue