drivers: pinctrl: npcx: add initial pin-controller driver
This CL is the initial version for npcx pinctrl driver and introduces pinctrl nodes for both IO-pads and peripheral devices for each npcx series. Users can set pin configuration via these nodes in the board layout DT file. It also wraps all configurations related to pin-muxing in pinctrl_soc.h. Regarding the other pin properties, we will implement them later. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit is contained in:
parent
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commit
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14 changed files with 1225 additions and 0 deletions
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@ -7,6 +7,7 @@
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/dts-v1/;
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#include <nuvoton/npcx7m6fb.dtsi>
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#include <nuvoton/npcx/npcx7/npcx7-pinctrl.dtsi>
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/ {
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model = "Nuvoton NPCX7M6FB evaluation board";
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@ -30,6 +30,9 @@ CONFIG_UART_INTERRUPT_DRIVEN=y
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# GPIO Driver
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CONFIG_GPIO=y
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# Pin Controller Driver
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CONFIG_PINCTRL=y
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# Console Driver
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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@ -7,6 +7,7 @@
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/dts-v1/;
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#include <nuvoton/npcx9m6f.dtsi>
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#include <nuvoton/npcx/npcx9/npcx9-pinctrl.dtsi>
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/ {
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model = "Nuvoton NPCX9M6F evaluation board";
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@ -30,6 +30,9 @@ CONFIG_UART_INTERRUPT_DRIVEN=y
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# GPIO Driver
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CONFIG_GPIO=y
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# Pin Controller Driver
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CONFIG_PINCTRL=y
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# Console Driver
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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@ -7,6 +7,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_TELINK_B91 pinctrl_b91.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AF pinctrl_gd32_af.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AFIO pinctrl_gd32_afio.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_ITE_IT8XXX2 pinctrl_ite_it8xxx2.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_NPCX pinctrl_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_NRF pinctrl_nrf.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RCAR_PFC pfc_rcar.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RPI_PICO pinctrl_rpi_pico.c)
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@ -32,6 +32,7 @@ config PINCTRL_DYNAMIC
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source "drivers/pinctrl/Kconfig.b91"
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source "drivers/pinctrl/Kconfig.gd32"
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source "drivers/pinctrl/Kconfig.it8xxx2"
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source "drivers/pinctrl/Kconfig.npcx"
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source "drivers/pinctrl/Kconfig.nrf"
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source "drivers/pinctrl/Kconfig.rcar"
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source "drivers/pinctrl/Kconfig.rpi_pico"
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15
drivers/pinctrl/Kconfig.npcx
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15
drivers/pinctrl/Kconfig.npcx
Normal file
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@ -0,0 +1,15 @@
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# NPCX Pin Controller configuration options
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# Copyright (c) 2022 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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DT_COMPAT_ST_PINCTRL_NPCX := nuvoton,npcx-pinctrl
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config PINCTRL_NPCX
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bool "Nuvoton NPCX embedded controller (EC) pin controller driver"
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depends on SOC_FAMILY_NPCX
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select PINCTRL_STORE_REG
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default $(dt_compat_enabled,$(DT_COMPAT_ST_PINCTRL_NPCX))
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help
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This option enables the pin controller driver for NPCX family of
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processors.
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114
drivers/pinctrl/pinctrl_npcx.c
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114
drivers/pinctrl/pinctrl_npcx.c
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@ -0,0 +1,114 @@
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/*
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* Copyright (c) 2022 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <assert.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <soc.h>
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/* Driver config */
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struct npcx_pinctrl_config {
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/* scfg device base address */
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uintptr_t base_scfg;
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};
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static const struct npcx_pinctrl_config npcx_pinctrl_cfg = {
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.base_scfg = DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), scfg),
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};
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/* Pin-control local functions for peripheral devices */
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static bool npcx_periph_pinmux_has_lock(int group)
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{
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#if defined(CONFIG_SOC_SERIES_NPCX7)
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if (group == 0x00 || (group >= 0x02 && group <= 0x04) || group == 0x06 ||
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group == 0x0b || group == 0x0f) {
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return true;
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}
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#elif defined(CONFIG_SOC_SERIES_NPCX9)
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if (group == 0x00 || (group >= 0x02 && group <= 0x06) || group == 0x0b ||
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group == 0x0d || (group >= 0x0f && group <= 0x12)) {
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return true;
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}
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#endif
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return false;
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}
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static void npcx_periph_pinmux_configure(const struct npcx_periph *alt, bool is_alternate,
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bool is_locked)
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{
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const uintptr_t scfg_base = npcx_pinctrl_cfg.base_scfg;
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uint8_t alt_mask = BIT(alt->bit);
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/*
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* is_alternate == 0 means select GPIO, otherwise Alternate Func.
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* inverted == 0:
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* Set devalt bit to select Alternate Func.
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* inverted == 1:
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* Clear devalt bit to select Alternate Func.
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*/
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if (is_alternate != alt->inverted) {
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NPCX_DEVALT(scfg_base, alt->group) |= alt_mask;
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} else {
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NPCX_DEVALT(scfg_base, alt->group) &= ~alt_mask;
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}
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if (is_locked && npcx_periph_pinmux_has_lock(alt->group)) {
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NPCX_DEVALT_LK(scfg_base, alt->group) |= alt_mask;
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}
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}
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static void npcx_periph_pupd_configure(const struct npcx_periph *pupd,
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enum npcx_io_bias_type type)
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{
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const uintptr_t scfg_base = npcx_pinctrl_cfg.base_scfg;
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if (type == NPCX_BIAS_TYPE_NONE) {
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NPCX_PUPD_EN(scfg_base, pupd->group) &= ~BIT(pupd->bit);
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} else {
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NPCX_PUPD_EN(scfg_base, pupd->group) |= BIT(pupd->bit);
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}
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}
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static void npcx_periph_pwm_drive_mode_configure(uintptr_t reg, bool is_od)
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{
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struct pwm_reg *const inst = (struct pwm_reg *)(reg);
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if (is_od) {
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inst->PWMCTLEX |= BIT(NPCX_PWMCTLEX_OD_OUT);
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} else {
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inst->PWMCTLEX &= ~BIT(NPCX_PWMCTLEX_OD_OUT);
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}
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}
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static void npcx_periph_configure(const pinctrl_soc_pin_t *pin, uintptr_t reg)
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{
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if (pin->cfg.periph.type == NPCX_PINCTRL_TYPE_PERIPH_PINMUX) {
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/* Configure peripheral device's pinmux functionality */
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npcx_periph_pinmux_configure(&pin->cfg.periph,
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!pin->flags.pinmux_gpio,
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pin->flags.pinmux_lock);
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} else if (pin->cfg.periph.type == NPCX_PINCTRL_TYPE_PERIPH_PUPD) {
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/* Configure peripheral device's internal PU/PD */
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npcx_periph_pupd_configure(&pin->cfg.periph,
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pin->flags.io_bias_type);
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} else if (pin->cfg.periph.type == NPCX_PINCTRL_TYPE_PERIPH_DRIVE) {
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/* Configure peripheral device's drive mode. (Only PWM pads support it) */
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npcx_periph_pwm_drive_mode_configure(reg,
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pin->flags.io_drive_type == NPCX_DRIVE_TYPE_OPEN_DRAIN);
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}
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}
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/* Pinctrl API implementation */
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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{
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ARG_UNUSED(reg);
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/* Configure all peripheral devices' properties here. */
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for (uint8_t i = 0; i < pin_cnt; i++) {
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npcx_periph_configure(&pins[i], reg);
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}
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return 0;
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}
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@ -69,6 +69,14 @@
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status = "disabled";
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};
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/** Dummy pinctrl node. It will be initialized with defaults based on the SoC series.
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* Then, the user can override the pin control options at the board level.
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*/
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pinctrl: pinctrl {
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compatible = "nuvoton,npcx-pinctrl";
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status = "okay";
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};
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soc {
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bbram: bb-ram@400af000 {
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compatible = "nuvoton,npcx-bbram";
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379
dts/arm/nuvoton/npcx/npcx7/npcx7-pinctrl.dtsi
Normal file
379
dts/arm/nuvoton/npcx/npcx7/npcx7-pinctrl.dtsi
Normal file
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/*
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* Copyright (c) 2022 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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&pinctrl {
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/* Prebuild nodes for peripheral device's pin-muxing and pad properties */
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/* Host peripheral interfaces */
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/omit-if-no-ref/ espi_lpc_gp46_47_51_52_53_54_55_57: periph-lpc-espi {
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pinmux = <&alt1_no_lpc_espi>;
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};
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/* I2C peripheral interfaces */
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/omit-if-no-ref/ i2c0_0_sda_scl_gpb4_b5: periph-i2c0-0 {
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pinmux = <&alt2_i2c0_0_sl>;
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periph-pupd = <0x00 0>;
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};
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/omit-if-no-ref/ i2c1_0_sda_scl_gp87_90: periph-i2c1-0 {
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pinmux = <&alt2_i2c1_0_sl>;
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periph-pupd = <0x00 2>;
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};
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/omit-if-no-ref/ i2c2_0_sda_scl_gp91_92: periph-i2c2-0 {
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pinmux = <&alt2_i2c2_0_sl>;
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periph-pupd = <0x00 4>;
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};
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/omit-if-no-ref/ i2c3_0_sda_scl_gpd0_d1: periph-i2c3-0 {
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pinmux = <&alt2_i2c3_0_sl>;
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periph-pupd = <0x00 6>;
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};
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/omit-if-no-ref/ i2c4_1_sda_scl_gpf2_f3: periph-i2c4-1 {
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pinmux = <&alt6_i2c4_1_sl>;
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periph-pupd = <0x01 2>;
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};
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/omit-if-no-ref/ i2c5_0_sda_scl_gp33_36: periph-i2c5-0 {
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pinmux = <&alt2_i2c5_0_sl>;
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periph-pupd = <0x00 5>;
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};
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/omit-if-no-ref/ i2c5_1_sda_scl_gpf4_f5: periph-i2c5-1 {
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pinmux = <&alt6_i2c5_1_sl>;
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periph-pupd = <0x01 1>;
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};
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/omit-if-no-ref/ i2c6_0_sda_scl_gpc1_c2: periph-i2c6-0 {
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pinmux = <&alt2_i2c6_0_sl>;
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periph-pupd = <0x00 3>;
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};
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/omit-if-no-ref/ i2c6_1_sda_scl_gpe3_e4: periph-i2c6-1 {
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pinmux = <&alt6_i2c6_1_sl>;
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periph-pupd = <0x01 0>;
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};
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/omit-if-no-ref/ i2c7_0_sda_scl_gpb2_b3: periph-i2c7-0 {
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pinmux = <&alt2_i2c7_0_sl>;
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periph-pupd = <0x00 1>;
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};
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/* PS2 peripheral interfaces */
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/omit-if-no-ref/ ps2_0_dat_clk_gp67_70: periph-ps2-0 {
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pinmux = <&alt3_ps2_0_sl>;
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};
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/omit-if-no-ref/ ps2_1_dat_clk_gp62_63: periph-ps2-1 {
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pinmux = <&alt3_ps2_1_sl>;
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};
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/omit-if-no-ref/ ps2_2_dat_clk_gp34_37: periph-ps2-2 {
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pinmux = <&alt3_ps2_2_sl>;
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};
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/omit-if-no-ref/ ps2_3_2_dat_clk_gpa6_a7: periph-ps2-3-2 {
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pinmux = <&altc_ps2_3_sl2>;
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};
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/* Tachometer peripheral interfaces */
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/omit-if-no-ref/ ta1_1_in_gp40: periph-ta1-1 {
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pinmux = <&alt3_ta1_sl1>;
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};
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/omit-if-no-ref/ ta1_2_in_gp93: periph-ta1-2 {
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pinmux = <&altc_ta1_sl2>;
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};
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/omit-if-no-ref/ ta2_1_in_gp73: periph-ta2-1 {
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pinmux = <&alt3_ta2_sl1>;
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};
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/omit-if-no-ref/ ta2_2_in_gpa6: periph-ta2-2 {
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pinmux = <&altc_ta2_sl2>;
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};
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/omit-if-no-ref/ tb1_1_in_gpa4: periph-tb1-1 {
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pinmux = <&alt3_tb1_sl1>;
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};
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/omit-if-no-ref/ tb1_2_in_gpd3: periph-tb1-2 {
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pinmux = <&altc_tb1_sl2>;
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};
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/omit-if-no-ref/ tb2_2_in_gpa7: periph-tb2-2 {
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pinmux = <&altc_tb2_sl2>;
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};
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/* PWM peripheral interfaces */
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/omit-if-no-ref/ pwm0_gpc3: periph-pwm0 {
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pinmux = <&alt4_pwm0_sl>;
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drive-supported;
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};
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/omit-if-no-ref/ pwm1_gpc2: periph-pwm1 {
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pinmux = <&alt4_pwm1_sl>;
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drive-supported;
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};
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/omit-if-no-ref/ pwm2_gpc4: periph-pwm2 {
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pinmux = <&alt4_pwm2_sl>;
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drive-supported;
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};
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/omit-if-no-ref/ pwm3_gp80: periph-pwm3 {
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pinmux = <&alt4_pwm3_sl>;
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drive-supported;
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};
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/omit-if-no-ref/ pwm4_gpb6: periph-pwm4 {
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pinmux = <&alt4_pwm4_sl>;
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drive-supported;
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};
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/omit-if-no-ref/ pwm5_gpb7: periph-pwm5 {
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pinmux = <&alt4_pwm5_sl>;
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drive-supported;
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};
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/omit-if-no-ref/ pwm6_gpc0: periph-pwm6 {
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pinmux = <&alt4_pwm6_sl>;
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drive-supported;
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};
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/omit-if-no-ref/ pwm7_gp60: periph-pwm7 {
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pinmux = <&alt4_pwm7_sl>;
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drive-supported;
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};
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/* Keyboard peripheral interfaces. */
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/omit-if-no-ref/ ksi0_gp31: periph-kbscan-ksi0 {
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pinmux = <&alt7_no_ksi0_sl>;
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};
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/omit-if-no-ref/ ksi1_gp30: periph-kbscan-ksi1 {
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pinmux = <&alt7_no_ksi1_sl>;
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};
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/omit-if-no-ref/ ksi2_gp27: periph-kbscan-ksi2 {
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pinmux = <&alt7_no_ksi2_sl>;
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};
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/omit-if-no-ref/ ksi3_gp26: periph-kbscan-ksi3 {
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pinmux = <&alt7_no_ksi3_sl>;
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};
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/omit-if-no-ref/ ksi4_gp25: periph-kbscan-ksi4 {
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pinmux = <&alt7_no_ksi4_sl>;
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};
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/omit-if-no-ref/ ksi5_gp24: periph-kbscan-ksi5 {
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pinmux = <&alt7_no_ksi5_sl>;
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};
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/omit-if-no-ref/ ksi6_gp23: periph-kbscan-ksi6 {
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pinmux = <&alt7_no_ksi6_sl>;
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};
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/omit-if-no-ref/ ksi7_gp22: periph-kbscan-ksi7 {
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pinmux = <&alt7_no_ksi7_sl>;
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};
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/omit-if-no-ref/ kso00_gp21: periph-kbscan-kso00 {
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pinmux = <&alt8_no_kso00_sl>;
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};
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/omit-if-no-ref/ kso01_gp20: periph-kbscan-kso01 {
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pinmux = <&alt8_no_kso01_sl>;
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};
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/omit-if-no-ref/ kso02_gp17: periph-kbscan-kso02 {
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pinmux = <&alt8_no_kso02_sl>;
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};
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/omit-if-no-ref/ kso03_gp16: periph-kbscan-kso03 {
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pinmux = <&alt8_no_kso03_sl>;
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};
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/omit-if-no-ref/ kso04_gp15: periph-kbscan-kso04 {
|
||||
pinmux = <&alt8_no_kso04_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso05_gp14: periph-kbscan-kso05 {
|
||||
pinmux = <&alt8_no_kso05_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso06_gp13: periph-kbscan-kso06 {
|
||||
pinmux = <&alt8_no_kso06_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso07_gp12: periph-kbscan-kso07 {
|
||||
pinmux = <&alt8_no_kso07_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso08_gp11: periph-kbscan-kso08 {
|
||||
pinmux = <&alt9_no_kso08_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso09_gp10: periph-kbscan-kso09 {
|
||||
pinmux = <&alt9_no_kso09_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso10_gp07: periph-kbscan-kso10 {
|
||||
pinmux = <&alt9_no_kso10_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso11_gp06: periph-kbscan-kso11 {
|
||||
pinmux = <&alt9_no_kso11_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso12_gp05: periph-kbscan-kso12 {
|
||||
pinmux = <&alt9_no_kso12_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso13_gp04: periph-kbscan-kso13 {
|
||||
pinmux = <&alt9_no_kso13_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso14_gp82: periph-kbscan-kso14 {
|
||||
pinmux = <&alt9_no_kso14_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso15_gp83: periph-kbscan-kso15 {
|
||||
pinmux = <&alt9_no_kso15_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso16_gp03: periph-kbscan-kso16 {
|
||||
pinmux = <&alta_no_kso16_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso17_gpb1: periph-kbscan-kso17 {
|
||||
pinmux = <&alta_no_kso17_sl>;
|
||||
};
|
||||
|
||||
/* Miscellaneous peripheral interfaces */
|
||||
/omit-if-no-ref/ clk_32k_out_gp75: periph-clk-32k-out {
|
||||
pinmux = <&alta_32k_out_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ vcc1_rst_gp77: periph-vcc1-rst {
|
||||
pinmux = <&alta_no_vcc1_rst>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ peci_dat_gp81: periph-peci-dat {
|
||||
pinmux = <&alta_no_peci_en>;
|
||||
};
|
||||
|
||||
/* Host UART peripheral interfaces */
|
||||
/omit-if-no-ref/ huart_rxd_gp75: periph-host-uart-rxd {
|
||||
pinmux = <&altb_rxd_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ huart_txd_gp86: periph-host-uart-txd {
|
||||
pinmux = <&altb_txd_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ huart_rts_gp36: periph-host-uart-rts {
|
||||
pinmux = <&altb_rts_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ huart_cts_gp33: periph-host-uart-cts {
|
||||
pinmux = <&altb_cts_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ huart_ri_gp42: periph-host-uart-ri {
|
||||
pinmux = <&altb_ri_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ huart_dtr_bout_gpc7: periph-host-uart-dtr_bout {
|
||||
pinmux = <&altb_dtr_bout_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ huart_dcd_gpb3: periph-host-uart-dcd {
|
||||
pinmux = <&altb_dcd_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ huart_dsr_gpb2: periph-host-uart-dsr {
|
||||
pinmux = <&altb_dsr_sl>;
|
||||
};
|
||||
|
||||
/* SHI peripheral interfaces */
|
||||
/omit-if-no-ref/ shi_gp46_47_53_55: periph-shi {
|
||||
pinmux = <&altc_shi_sl>;
|
||||
periph-pupd = <0x01 4>;
|
||||
};
|
||||
|
||||
/* ADC peripheral interfaces. */
|
||||
/omit-if-no-ref/ adc0_chan0_gp45: periph-adc0-0 {
|
||||
pinmux = <&alt6_adc0_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan1_gp44: periph-adc0-1 {
|
||||
pinmux = <&alt6_adc1_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan2_gp43: periph-adc0-2 {
|
||||
pinmux = <&alt6_adc2_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan3_gp42: periph-adc0-3 {
|
||||
pinmux = <&alt6_adc3_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan4_gp41: periph-adc0-4 {
|
||||
pinmux = <&alt6_adc4_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan5_gp37: periph-adc0-5 {
|
||||
pinmux = <&altf_adc5_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan6_gp34: periph-adc0-6 {
|
||||
pinmux = <&altf_adc6_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan7_gpe1: periph-adc0-7 {
|
||||
pinmux = <&altf_adc7_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan8_gpf1: periph-adc0-8 {
|
||||
pinmux = <&altf_adc8_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan9_gpf0: periph-adc0-9 {
|
||||
pinmux = <&altf_adc9_sl>;
|
||||
};
|
||||
|
||||
/* PSL peripheral interfaces. */
|
||||
/omit-if-no-ref/ psl_in1_gpd2: periph-psl-in1 {
|
||||
pinmux = <&altd_npsl_in1_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ psl_in2_gp00: periph-psl-in2 {
|
||||
pinmux = <&altd_npsl_in2_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ psl_in3_gp01: periph-psl-in3 {
|
||||
pinmux = <&altd_psl_in3_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ psl_in4_gp02: periph-psl-in4 {
|
||||
pinmux = <&altd_psl_in4_sl>;
|
||||
};
|
||||
|
||||
/* UART peripheral interfaces */
|
||||
/omit-if-no-ref/ uart1_1_sin_sout_gp10_11: periph-uart1-1 {
|
||||
pinmux = <&alta_uart1_sl1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ uart1_2_sin_sout_gp64_65: periph-uart1-2 {
|
||||
pinmux = <&altc_uart1_sl2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ uart2_sin_sout_gp75_86: periph-uart2 {
|
||||
pinmux = <&alta_uart2_sl>;
|
||||
};
|
||||
};
|
428
dts/arm/nuvoton/npcx/npcx9/npcx9-pinctrl.dtsi
Normal file
428
dts/arm/nuvoton/npcx/npcx9/npcx9-pinctrl.dtsi
Normal file
|
@ -0,0 +1,428 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
/* Prebuild nodes for peripheral device's pin-muxing and pad properties */
|
||||
/* Host peripheral interfaces */
|
||||
/omit-if-no-ref/ espi_lpc_gp46_47_51_52_53_54_55_57: periph-lpc-espi {
|
||||
pinmux = <&alt1_no_lpc_espi>;
|
||||
};
|
||||
|
||||
/* I2C peripheral interfaces */
|
||||
/omit-if-no-ref/ i2c0_0_sda_scl_gpb4_b5: periph-i2c0-0 {
|
||||
pinmux = <&alt2_i2c0_0_sl>;
|
||||
periph-pupd = <0x00 0>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ i2c1_0_sda_scl_gp87_90: periph-i2c1-0 {
|
||||
pinmux = <&alt2_i2c1_0_sl>;
|
||||
periph-pupd = <0x00 2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ i2c2_0_sda_scl_gp91_92: periph-i2c2-0 {
|
||||
pinmux = <&alt2_i2c2_0_sl>;
|
||||
periph-pupd = <0x00 4>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ i2c3_0_sda_scl_gpd0_d1: periph-i2c3-0 {
|
||||
pinmux = <&alt2_i2c3_0_sl>;
|
||||
periph-pupd = <0x00 6>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ i2c4_1_sda_scl_gpf2_f3: periph-i2c4-1 {
|
||||
pinmux = <&alt6_i2c4_1_sl>;
|
||||
periph-pupd = <0x01 2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ i2c5_0_sda_scl_gp33_36: periph-i2c5-0 {
|
||||
pinmux = <&alt2_i2c5_0_sl>;
|
||||
periph-pupd = <0x00 5>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ i2c5_1_sda_scl_gpf4_f5: periph-i2c5-1 {
|
||||
pinmux = <&alt6_i2c5_1_sl>;
|
||||
periph-pupd = <0x01 1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ i2c6_0_sda_scl_gpc1_c2: periph-i2c6-0 {
|
||||
pinmux = <&alt2_i2c6_0_sl>;
|
||||
periph-pupd = <0x00 3>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ i2c6_1_sda_scl_gpe3_e4: periph-i2c6-1 {
|
||||
pinmux = <&alt6_i2c6_1_sl>;
|
||||
periph-pupd = <0x01 0>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ i2c7_0_sda_scl_gpb2_b3: periph-i2c7-0 {
|
||||
pinmux = <&alt2_i2c7_0_sl>;
|
||||
periph-pupd = <0x00 1>;
|
||||
};
|
||||
|
||||
/* PS2 peripheral interfaces */
|
||||
/omit-if-no-ref/ ps2_0_dat_clk_gp67_70: periph-ps2-0 {
|
||||
pinmux = <&alt3_ps2_0_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ ps2_1_dat_clk_gp62_63: periph-ps2-1 {
|
||||
pinmux = <&alt3_ps2_1_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ ps2_2_dat_clk_gp34_37: periph-ps2-2 {
|
||||
pinmux = <&alt3_ps2_2_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ ps2_3_2_dat_clk_gpa6_a7: periph-ps2-3-2 {
|
||||
pinmux = <&altc_ps2_3_sl2>;
|
||||
};
|
||||
|
||||
/* Tachometer peripheral interfaces */
|
||||
/omit-if-no-ref/ ta1_1_in_gp40: periph-ta1-1 {
|
||||
pinmux = <&alt3_ta1_sl1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ ta1_2_in_gp93: periph-ta1-2 {
|
||||
pinmux = <&altc_ta1_sl2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ ta2_1_in_gp73: periph-ta2-1 {
|
||||
pinmux = <&alt3_ta2_sl1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ ta2_2_in_gpa6: periph-ta2-2 {
|
||||
pinmux = <&altc_ta2_sl2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ tb1_1_in_gpa4: periph-tb1-1 {
|
||||
pinmux = <&alt3_tb1_sl1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ tb1_2_in_gpd3: periph-tb1-2 {
|
||||
pinmux = <&altc_tb1_sl2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ tb2_2_in_gpa7: periph-tb2-2 {
|
||||
pinmux = <&altc_tb2_sl2>;
|
||||
};
|
||||
|
||||
/* PWM peripheral interfaces */
|
||||
/omit-if-no-ref/ pwm0_gpc3: periph-pwm0 {
|
||||
pinmux = <&alt4_pwm0_sl>;
|
||||
drive-supported;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ pwm1_gpc2: periph-pwm1 {
|
||||
pinmux = <&alt4_pwm1_sl>;
|
||||
drive-supported;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ pwm2_gpc4: periph-pwm2 {
|
||||
pinmux = <&alt4_pwm2_sl>;
|
||||
drive-supported;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ pwm3_gp80: periph-pwm3 {
|
||||
pinmux = <&alt4_pwm3_sl>;
|
||||
drive-supported;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ pwm4_gpb6: periph-pwm4 {
|
||||
pinmux = <&alt4_pwm4_sl>;
|
||||
drive-supported;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ pwm5_gpb7: periph-pwm5 {
|
||||
pinmux = <&alt4_pwm5_sl>;
|
||||
drive-supported;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ pwm6_gpc0: periph-pwm6 {
|
||||
pinmux = <&alt4_pwm6_sl>;
|
||||
drive-supported;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ pwm7_gp60: periph-pwm7 {
|
||||
pinmux = <&alt4_pwm7_sl>;
|
||||
drive-supported;
|
||||
};
|
||||
|
||||
/* Keyboard peripheral interfaces. */
|
||||
/omit-if-no-ref/ ksi0_gp31: periph-kbscan-ksi0 {
|
||||
pinmux = <&alt7_no_ksi0_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ ksi1_gp30: periph-kbscan-ksi1 {
|
||||
pinmux = <&alt7_no_ksi1_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ ksi2_gp27: periph-kbscan-ksi2 {
|
||||
pinmux = <&alt7_no_ksi2_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ ksi3_gp26: periph-kbscan-ksi3 {
|
||||
pinmux = <&alt7_no_ksi3_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ ksi4_gp25: periph-kbscan-ksi4 {
|
||||
pinmux = <&alt7_no_ksi4_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ ksi5_gp24: periph-kbscan-ksi5 {
|
||||
pinmux = <&alt7_no_ksi5_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ ksi6_gp23: periph-kbscan-ksi6 {
|
||||
pinmux = <&alt7_no_ksi6_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ ksi7_gp22: periph-kbscan-ksi7 {
|
||||
pinmux = <&alt7_no_ksi7_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso00_gp21: periph-kbscan-kso00 {
|
||||
pinmux = <&alt8_no_kso00_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso01_gp20: periph-kbscan-kso01 {
|
||||
pinmux = <&alt8_no_kso01_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso02_gp17: periph-kbscan-kso02 {
|
||||
pinmux = <&alt8_no_kso02_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso03_gp16: periph-kbscan-kso03 {
|
||||
pinmux = <&alt8_no_kso03_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso04_gp15: periph-kbscan-kso04 {
|
||||
pinmux = <&alt8_no_kso04_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso05_gp14: periph-kbscan-kso05 {
|
||||
pinmux = <&alt8_no_kso05_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso06_gp13: periph-kbscan-kso06 {
|
||||
pinmux = <&alt8_no_kso06_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso07_gp12: periph-kbscan-kso07 {
|
||||
pinmux = <&alt8_no_kso07_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso08_gp11: periph-kbscan-kso08 {
|
||||
pinmux = <&alt9_no_kso08_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso09_gp10: periph-kbscan-kso09 {
|
||||
pinmux = <&alt9_no_kso09_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso10_gp07: periph-kbscan-kso10 {
|
||||
pinmux = <&alt9_no_kso10_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso11_gp06: periph-kbscan-kso11 {
|
||||
pinmux = <&alt9_no_kso11_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso12_gp05: periph-kbscan-kso12 {
|
||||
pinmux = <&alt9_no_kso12_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso13_gp04: periph-kbscan-kso13 {
|
||||
pinmux = <&alt9_no_kso13_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso14_gp82: periph-kbscan-kso14 {
|
||||
pinmux = <&alt9_no_kso14_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso15_gp83: periph-kbscan-kso15 {
|
||||
pinmux = <&alt9_no_kso15_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso16_gp03: periph-kbscan-kso16 {
|
||||
pinmux = <&alta_no_kso16_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ kso17_gpb1: periph-kbscan-kso17 {
|
||||
pinmux = <&alta_no_kso17_sl>;
|
||||
};
|
||||
|
||||
/* Miscellaneous peripheral interfaces */
|
||||
/omit-if-no-ref/ clk_32k_out_gp75: periph-clk-32k-out {
|
||||
pinmux = <&alta_32k_out_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ vcc1_rst_gp77: periph-vcc1-rst {
|
||||
pinmux = <&alta_no_vcc1_rst>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ peci_dat_gp81: periph-peci-dat {
|
||||
pinmux = <&alta_no_peci_en>;
|
||||
};
|
||||
|
||||
/* Host UART peripheral interfaces */
|
||||
/omit-if-no-ref/ huart_rxd_gp75: periph-host-uart-rxd {
|
||||
pinmux = <&altb_rxd_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ huart_txd_gp86: periph-host-uart-txd {
|
||||
pinmux = <&altb_txd_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ huart_rts_gp36: periph-host-uart-rts {
|
||||
pinmux = <&altb_rts_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ huart_cts_gp33: periph-host-uart-cts {
|
||||
pinmux = <&altb_cts_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ huart_ri_gp42: periph-host-uart-ri {
|
||||
pinmux = <&altb_ri_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ huart_dtr_bout_gpc7: periph-host-uart-dtr_bout {
|
||||
pinmux = <&altb_dtr_bout_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ huart_dcd_gpb3: periph-host-uart-dcd {
|
||||
pinmux = <&altb_dcd_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ huart_dsr_gpb2: periph-host-uart-dsr {
|
||||
pinmux = <&altb_dsr_sl>;
|
||||
};
|
||||
|
||||
/* SHI peripheral interfaces */
|
||||
/omit-if-no-ref/ shi_gp46_47_53_55: periph-shi {
|
||||
pinmux = <&altc_shi_sl>;
|
||||
periph-pupd = <0x01 4>;
|
||||
};
|
||||
|
||||
/* ADC peripheral interfaces. */
|
||||
/omit-if-no-ref/ adc0_chan0_gp45: periph-adc0-0 {
|
||||
pinmux = <&alt6_adc0_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan1_gp44: periph-adc0-1 {
|
||||
pinmux = <&alt6_adc1_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan2_gp43: periph-adc0-2 {
|
||||
pinmux = <&alt6_adc2_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan3_gp42: periph-adc0-3 {
|
||||
pinmux = <&alt6_adc3_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan4_gp41: periph-adc0-4 {
|
||||
pinmux = <&alt6_adc4_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan5_gp37: periph-adc0-5 {
|
||||
pinmux = <&altf_adc5_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan6_gp34: periph-adc0-6 {
|
||||
pinmux = <&altf_adc6_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan7_gpe1: periph-adc0-7 {
|
||||
pinmux = <&altf_adc7_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan8_gpf1: periph-adc0-8 {
|
||||
pinmux = <&altf_adc8_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan9_gpf0: periph-adc0-9 {
|
||||
pinmux = <&altf_adc9_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan10_gpe0: periph-adc0-10 {
|
||||
pinmux = <&altf_adc10_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ adc0_chan11_gpc7: periph-adc0-11 {
|
||||
pinmux = <&altf_adc11_sl>;
|
||||
};
|
||||
|
||||
/* PSL peripheral interfaces */
|
||||
/omit-if-no-ref/ psl_in1_gpd2: periph-psl-in1 {
|
||||
pinmux = <&altd_npsl_in1_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ psl_in2_gp00: periph-psl-in2 {
|
||||
pinmux = <&altd_npsl_in2_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ psl_in3_gp01: periph-psl-in3 {
|
||||
pinmux = <&altd_psl_in3_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ psl_in4_gp02: periph-psl-in4 {
|
||||
pinmux = <&altd_psl_in4_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ psl_gpo_gpd7: periph-psl-gpo {
|
||||
pinmux = <&altg_psl_gpo_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ psl_out_gp85: periph-psl-out {
|
||||
pinmux = <&altg_psl_out_sl>;
|
||||
};
|
||||
|
||||
/* I3C peripheral interfaces */
|
||||
/omit-if-no-ref/ i3c_sda_scl_gpe3_e4: periph-i3c {
|
||||
pinmux = <&alth_i3c_sl>;
|
||||
};
|
||||
|
||||
/* UART peripheral interfaces */
|
||||
/omit-if-no-ref/ uart1_1_sin_gp10: periph-uart1-1-sin {
|
||||
pinmux = <&altj_cr_sin1_sl1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ uart1_1_sout_gp11: periph-uart1-1-sout {
|
||||
pinmux = <&altj_cr_sout1_sl1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ uart1_2_sin_gp64: periph-uart1-2-sin {
|
||||
pinmux = <&altj_cr_sin1_sl2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ uart1_2_sout_gp65: periph-uart1-2-sout {
|
||||
pinmux = <&altj_cr_sout1_sl2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ uart2_sin_gp75: periph-uart2-sin {
|
||||
pinmux = <&altj_cr_sin2_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ uart2_sout_gp86: periph-uart2-sout {
|
||||
pinmux = <&altj_cr_sout2_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ uart3_sin_gpd4: periph-uart3-sin {
|
||||
pinmux = <&altj_cr_sin3_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ uart3_sout_gpd6: periph-uart3-sout {
|
||||
pinmux = <&altj_cr_sout3_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ uart4_sin_gpb1: periph-uart4-sin {
|
||||
pinmux = <&alte_cr_sin4_sl>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ uart4_sout_gp35: periph-uart4-sout {
|
||||
pinmux = <&alte_cr_sout4_sl>;
|
||||
};
|
||||
};
|
77
dts/bindings/pinctrl/nuvoton,npcx-pinctrl.yaml
Normal file
77
dts/bindings/pinctrl/nuvoton,npcx-pinctrl.yaml
Normal file
|
@ -0,0 +1,77 @@
|
|||
# Copyright (c) 2022 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
The Nuvoton pin controller is a singleton node responsible for controlling
|
||||
pin function selection and pin properties. For example, you can use these
|
||||
nodes to select peripheral pin functions.
|
||||
|
||||
Here is a list of supported standard pin properties:
|
||||
- bias-pull-down: Enable pull-down resistor.
|
||||
- bias-pull-up: Enable pull-up resistor.
|
||||
- drive-open-drain: Output driver is open-drain.
|
||||
|
||||
Custom pin properties for npcx series are available also:
|
||||
- pinmux-locked: Lock pinmux configuration for peripheral device
|
||||
- pinmux-gpio: Inverse pinmux back to gpio
|
||||
|
||||
An example for NPCX7 family, include the chip level pinctrl DTSI file in the
|
||||
board level DTS:
|
||||
|
||||
#include <nuvoton/npcx/npcx7/npcx7-pinctrl.dtsi>
|
||||
|
||||
We want to use the I2C0_0 port of the NPCX7M6FB controller and enable the
|
||||
internal 3.3V pull-up if its i2c frequency won't exceed 400kHz.
|
||||
|
||||
To change a pin's pinctrl default properties, add a reference to the
|
||||
pin in the board's DTS file and set the properties as below:
|
||||
|
||||
&i2c0_0_sda_scl_gpb4_b5 {
|
||||
bias-pull-up; /* Enable internal pull-up for i2c0_0 */
|
||||
pinmux-locked; /* Lock pinmuxing */
|
||||
};
|
||||
|
||||
&i2c0_0 {
|
||||
pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
|
||||
pinctrl-names = "default";
|
||||
}
|
||||
|
||||
compatible: "nuvoton,npcx-pinctrl"
|
||||
|
||||
include:
|
||||
- name: base.yaml
|
||||
- name: pincfg-node.yaml
|
||||
child-binding:
|
||||
property-allowlist:
|
||||
- bias-pull-down
|
||||
- bias-pull-up
|
||||
- drive-open-drain
|
||||
|
||||
child-binding:
|
||||
description: |
|
||||
NPCX pin controller pin configuration nodes
|
||||
properties:
|
||||
pinmux:
|
||||
type: phandle
|
||||
required: false
|
||||
description: Configurations of pinmux selection
|
||||
periph-pupd:
|
||||
type: array
|
||||
required: false
|
||||
description: |
|
||||
A map to PUPD_ENn register/bit that enable pull-up/down of NPCX peripheral devices.
|
||||
Please don't overwrite this property in the board-level DT driver.
|
||||
drive-supported:
|
||||
required: false
|
||||
type: boolean
|
||||
description: |
|
||||
It indicates the pad's drive mode is selectable. So far, only PWM's pad has this
|
||||
property in npcx series. Please don't overwrite it in the board-level DT driver.
|
||||
pinmux-locked:
|
||||
required: false
|
||||
type: boolean
|
||||
description: Lock pinmux selection
|
||||
pinmux-gpio:
|
||||
required: false
|
||||
type: boolean
|
||||
description: Inverse pinmux selection to GPIO
|
180
soc/arm/nuvoton_npcx/common/pinctrl_soc.h
Normal file
180
soc/arm/nuvoton_npcx/common/pinctrl_soc.h
Normal file
|
@ -0,0 +1,180 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_PINCTRL_SOC_H_
|
||||
#define _NUVOTON_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/sys/util_macro.h>
|
||||
#include <zephyr/types.h>
|
||||
|
||||
/**
|
||||
* @brief Pinctrl node types in NPCX series
|
||||
*/
|
||||
enum npcx_pinctrl_type {
|
||||
NPCX_PINCTRL_TYPE_PERIPH,
|
||||
NPCX_PINCTRL_TYPE_RESERVED,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Suppoerted peripheral device configuration type in NPCX series
|
||||
*/
|
||||
enum npcx_periph_type {
|
||||
NPCX_PINCTRL_TYPE_PERIPH_PINMUX,
|
||||
NPCX_PINCTRL_TYPE_PERIPH_PUPD,
|
||||
NPCX_PINCTRL_TYPE_PERIPH_DRIVE,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Suppoerted IO bias type in NPCX series
|
||||
*/
|
||||
enum npcx_io_bias_type {
|
||||
NPCX_BIAS_TYPE_NONE,
|
||||
NPCX_BIAS_TYPE_PULL_DOWN,
|
||||
NPCX_BIAS_TYPE_PULL_UP,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Suppoerted IO drive type in NPCX series
|
||||
*/
|
||||
enum npcx_io_drive_type {
|
||||
NPCX_DRIVE_TYPE_PUSH_PULL,
|
||||
NPCX_DRIVE_TYPE_OPEN_DRAIN,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief NPCX peripheral device configuration structure
|
||||
*
|
||||
* Used to indicate the peripheral device's corresponding register/bit for
|
||||
* pin-muxing, pull-up/down and so on.
|
||||
*/
|
||||
struct npcx_periph {
|
||||
/** Related register group for peripheral device. */
|
||||
uint16_t group: 8;
|
||||
/** Related register bit for peripheral device. */
|
||||
uint16_t bit: 3;
|
||||
/** The polarity for peripheral device functionality. */
|
||||
bool inverted: 1;
|
||||
/** The type of peripheral device configuration. */
|
||||
enum npcx_periph_type type: 2;
|
||||
/** Reserved field. */
|
||||
uint16_t reserved: 2;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* @brief Type for NPCX pin configuration. Please make sure the size of this
|
||||
* structure is 4 bytes in case the impact of ROM usage.
|
||||
*/
|
||||
struct npcx_pinctrl {
|
||||
union {
|
||||
struct npcx_periph periph;
|
||||
uint16_t cfg_word;
|
||||
} cfg;
|
||||
struct {
|
||||
/** Indicates the current pinctrl type. */
|
||||
enum npcx_pinctrl_type type :2;
|
||||
/** Properties used for pinmuxing. */
|
||||
bool pinmux_lock :1;
|
||||
bool pinmux_gpio :1;
|
||||
/** Properties used for io-pad. */
|
||||
enum npcx_io_bias_type io_bias_type :2;
|
||||
enum npcx_io_drive_type io_drive_type :1;
|
||||
uint16_t reserved :1;
|
||||
} flags;
|
||||
} __packed;
|
||||
|
||||
typedef struct npcx_pinctrl pinctrl_soc_pin_t;
|
||||
|
||||
/** Helper macros for NPCX pinctrl configurations. */
|
||||
#define Z_PINCTRL_NPCX_BIAS_TYPE(node_id) \
|
||||
COND_CODE_1(DT_PROP(node_id, bias_pull_up), (NPCX_BIAS_TYPE_PULL_UP), \
|
||||
(COND_CODE_1(DT_PROP(node_id, bias_pull_down), \
|
||||
(NPCX_BIAS_TYPE_PULL_DOWN), (NPCX_BIAS_TYPE_NONE))))
|
||||
|
||||
#define Z_PINCTRL_NPCX_DRIVE_TYPE(node_id) \
|
||||
COND_CODE_1(DT_PROP(node_id, drive_open_drain), \
|
||||
(NPCX_DRIVE_TYPE_OPEN_DRAIN), (NPCX_DRIVE_TYPE_PUSH_PULL))
|
||||
|
||||
#define Z_PINCTRL_NPCX_HAS_PUPD_PROP(node_id) \
|
||||
UTIL_OR(DT_PROP(node_id, bias_pull_down), \
|
||||
DT_PROP(node_id, bias_pull_up))
|
||||
|
||||
#define Z_PINCTRL_NPCX_HAS_DRIVE_PROP(node_id) \
|
||||
UTIL_AND(DT_PROP(node_id, drive_open_drain), \
|
||||
DT_PROP(node_id, drive_supported))
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize a periphral pinmux configuration.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name for pinmux configuration. (i.e. 'pinmux')
|
||||
*/
|
||||
#define Z_PINCTRL_NPCX_PERIPH_PINMUX_INIT(node_id, prop) \
|
||||
{ \
|
||||
.flags.type = NPCX_PINCTRL_TYPE_PERIPH, \
|
||||
.flags.pinmux_lock = DT_PROP(node_id, pinmux_locked), \
|
||||
.flags.pinmux_gpio = DT_PROP(node_id, pinmux_gpio), \
|
||||
.cfg.periph.type = NPCX_PINCTRL_TYPE_PERIPH_PINMUX, \
|
||||
.cfg.periph.group = DT_PHA(DT_PROP(node_id, prop), alts, group), \
|
||||
.cfg.periph.bit = DT_PHA(DT_PROP(node_id, prop), alts, bit), \
|
||||
.cfg.periph.inverted = DT_PHA(DT_PROP(node_id, prop), alts, inv), \
|
||||
},
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize a periphral pull-up/down configuration.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name for pull-up/down configuration. (i.e. 'periph-pupd')
|
||||
*/
|
||||
#define Z_PINCTRL_NPCX_PERIPH_PUPD_INIT(node_id, prop) \
|
||||
{ \
|
||||
.flags.type = NPCX_PINCTRL_TYPE_PERIPH, \
|
||||
.flags.io_bias_type = Z_PINCTRL_NPCX_BIAS_TYPE(node_id), \
|
||||
.cfg.periph.type = NPCX_PINCTRL_TYPE_PERIPH_PUPD, \
|
||||
.cfg.periph.group = DT_PROP_BY_IDX(node_id, prop, 0), \
|
||||
.cfg.periph.bit = DT_PROP_BY_IDX(node_id, prop, 1), \
|
||||
},
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize a periphral drive mode configuration.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
*/
|
||||
#define Z_PINCTRL_NPCX_PERIPH_DRIVE_INIT(node_id) \
|
||||
{ \
|
||||
.flags.type = NPCX_PINCTRL_TYPE_PERIPH, \
|
||||
.flags.io_drive_type = Z_PINCTRL_NPCX_DRIVE_TYPE(node_id), \
|
||||
.cfg.periph.type = NPCX_PINCTRL_TYPE_PERIPH_DRIVE, \
|
||||
},
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize all peripheral confiurations for each pin.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Pinctrl state property name. (i.e. 'pinctrl-0/1/2')
|
||||
* @param idx Property entry index.
|
||||
*/
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
|
||||
COND_CODE_1(Z_PINCTRL_NPCX_HAS_DRIVE_PROP(DT_PROP_BY_IDX(node_id, prop, idx)), \
|
||||
(Z_PINCTRL_NPCX_PERIPH_DRIVE_INIT( \
|
||||
DT_PROP_BY_IDX(node_id, prop, idx))), ()) \
|
||||
COND_CODE_1(Z_PINCTRL_NPCX_HAS_PUPD_PROP(DT_PROP_BY_IDX(node_id, prop, idx)), \
|
||||
(Z_PINCTRL_NPCX_PERIPH_PUPD_INIT( \
|
||||
DT_PROP_BY_IDX(node_id, prop, idx), periph_pupd)), ()) \
|
||||
COND_CODE_1(DT_NODE_HAS_PROP(DT_PROP_BY_IDX(node_id, prop, idx), pinmux), \
|
||||
(Z_PINCTRL_NPCX_PERIPH_PINMUX_INIT( \
|
||||
DT_PROP_BY_IDX(node_id, prop, idx), pinmux)), ())
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize state pins contained in a given property.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name describing state pins.
|
||||
*/
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT)}
|
||||
|
||||
#endif /* _NUVOTON_PINCTRL_SOC_H_ */
|
|
@ -192,6 +192,16 @@ static inline uint32_t npcx_devalt_offset(uint32_t alt_no)
|
|||
return 0x010 + alt_no;
|
||||
}
|
||||
|
||||
static inline uint32_t npcx_devalt_lk_offset(uint32_t alt_lk_no)
|
||||
{
|
||||
return 0x210 + alt_lk_no;
|
||||
}
|
||||
|
||||
static inline uint32_t npcx_pupd_en_offset(uint32_t pupd_en_no)
|
||||
{
|
||||
return 0x28 + pupd_en_no;
|
||||
}
|
||||
|
||||
static inline uint32_t npcx_lv_gpio_ctl_offset(uint32_t ctl_no)
|
||||
{
|
||||
if (ctl_no < 5) {
|
||||
|
@ -204,6 +214,10 @@ static inline uint32_t npcx_lv_gpio_ctl_offset(uint32_t ctl_no)
|
|||
/* Macro functions for SCFG multi-registers */
|
||||
#define NPCX_DEVALT(base, n) (*(volatile uint8_t *)(base + \
|
||||
npcx_devalt_offset(n)))
|
||||
#define NPCX_DEVALT_LK(base, n) (*(volatile uint8_t *)(base + \
|
||||
npcx_devalt_lk_offset(n)))
|
||||
#define NPCX_PUPD_EN(base, n) (*(volatile uint8_t *)(base + \
|
||||
npcx_pupd_en_offset(n)))
|
||||
#define NPCX_LV_GPIO_CTL(base, n) (*(volatile uint8_t *)(base + \
|
||||
npcx_lv_gpio_ctl_offset(n)))
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue