soc: Add support for MXRT595
Add support for MXRT595 Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit is contained in:
parent
eb7d95cd48
commit
a62ff8906d
13 changed files with 747 additions and 1 deletions
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@ -1,4 +1,4 @@
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# Copyright (c) 2017-2020, NXP
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# Copyright (c) 2017-2021, NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_IMX
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@ -14,6 +14,7 @@ config SOC_FAMILY
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source "soc/arm/nxp_imx/*/Kconfig.soc"
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config SOC_PART_NUMBER
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default SOC_PART_NUMBER_IMX_RT5XX if SOC_SERIES_IMX_RT5XX
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default SOC_PART_NUMBER_IMX_RT6XX if SOC_SERIES_IMX_RT6XX
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default SOC_PART_NUMBER_IMX_RT if SOC_SERIES_IMX_RT
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default SOC_PART_NUMBER_IMX_6X_M4 if SOC_SERIES_IMX_6X_M4
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25
soc/arm/nxp_imx/rt5xx/CMakeLists.txt
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25
soc/arm/nxp_imx/rt5xx/CMakeLists.txt
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#
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# Copyright (c) 2022, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_compile_definitions(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE)
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zephyr_sources(
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soc.c
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flash_clock_setup.c
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)
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zephyr_library_include_directories(
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${ZEPHYR_BASE}/kernel/include
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${ZEPHYR_BASE}/arch/${ARCH}/include
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)
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zephyr_linker_sources_ifdef(CONFIG_NXP_IMX_RT5XX_BOOT_HEADER
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ROM_START SORT_KEY 0 boot_header.ld)
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zephyr_linker_sources(
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RWDATA quick_access.ld)
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zephyr_code_relocate(flash_clock_setup.c SRAM)
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41
soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.mimxrt595_cm33
Normal file
41
soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.mimxrt595_cm33
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# NXP MIMXRT5XX platform configuration options
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# Copyright (c) 2022, NXP
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# SPDX-License-Identifier: Apache-2.0
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if SOC_MIMXRT595S_CM33
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config SOC
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default "mimxrt595s_cm33"
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config PINMUX_MCUX_LPC
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default y
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depends on PINMUX
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config GPIO_MCUX_LPC
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default y
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depends on GPIO
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config UART_MCUX_FLEXCOMM
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default y if HAS_MCUX_FLEXCOMM
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depends on SERIAL
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config CLOCK_CONTROL_MCUX_SYSCON
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default y if HAS_MCUX_SYSCON
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depends on CLOCK_CONTROL
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if MCUX_OS_TIMER
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 1000000
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endif # MCUX_OS_TIMER
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if CORTEX_M_SYSTICK
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 250105263
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endif # CORTEX_M_SYSTICK
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endif # SOC_MIMXRT685S_CM33
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45
soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.series
Normal file
45
soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.series
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# i.MX RT5XX series configuration options
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# Copyright (c) 2022, NXP
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_IMX_RT5XX
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config SOC_SERIES
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default "rt5xx"
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config ROM_START_OFFSET
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default 0x1200 if NXP_IMX_RT5XX_BOOT_HEADER
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config NUM_IRQS
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default 74
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#
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# The base address of the external flash comes from the FLEXSPI base
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# address. The size of the flash is defined by what is populated and
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# described in the board devicetree file.
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#
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config FLASH_BASE_ADDRESS
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default $(dt_node_reg_addr_hex,/soc/spi@134000,1)
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#
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# MBEDTLS is larger but much faster than TinyCrypt so choose wisely
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#
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config MBEDTLS
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#config TINYCRYPT
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default y if CSPRING_ENABLED
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depends on ENTROPY_GENERATOR
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if MBEDTLS
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#
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# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than
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# what the ztest_thread_stack defaults to.
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#
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config TEST_EXTRA_STACKSIZE
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int
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default 1024
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endif # MBEDTLS
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source "soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.mimxrt5*"
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endif # SOC_SERIES_MIMXRT6XX
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14
soc/arm/nxp_imx/rt5xx/Kconfig.series
Normal file
14
soc/arm/nxp_imx/rt5xx/Kconfig.series
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# i.MX RT5XX Series
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# Copyright (c) 2022, NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_IMX_RT5XX
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bool "i.MX RT5XX Series Family MCU"
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select ARM
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select CPU_CORTEX_M33
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select CPU_CORTEX_M_HAS_DWT
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select SOC_FAMILY_IMX
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select CLOCK_CONTROL
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help
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Enable support for i.MX RT5XX Series MCU series
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98
soc/arm/nxp_imx/rt5xx/Kconfig.soc
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98
soc/arm/nxp_imx/rt5xx/Kconfig.soc
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# i.MX RT5XX Series
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# Copyright (c) 2022, NXP
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "i.MX RT5XX Series MCU Selection"
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depends on SOC_SERIES_IMX_RT5XX
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config SOC_MIMXRT595S_CM33
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bool "SOC_MIMXRT595S M33"
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select PLATFORM_SPECIFIC_INIT
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select ARMV8_M_DSP
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select ARM_TRUSTZONE_M
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select CPU_CORTEX_M_HAS_SYSTICK
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select HAS_MCUX
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select HAS_MCUX_SYSCON
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select HAS_MCUX_FLEXCOMM
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select HAS_MCUX_FLEXSPI
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select HAS_MCUX_CACHE
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select HAS_MCUX_LPC_DMA
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select HAS_MCUX_LPADC
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select HAS_MCUX_OS_TIMER
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select HAS_MCUX_LPC_RTC
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select HAS_MCUX_TRNG
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select HAS_MCUX_SCTIMER
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select HAS_MCUX_USDHC1
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select HAS_MCUX_USDHC2
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select HAS_MCUX_USB_LPCIP3511
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select USB_DEDICATED_MEMORY if USB_DEVICE_DRIVER
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select HAS_MCUX_CTIMER
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endchoice
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if SOC_SERIES_IMX_RT5XX
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config SOC_PART_NUMBER_MIMXRT533SFFOC
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bool
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config SOC_PART_NUMBER_MIMXRT555SFFOC
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bool
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config SOC_PART_NUMBER_MIMXRT595SFFOC
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bool
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config SOC_PART_NUMBER_MIMXRT533SFAWCR
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bool
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config SOC_PART_NUMBER_MIMXRT555SFAWCR
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bool
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config SOC_PART_NUMBER_MIMXRT595SFAWCR
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bool
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config SOC_PART_NUMBER_IMX_RT5XX
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string
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default "MIMXRT533SFAWCR" if SOC_PART_NUMBER_MIMXRT533SFAWCR
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default "MIMXRT555SFAWCR" if SOC_PART_NUMBER_MIMXRT555SFAWCR
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default "MIMXRT595SFAWCR" if SOC_PART_NUMBER_MIMXRT595SFAWCR
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default "MIMXRT533SFFOC" if SOC_PART_NUMBER_MIMXRT533SFFOC
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default "MIMXRT555SFFOC" if SOC_PART_NUMBER_MIMXRT555SFFOC
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default "MIMXRT595SFFOC" if SOC_PART_NUMBER_MIMXRT595SFFOC
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help
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This string holds the full part number of the SoC. It is a hidden
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option that you should not set directly. The part number selection
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choice defines the default value for this string.
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menuconfig NXP_IMX_RT5XX_BOOT_HEADER
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bool "Enable the boot header"
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depends on !BOOTLOADER_MCUBOOT
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help
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Enable data structures required by the boot ROM to boot the
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application from an external flash device.
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if NXP_IMX_RT5XX_BOOT_HEADER
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config FLASH_CONFIG_OFFSET
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hex "Flash config data offset"
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default 0x400
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help
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The flash config offset provides the boot ROM with the on-board
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flash type and parameters. The boot ROM requires a fixed flash conifg
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offset for FlexSPI device.
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config IMAGE_VECTOR_TABLE_OFFSET
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hex "Image vector table offset"
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default 0x1000
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help
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The Image Vector Table (IVT) provides the boot ROM with pointers to
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the application entry point and device configuration data. The boot
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ROM requires a fixed IVT offset for each type of boot device.
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endif # NXP_IMX_RT5XX_BOOT_HEADER
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endif # SOC_SERIES_IMX_RT5XX
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10
soc/arm/nxp_imx/rt5xx/boot_header.ld
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10
soc/arm/nxp_imx/rt5xx/boot_header.ld
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/*
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* Copyright (c) 2022 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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. = CONFIG_FLASH_CONFIG_OFFSET;
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KEEP(*(.flash_conf))
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. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;
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KEEP(*(.boot_hdr.ivt))
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145
soc/arm/nxp_imx/rt5xx/flash_clock_setup.c
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145
soc/arm/nxp_imx/rt5xx/flash_clock_setup.c
Normal file
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/*
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* Copyright (c) 2022, NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "fsl_power.h"
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#include "flash_clock_setup.h"
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#define FLEXSPI_DLL_LOCK_RETRY (10)
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static void flash_deinit(FLEXSPI_Type *base)
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{
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/* Enable FLEXSPI clock again */
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CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK;
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/* Enable FLEXSPI module */
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base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
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/* Wait until FLEXSPI is not busy */
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while (!((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) &&
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(base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) {
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}
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/* Disable module during the reset procedure */
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base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
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}
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static void flash_init(FLEXSPI_Type *base)
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{
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uint32_t status;
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uint32_t lastStatus;
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uint32_t retry;
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/* If serial root clock is >= 100 MHz, DLLEN set to 1, OVRDEN set to 0,
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* then SLVDLYTARGET setting of 0x0 is recommended.
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*/
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base->DLLCR[0] = 0x1U;
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/* Enable FLEXSPI module */
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base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
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base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
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while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) {
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}
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/* Need to wait DLL locked if DLL enabled */
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if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK)) {
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lastStatus = base->STS2;
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retry = FLEXSPI_DLL_LOCK_RETRY;
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/* Wait slave delay line locked and slave reference delay line locked. */
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do {
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status = base->STS2;
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if ((status & (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) ==
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(FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) {
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/* Locked */
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retry = 100;
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break;
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} else if (status == lastStatus) {
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/* Same delay cell number in calibration */
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retry--;
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} else {
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retry = FLEXSPI_DLL_LOCK_RETRY;
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lastStatus = status;
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}
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} while (retry > 0);
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/* According to ERR011377, need to delay at least 100 NOPs to ensure
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* the DLL is locked.
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*/
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for (; retry > 0U; retry--) {
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__NOP();
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}
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}
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}
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/*
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* flexspi_set_clock run in RAM used to configure FlexSPI clock source and divider
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* when XIP.
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*/
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void flexspi_setup_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider)
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{
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if (base == FLEXSPI0) {
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if ((CLKCTL0->FLEXSPI0FCLKSEL != CLKCTL0_FLEXSPI0FCLKSEL_SEL(src)) ||
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((CLKCTL0->FLEXSPI0FCLKDIV & CLKCTL0_FLEXSPI0FCLKDIV_DIV_MASK) !=
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(divider - 1))) {
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/* Always deinit FLEXSPI and init FLEXSPI for the flash to make sure the
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* flash works correctly after the FLEXSPI root clock changed as the
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* default FLEXSPI configuration may does not work for the new root
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* clock frequency.
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*/
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flash_deinit(base);
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/* Disable clock before changing clock source */
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CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI0_OTFAD_CLK_MASK;
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/* Update flexspi clock. */
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CLKCTL0->FLEXSPI0FCLKSEL = CLKCTL0_FLEXSPI0FCLKSEL_SEL(src);
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/* Reset the divider counter */
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CLKCTL0->FLEXSPI0FCLKDIV |= CLKCTL0_FLEXSPI0FCLKDIV_RESET_MASK;
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CLKCTL0->FLEXSPI0FCLKDIV = CLKCTL0_FLEXSPI0FCLKDIV_DIV(divider - 1);
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while ((CLKCTL0->FLEXSPI0FCLKDIV) & CLKCTL0_FLEXSPI0FCLKDIV_REQFLAG_MASK) {
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}
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/* Enable FLEXSPI clock again */
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CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK;
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flash_init(base);
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}
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} else if (base == FLEXSPI1) {
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if ((CLKCTL0->FLEXSPI1FCLKSEL != CLKCTL0_FLEXSPI1FCLKSEL_SEL(src)) ||
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((CLKCTL0->FLEXSPI1FCLKDIV & CLKCTL0_FLEXSPI1FCLKDIV_DIV_MASK) !=
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(divider - 1))) {
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/* Always deinit FLEXSPI and init FLEXSPI for the flash to make sure the
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* flash works correctly after the FLEXSPI root clock changed as the
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* default FLEXSPI configuration may does not work for the new root
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* clock frequency.
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*/
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flash_deinit(base);
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/* Disable clock before changing clock source */
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CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI1_CLK_MASK;
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/* Update flexspi clock. */
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CLKCTL0->FLEXSPI1FCLKSEL = CLKCTL0_FLEXSPI1FCLKSEL_SEL(src);
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/* Reset the divider counter */
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CLKCTL0->FLEXSPI1FCLKDIV |= CLKCTL0_FLEXSPI1FCLKDIV_RESET_MASK;
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CLKCTL0->FLEXSPI1FCLKDIV = CLKCTL0_FLEXSPI1FCLKDIV_DIV(divider - 1);
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while ((CLKCTL0->FLEXSPI1FCLKDIV) & CLKCTL0_FLEXSPI1FCLKDIV_REQFLAG_MASK) {
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}
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/* Enable FLEXSPI clock again */
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CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_MASK;
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flash_init(base);
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}
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} else {
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return;
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}
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}
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/* This function is used to change FlexSPI clock to a stable source before clock
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* sources(Such as PLL and Main clock) updating in case XIP (execute code on
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* FLEXSPI memory.)
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*/
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void flexspi_clock_safe_config(void)
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{
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/* Move FLEXSPI clock source from main clock to FRO192M / 2 to avoid instruction/data
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* fetch issue in XIP when updating PLL and main clock.
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*/
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flexspi_setup_clock(FLEXSPI0, 3U, 2U);
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}
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15
soc/arm/nxp_imx/rt5xx/flash_clock_setup.h
Normal file
15
soc/arm/nxp_imx/rt5xx/flash_clock_setup.h
Normal file
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/*
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* Copyright (c) 2022, NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _FLASH_CLOCK_SETUP_H_
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#define _FLASH_CLOCK_SETUP_H_
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#include "fsl_common.h"
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void flexspi_clock_safe_config(void);
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void flexspi_setup_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider);
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#endif /* _FLASH_CLOCK_SETUP_H_ */
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12
soc/arm/nxp_imx/rt5xx/linker.ld
Normal file
12
soc/arm/nxp_imx/rt5xx/linker.ld
Normal file
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/*
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* Copyright (c) 2021, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Linker command/script file
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*
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* This is the linker script for both standard images and XIP images.
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*/
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#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>
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9
soc/arm/nxp_imx/rt5xx/quick_access.ld
Normal file
9
soc/arm/nxp_imx/rt5xx/quick_access.ld
Normal file
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/*
|
||||
* Copyright (c) 2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(CodeQuickAccess))
|
||||
KEEP(*(DataQuickAccess))
|
256
soc/arm/nxp_imx/rt5xx/soc.c
Normal file
256
soc/arm/nxp_imx/rt5xx/soc.c
Normal file
|
@ -0,0 +1,256 @@
|
|||
/*
|
||||
* Copyright (c) 2022, NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief System/hardware module for NXP RT5XX platform
|
||||
*
|
||||
* This module provides routines to initialize and support board-level
|
||||
* hardware for the RT5XX platforms.
|
||||
*/
|
||||
|
||||
#include <init.h>
|
||||
#include <soc.h>
|
||||
#include "flash_clock_setup.h"
|
||||
#include "fsl_power.h"
|
||||
#include "fsl_clock.h"
|
||||
|
||||
/* Board System oscillator settling time in us */
|
||||
#define BOARD_SYSOSC_SETTLING_US 100U
|
||||
/* Board xtal frequency in Hz */
|
||||
#define BOARD_XTAL_SYS_CLK_HZ 24000000U
|
||||
/* Core clock frequency: 198000000Hz */
|
||||
#define CLOCK_INIT_CORE_CLOCK 198000000U
|
||||
|
||||
const clock_sys_pll_config_t g_sysPllConfig_clock_init = {
|
||||
/* OSC clock */
|
||||
.sys_pll_src = kCLOCK_SysPllXtalIn,
|
||||
/* Numerator of the SYSPLL0 fractional loop divider is 0 */
|
||||
.numerator = 0,
|
||||
/* Denominator of the SYSPLL0 fractional loop divider is 1 */
|
||||
.denominator = 1,
|
||||
/* Divide by 22 */
|
||||
.sys_pll_mult = kCLOCK_SysPllMult22
|
||||
};
|
||||
|
||||
const clock_audio_pll_config_t g_audioPllConfig_clock_init = {
|
||||
/* OSC clock */
|
||||
.audio_pll_src = kCLOCK_AudioPllXtalIn,
|
||||
/* Numerator of the Audio PLL fractional loop divider is 0 */
|
||||
.numerator = 5040,
|
||||
/* Denominator of the Audio PLL fractional loop divider is 1 */
|
||||
.denominator = 27000,
|
||||
/* Divide by 22 */
|
||||
.audio_pll_mult = kCLOCK_AudioPllMult22
|
||||
};
|
||||
|
||||
const clock_frg_clk_config_t g_frg0Config_clock_init = {
|
||||
.num = 0,
|
||||
.sfg_clock_src = kCLOCK_FrgPllDiv,
|
||||
.divider = 255U,
|
||||
.mult = 0
|
||||
};
|
||||
|
||||
const clock_frg_clk_config_t g_frg12Config_clock_init = {
|
||||
.num = 12,
|
||||
.sfg_clock_src = kCLOCK_FrgMainClk,
|
||||
.divider = 255U,
|
||||
.mult = 167
|
||||
};
|
||||
|
||||
/* System clock frequency. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
#ifdef CONFIG_NXP_IMX_RT5XX_BOOT_HEADER
|
||||
extern char z_main_stack[];
|
||||
extern char _flash_used[];
|
||||
|
||||
extern void z_arm_reset(void);
|
||||
extern void z_arm_nmi(void);
|
||||
extern void z_arm_hard_fault(void);
|
||||
extern void z_arm_mpu_fault(void);
|
||||
extern void z_arm_bus_fault(void);
|
||||
extern void z_arm_usage_fault(void);
|
||||
extern void z_arm_secure_fault(void);
|
||||
extern void z_arm_svc(void);
|
||||
extern void z_arm_debug_monitor(void);
|
||||
extern void z_arm_pendsv(void);
|
||||
extern void sys_clock_isr(void);
|
||||
extern void z_arm_exc_spurious(void);
|
||||
|
||||
__imx_boot_ivt_section void (* const image_vector_table[])(void) = {
|
||||
(void (*)())(z_main_stack + CONFIG_MAIN_STACK_SIZE), /* 0x00 */
|
||||
z_arm_reset, /* 0x04 */
|
||||
z_arm_nmi, /* 0x08 */
|
||||
z_arm_hard_fault, /* 0x0C */
|
||||
z_arm_mpu_fault, /* 0x10 */
|
||||
z_arm_bus_fault, /* 0x14 */
|
||||
z_arm_usage_fault, /* 0x18 */
|
||||
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
|
||||
z_arm_secure_fault, /* 0x1C */
|
||||
#else
|
||||
z_arm_exc_spurious,
|
||||
#endif /* CONFIG_ARM_SECURE_FIRMWARE */
|
||||
(void (*)())_flash_used, /* 0x20, imageLength. */
|
||||
0, /* 0x24, imageType (Plain Image) */
|
||||
0, /* 0x28, authBlockOffset/crcChecksum */
|
||||
z_arm_svc, /* 0x2C */
|
||||
z_arm_debug_monitor, /* 0x30 */
|
||||
(void (*)())image_vector_table, /* 0x34, imageLoadAddress. */
|
||||
z_arm_pendsv, /* 0x38 */
|
||||
#if defined(CONFIG_SYS_CLOCK_EXISTS) && \
|
||||
defined(CONFIG_CORTEX_M_SYSTICK_INSTALL_ISR)
|
||||
sys_clock_isr, /* 0x3C */
|
||||
#else
|
||||
z_arm_exc_spurious,
|
||||
#endif
|
||||
};
|
||||
#endif /* CONFIG_NXP_IMX_RT5XX_BOOT_HEADER */
|
||||
|
||||
void z_arm_platform_init(void)
|
||||
{
|
||||
/* This is provided by the SDK */
|
||||
SystemInit();
|
||||
}
|
||||
|
||||
void clock_init(void)
|
||||
{
|
||||
/* Configure LPOSC 1M */
|
||||
/* Power on LPOSC (1MHz) */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_LPOSC);
|
||||
/* Wait until LPOSC stable */
|
||||
CLOCK_EnableLpOscClk();
|
||||
|
||||
/* Configure FRO clock source */
|
||||
/* Power on FRO (192MHz or 96MHz) */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_FFRO);
|
||||
/* FRO_DIV1 is always enabled and used as Main clock during PLL update. */
|
||||
/* Enable all FRO outputs */
|
||||
CLOCK_EnableFroClk(kCLOCK_FroAllOutEn);
|
||||
|
||||
/*
|
||||
* Call function flexspi_clock_safe_config() to move FlexSPI clock to a stable
|
||||
* clock source to avoid instruction/data fetch issue when updating PLL and Main
|
||||
* clock if XIP(execute code on FLEXSPI memory).
|
||||
*/
|
||||
flexspi_clock_safe_config();
|
||||
|
||||
/* Let CPU run on FRO with divider 2 for safe switching. */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2);
|
||||
CLOCK_AttachClk(kFRO_DIV1_to_MAIN_CLK);
|
||||
|
||||
/* Configure SYSOSC clock source. */
|
||||
/* Power on SYSXTAL */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL);
|
||||
/* Updated XTAL oscillator settling time */
|
||||
POWER_UpdateOscSettlingTime(BOARD_SYSOSC_SETTLING_US);
|
||||
/* Enable system OSC */
|
||||
CLOCK_EnableSysOscClk(true, true, BOARD_SYSOSC_SETTLING_US);
|
||||
/* Sets external XTAL OSC freq */
|
||||
CLOCK_SetXtalFreq(BOARD_XTAL_SYS_CLK_HZ);
|
||||
|
||||
/* Configure SysPLL0 clock source. */
|
||||
CLOCK_InitSysPll(&g_sysPllConfig_clock_init);
|
||||
/* Enable MAIN PLL clock */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd0, 24);
|
||||
/* Enable AUX0 PLL clock */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
|
||||
|
||||
/* Configure Audio PLL clock source. */
|
||||
CLOCK_InitAudioPll(&g_audioPllConfig_clock_init);
|
||||
/* Enable Audio PLL clock */
|
||||
CLOCK_InitAudioPfd(kCLOCK_Pfd0, 26);
|
||||
|
||||
/* Set MAINPLLCLKDIV divider to value 5 */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivMainPllClk, 5U);
|
||||
|
||||
/* Set SYSCPUAHBCLKDIV divider to value 2 */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2U);
|
||||
|
||||
/* Setup FRG0 clock */
|
||||
CLOCK_SetFRGClock(&g_frg0Config_clock_init);
|
||||
/* Setup FRG12 clock */
|
||||
CLOCK_SetFRGClock(&g_frg12Config_clock_init);
|
||||
|
||||
/* Set up clock selectors - Attach clocks to the peripheries. */
|
||||
/* Switch MAIN_CLK to MAIN_PLL */
|
||||
CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK);
|
||||
/* Switch SYSTICK_CLK to MAIN_CLK_DIV */
|
||||
CLOCK_AttachClk(kMAIN_CLK_DIV_to_SYSTICK_CLK);
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_usart, okay)
|
||||
/* Switch FLEXCOMM0 to FRG */
|
||||
CLOCK_AttachClk(kFRG_to_FLEXCOMM0);
|
||||
#endif
|
||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm12), nxp_lpc_usart, okay)
|
||||
/* Switch FLEXCOMM12 to FRG */
|
||||
CLOCK_AttachClk(kFRG_to_FLEXCOMM12);
|
||||
#endif
|
||||
/* Switch CLKOUT to FRO_DIV2 */
|
||||
CLOCK_AttachClk(kFRO_DIV2_to_CLKOUT);
|
||||
|
||||
/* Set up dividers. */
|
||||
/* Set AUDIOPLLCLKDIV divider to value 15 */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 15U);
|
||||
/* Set FRGPLLCLKDIV divider to value 11 */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivPLLFRGClk, 11U);
|
||||
/* Set SYSTICKFCLKDIV divider to value 2 */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 2U);
|
||||
/* Set PFC0DIV divider to value 2 */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivPfc0Clk, 2U);
|
||||
/* Set PFC1DIV divider to value 4 */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivPfc1Clk, 4U);
|
||||
/* Set CLKOUTFCLKDIV divider to value 100 */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivClockOut, 100U);
|
||||
|
||||
/*
|
||||
* Call function flexspi_setup_clock() to set user configured clock source/divider
|
||||
* for FlexSPI.
|
||||
*/
|
||||
flexspi_setup_clock(FLEXSPI0, 0U, 2U);
|
||||
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
|
||||
|
||||
/* Set main clock to FRO as deep sleep clock by default. */
|
||||
POWER_SetDeepSleepClock(kDeepSleepClk_Fro);
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Perform basic hardware initialization
|
||||
*
|
||||
* Initialize the interrupt controller device drivers.
|
||||
* Also initialize the timer device driver, if required.
|
||||
*
|
||||
* @return 0
|
||||
*/
|
||||
|
||||
static int nxp_rt500_init(const struct device *arg)
|
||||
{
|
||||
ARG_UNUSED(arg);
|
||||
|
||||
/* old interrupt lock level */
|
||||
unsigned int oldLevel;
|
||||
|
||||
/* disable interrupts */
|
||||
oldLevel = irq_lock();
|
||||
|
||||
/* Initialize clocks with tool generated code */
|
||||
clock_init();
|
||||
|
||||
/*
|
||||
* install default handler that simply resets the CPU if configured in
|
||||
* the kernel, NOP otherwise
|
||||
*/
|
||||
NMI_INIT();
|
||||
|
||||
/* restore interrupt state */
|
||||
irq_unlock(oldLevel);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(nxp_rt500_init, PRE_KERNEL_1, 0);
|
75
soc/arm/nxp_imx/rt5xx/soc.h
Normal file
75
soc/arm/nxp_imx/rt5xx/soc.h
Normal file
|
@ -0,0 +1,75 @@
|
|||
/*
|
||||
* Copyright (c) 2022, NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Board configuration macros for the MXRT595 platform
|
||||
*
|
||||
* This header file is used to specify and describe board-level aspects for the
|
||||
* 'MXRT595' platform.
|
||||
*/
|
||||
|
||||
#ifndef _SOC__H_
|
||||
#define _SOC__H_
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
#include <sys/util.h>
|
||||
#include <fsl_common.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
/*!<@brief Analog mux is disabled */
|
||||
#define IOPCTL_PIO_ANAMUX_DI 0x00u
|
||||
/*!<@brief Analog mux is enabled */
|
||||
#define IOPCTL_PIO_ANAMUX_EN 0x0200u
|
||||
/*!<@brief Normal drive */
|
||||
#define IOPCTL_PIO_FULLDRIVE_DI 0x00u
|
||||
/*!<@brief Full drive */
|
||||
#define IOPCTL_PIO_FULLDRIVE_EN 0x0100u
|
||||
/*!<@brief Selects pin function 0 */
|
||||
#define IOPCTL_PIO_FUNC0 0x00u
|
||||
/*!<@brief Selects pin function 1 */
|
||||
#define IOPCTL_PIO_FUNC1 0x01u
|
||||
/*!<@brief Selects pin function 2 */
|
||||
#define IOPCTL_PIO_FUNC2 0x02u
|
||||
/*!<@brief Selects pin function 3 */
|
||||
#define IOPCTL_PIO_FUNC3 0x03u
|
||||
/*!<@brief Selects pin function 4 */
|
||||
#define IOPCTL_PIO_FUNC4 0x04u
|
||||
/*!<@brief Selects pin function 5 */
|
||||
#define IOPCTL_PIO_FUNC5 0x05u
|
||||
/*!<@brief Selects pin function 6 */
|
||||
#define IOPCTL_PIO_FUNC6 0x06u
|
||||
/*!<@brief Selects pin function 7 */
|
||||
#define IOPCTL_PIO_FUNC7 0x07u
|
||||
/*!<@brief Selects pin function 8 */
|
||||
#define IOPCTL_PIO_FUNC8 0x08u
|
||||
/*!<@brief Disable input buffer function */
|
||||
#define IOPCTL_PIO_INBUF_DI 0x00u
|
||||
/*!<@brief Enables input buffer function */
|
||||
#define IOPCTL_PIO_INBUF_EN 0x40u
|
||||
/*!<@brief Input function is not inverted */
|
||||
#define IOPCTL_PIO_INV_DI 0x00u
|
||||
/*!<@brief Input function is inverted */
|
||||
#define IOPCTL_PIO_INV_EN 0x0800u
|
||||
/*!<@brief Pseudo Output Drain is disabled */
|
||||
#define IOPCTL_PIO_PSEDRAIN_DI 0x00u
|
||||
/*!<@brief Pseudo Output Drain is enabled */
|
||||
#define IOPCTL_PIO_PSEDRAIN_EN 0x0400u
|
||||
/*!<@brief Enable pull-down function */
|
||||
#define IOPCTL_PIO_PULLDOWN_EN 0x00u
|
||||
/*!<@brief Enable pull-up function */
|
||||
#define IOPCTL_PIO_PULLUP_EN 0x20u
|
||||
/*!<@brief Disable pull-up / pull-down function */
|
||||
#define IOPCTL_PIO_PUPD_DI 0x00u
|
||||
/*!<@brief Enable pull-up / pull-down function */
|
||||
#define IOPCTL_PIO_PUPD_EN 0x10u
|
||||
/*!<@brief Normal mode */
|
||||
#define IOPCTL_PIO_SLEW_RATE_NORMAL 0x00u
|
||||
/*!<@brief Slow mode */
|
||||
#define IOPCTL_PIO_SLEW_RATE_SLOW 0x80u
|
||||
|
||||
#endif /* _SOC__H_ */
|
Loading…
Add table
Add a link
Reference in a new issue