soc: arm: nxp_imx: Convert from Kconfig to DT_NODELABEL
As prep for drivers being converted to utilize DT_INST and removal of per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL instead. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala
Kumar Gala
parent
5a8a06661d
commit
e6a1dc9674
3 changed files with 92 additions and 90 deletions
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@ -18,4 +18,6 @@
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#define RDC_DOMAIN_PERM(domain, perm) (perm << (domain * 2))
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#define RDC_DT_VAL(nodelabel) DT_PROP(DT_NODELABEL(nodelabel), rdc)
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RDC_IMX_RDC_H_ */
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@ -21,72 +21,72 @@ static void SOC_RdcInit(void)
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RDC_DOMAIN_PERM(M4_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
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false, false);
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#ifdef CONFIG_UART_IMX_UART_1
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#if DT_HAS_NODE(DT_NODELABEL(uart1))
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/* Set access to UART_1 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapUart1, DT_NXP_IMX_UART_UART_1_RDC, false, false);
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#endif /* CONFIG_UART_IMX_UART_1 */
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#ifdef CONFIG_UART_IMX_UART_2
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RDC_SetPdapAccess(RDC, rdcPdapUart1, RDC_DT_VAL(uart1), false, false);
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#endif
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#if DT_HAS_NODE(DT_NODELABEL(uart2))
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/* Set access to UART_2 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapUart2, DT_NXP_IMX_UART_UART_2_RDC, false, false);
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#endif /* CONFIG_UART_IMX_UART_2 */
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#ifdef CONFIG_UART_IMX_UART_3
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RDC_SetPdapAccess(RDC, rdcPdapUart2, RDC_DT_VAL(uart2), false, false);
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#endif
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#if DT_HAS_NODE(DT_NODELABEL(uart3))
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/* Set access to UART_3 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapUart3, DT_NXP_IMX_UART_UART_3_RDC, false, false);
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#endif /* CONFIG_UART_IMX_UART_3 */
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#ifdef CONFIG_UART_IMX_UART_4
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RDC_SetPdapAccess(RDC, rdcPdapUart3, RDC_DT_VAL(uart3), false, false);
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#endif
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#if DT_HAS_NODE(DT_NODELABEL(uart4))
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/* Set access to UART_4 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapUart4, DT_NXP_IMX_UART_UART_4_RDC, false, false);
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#endif /* CONFIG_UART_IMX_UART_4 */
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#ifdef CONFIG_UART_IMX_UART_5
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RDC_SetPdapAccess(RDC, rdcPdapUart4, RDC_DT_VAL(uart4), false, false);
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#endif
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#if DT_HAS_NODE(DT_NODELABEL(uart5))
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/* Set access to UART_5 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapUart5, DT_NXP_IMX_UART_UART_5_RDC, false, false);
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#endif /* CONFIG_UART_IMX_UART_5 */
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#ifdef CONFIG_UART_IMX_UART_6
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RDC_SetPdapAccess(RDC, rdcPdapUart5, RDC_DT_VAL(uart5), false, false);
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#endif
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#if DT_HAS_NODE(DT_NODELABEL(uart6))
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/* Set access to UART_6 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapUart6, DT_NXP_IMX_UART_UART_6_RDC, false, false);
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#endif /* CONFIG_UART_IMX_UART_6 */
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#ifdef CONFIG_GPIO_IMX_PORT_1
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RDC_SetPdapAccess(RDC, rdcPdapUart6, RDC_DT_VAL(uart6), false, false);
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#endif
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#if DT_HAS_NODE(DT_NODELABEL(gpio1))
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/* Set access to GPIO_1 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapGpio1, DT_NXP_IMX_GPIO_GPIO_1_RDC, false, false);
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#endif /* CONFIG_GPIO_IMX_PORT_1 */
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#ifdef CONFIG_GPIO_IMX_PORT_2
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RDC_SetPdapAccess(RDC, rdcPdapGpio1, RDC_DT_VAL(gpio1), false, false);
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#endif
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#if DT_HAS_NODE(DT_NODELABEL(gpio2))
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/* Set access to GPIO_2 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapGpio2, DT_NXP_IMX_GPIO_GPIO_2_RDC, false, false);
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#endif /* CONFIG_GPIO_IMX_PORT_2 */
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#ifdef CONFIG_GPIO_IMX_PORT_3
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RDC_SetPdapAccess(RDC, rdcPdapGpio2, RDC_DT_VAL(gpio2), false, false);
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#endif
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#if DT_HAS_NODE(DT_NODELABEL(gpio3))
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/* Set access to GPIO_3 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapGpio3, DT_NXP_IMX_GPIO_GPIO_3_RDC, false, false);
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#endif /* CONFIG_GPIO_IMX_PORT_3 */
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#ifdef CONFIG_GPIO_IMX_PORT_4
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RDC_SetPdapAccess(RDC, rdcPdapGpio3, RDC_DT_VAL(gpio3), false, false);
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#endif
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#if DT_HAS_NODE(DT_NODELABEL(gpio4))
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/* Set access to GPIO_4 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapGpio4, DT_NXP_IMX_GPIO_GPIO_4_RDC, false, false);
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#endif /* CONFIG_GPIO_IMX_PORT_4 */
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#ifdef CONFIG_GPIO_IMX_PORT_5
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RDC_SetPdapAccess(RDC, rdcPdapGpio4, RDC_DT_VAL(gpio4), false, false);
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#endif
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#if DT_HAS_NODE(DT_NODELABEL(gpio5))
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/* Set access to GPIO_5 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapGpio5, DT_NXP_IMX_GPIO_GPIO_5_RDC, false, false);
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#endif /* CONFIG_GPIO_IMX_PORT_5 */
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#ifdef CONFIG_GPIO_IMX_PORT_6
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RDC_SetPdapAccess(RDC, rdcPdapGpio5, RDC_DT_VAL(gpio5), false, false);
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#endif
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#if DT_HAS_NODE(DT_NODELABEL(gpio6))
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/* Set access to GPIO_6 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapGpio6, DT_NXP_IMX_GPIO_GPIO_6_RDC, false, false);
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#endif /* CONFIG_GPIO_IMX_PORT_6 */
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#ifdef CONFIG_GPIO_IMX_PORT_7
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RDC_SetPdapAccess(RDC, rdcPdapGpio6, RDC_DT_VAL(gpio6), false, false);
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#endif
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#if DT_HAS_NODE(DT_NODELABEL(gpio7))
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/* Set access to GPIO_7 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapGpio7, DT_NXP_IMX_GPIO_GPIO_7_RDC, false, false);
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#endif /* CONFIG_GPIO_IMX_PORT_7 */
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RDC_SetPdapAccess(RDC, rdcPdapGpio7, RDC_DT_VAL(gpio7), false, false);
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#endif
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#ifdef CONFIG_IPM_IMX
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/* Set access to MU B for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapMuB, DT_NXP_IMX_MU_MU_B_RDC, false, false);
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RDC_SetPdapAccess(RDC, rdcPdapMuB, RDC_DT_VAL(mub), false, false);
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#endif /* CONFIG_IPM_IMX */
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#ifdef CONFIG_COUNTER_IMX_EPIT_1
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#if DT_HAS_NODE(DT_NODELABEL(epit1))
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/* Set access to EPIT_1 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapEpit1, DT_NXP_IMX_EPIT_EPIT_1_RDC, false, false);
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#endif /* CONFIG_COUNTER_IMX_EPIT_1 */
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#ifdef CONFIG_COUNTER_IMX_EPIT_2
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RDC_SetPdapAccess(RDC, rdcPdapEpit1, RDC_DT_VAL(epit1), false, false);
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#endif
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#if DT_HAS_NODE(DT_NODELABEL(epit2))
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/* Set access to EPIT_2 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapEpit2, DT_NXP_IMX_EPIT_EPIT_2_RDC, false, false);
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#endif /* CONFIG_COUNTER_IMX_EPIT_2 */
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RDC_SetPdapAccess(RDC, rdcPdapEpit2, RDC_DT_VAL(epit2), false, false);
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#endif
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}
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/* Initialize cache. */
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@ -151,12 +151,12 @@ static void SOC_ClockInit(void)
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CCM_SetRootDivider(CCM, ccmRootPerclkPodf, 0);
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/* Enable EPIT clocks */
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#ifdef CONFIG_COUNTER_IMX_EPIT_1
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#if DT_HAS_NODE(DT_NODELABEL(epit1))
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CCM_ControlGate(CCM, ccmCcgrGateEpit1Clk, ccmClockNeededAll);
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#endif /* CONFIG_COUNTER_IMX_EPIT_1 */
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#ifdef CONFIG_COUNTER_IMX_EPIT_2
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#endif
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#if DT_HAS_NODE(DT_NODELABEL(epit2))
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CCM_ControlGate(CCM, ccmCcgrGateEpit2Clk, ccmClockNeededAll);
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#endif /* CONFIG_COUNTER_IMX_EPIT_2 */
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#endif
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#endif /* CONFIG_COUNTER_IMX_EPIT */
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}
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@ -56,25 +56,25 @@ void SOC_RdcInit(void)
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static void nxp_mcimx7_gpio_config(void)
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{
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#ifdef CONFIG_GPIO_IMX_PORT_1
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RDC_SetPdapAccess(RDC, rdcPdapGpio1, DT_NXP_IMX_GPIO_GPIO_1_RDC, false, false);
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#if DT_HAS_NODE(DT_NODELABEL(gpio1))
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RDC_SetPdapAccess(RDC, rdcPdapGpio1, RDC_DT_VAL(gpio1), false, false);
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/* Enable gpio clock gate */
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CCM_ControlGate(CCM, ccmCcgrGateGpio1, ccmClockNeededRunWait);
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#endif /* CONFIG_GPIO_IMX_PORT_1 */
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#endif
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#ifdef CONFIG_GPIO_IMX_PORT_2
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RDC_SetPdapAccess(RDC, rdcPdapGpio2, DT_NXP_IMX_GPIO_GPIO_2_RDC, false, false);
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#if DT_HAS_NODE(DT_NODELABEL(gpio2))
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RDC_SetPdapAccess(RDC, rdcPdapGpio2, RDC_DT_VAL(gpio2), false, false);
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/* Enable gpio clock gate */
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CCM_ControlGate(CCM, ccmCcgrGateGpio2, ccmClockNeededRunWait);
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#endif /* CONFIG_GPIO_IMX_PORT_2 */
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#endif
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#ifdef CONFIG_GPIO_IMX_PORT_7
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RDC_SetPdapAccess(RDC, rdcPdapGpio7, DT_NXP_IMX_GPIO_GPIO_7_RDC, false, false);
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#if DT_HAS_NODE(DT_NODELABEL(gpio7))
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RDC_SetPdapAccess(RDC, rdcPdapGpio7, RDC_DT_VAL(gpio7), false, false);
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/* Enable gpio clock gate */
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CCM_ControlGate(CCM, ccmCcgrGateGpio7, ccmClockNeededRunWait);
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#endif /* CONFIG_GPIO_IMX_PORT_2 */
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#endif
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}
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#endif /* CONFIG_GPIO_IMX */
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@ -83,9 +83,9 @@ static void nxp_mcimx7_gpio_config(void)
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static void nxp_mcimx7_uart_config(void)
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{
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#ifdef CONFIG_UART_IMX_UART_2
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#if DT_HAS_NODE(DT_NODELABEL(uart2))
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/* We need to grasp board uart exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapUart2, DT_NXP_IMX_UART_UART_2_RDC, false, false);
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RDC_SetPdapAccess(RDC, rdcPdapUart2, RDC_DT_VAL(uart2), false, false);
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/* Select clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootUart2, ccmRootmuxUartOsc24m, 0, 0);
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/* Enable uart clock */
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@ -96,11 +96,11 @@ static void nxp_mcimx7_uart_config(void)
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* So we need UART clock all the time
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*/
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CCM_ControlGate(CCM, ccmCcgrGateUart2, ccmClockNeededAll);
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#endif /* #ifdef CONFIG_UART_IMX_UART_2 */
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#endif
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#ifdef CONFIG_UART_IMX_UART_6
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#if DT_HAS_NODE(DT_NODELABEL(uart6))
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/* We need to grasp board uart exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapUart6, DT_NXP_IMX_UART_UART_6_RDC, false, false);
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RDC_SetPdapAccess(RDC, rdcPdapUart6, RDC_DT_VAL(uart6), false, false);
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/* Select clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootUart6, ccmRootmuxUartOsc24m, 0, 0);
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/* Enable uart clock */
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@ -111,7 +111,7 @@ static void nxp_mcimx7_uart_config(void)
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* So we need UART clock all the time
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*/
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CCM_ControlGate(CCM, ccmCcgrGateUart6, ccmClockNeededAll);
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#endif /* #ifdef CONFIG_UART_IMX_UART_6 */
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#endif
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}
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#endif /* CONFIG_UART_IMX */
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@ -120,45 +120,45 @@ static void nxp_mcimx7_uart_config(void)
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static void nxp_mcimx7_i2c_config(void)
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{
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#ifdef CONFIG_I2C_1
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#if DT_HAS_NODE(DT_NODELABEL(i2c1))
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/* In this example, we need to grasp board I2C exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapI2c1, DT_FSL_IMX7D_I2C_I2C_1_RDC, false, false);
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RDC_SetPdapAccess(RDC, rdcPdapI2c1, RDC_DT_VAL(i2c1), false, false);
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/* Select I2C clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootI2c1, ccmRootmuxI2cOsc24m, 0, 0);
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/* Enable I2C clock */
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CCM_EnableRoot(CCM, ccmRootI2c1);
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CCM_ControlGate(CCM, ccmCcgrGateI2c1, ccmClockNeededRunWait);
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#endif /* CONFIG_I2C_1 */
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#endif
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#ifdef CONFIG_I2C_2
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#if DT_HAS_NODE(DT_NODELABEL(i2c2))
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/* In this example, we need to grasp board I2C exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapI2c2, DT_FSL_IMX7D_I2C_I2C_2_RDC, false, false);
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RDC_SetPdapAccess(RDC, rdcPdapI2c2, RDC_DT_VAL(i2c2), false, false);
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/* Select I2C clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootI2c2, ccmRootmuxI2cOsc24m, 0, 0);
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/* Enable I2C clock */
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CCM_EnableRoot(CCM, ccmRootI2c2);
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CCM_ControlGate(CCM, ccmCcgrGateI2c2, ccmClockNeededRunWait);
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#endif /* CONFIG_I2C_2 */
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#endif
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#ifdef CONFIG_I2C_3
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#if DT_HAS_NODE(DT_NODELABEL(i2c3))
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/* In this example, we need to grasp board I2C exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapI2c3, DT_FSL_IMX7D_I2C_I2C_3_RDC, false, false);
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RDC_SetPdapAccess(RDC, rdcPdapI2c3, RDC_DT_VAL(i2c3), false, false);
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/* Select I2C clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootI2c3, ccmRootmuxI2cOsc24m, 0, 0);
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/* Enable I2C clock */
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CCM_EnableRoot(CCM, ccmRootI2c3);
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CCM_ControlGate(CCM, ccmCcgrGateI2c3, ccmClockNeededRunWait);
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#endif /* CONFIG_I2C_3 */
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#endif
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#ifdef CONFIG_I2C_4
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#if DT_HAS_NODE(DT_NODELABEL(i2c4))
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/* In this example, we need to grasp board I2C exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapI2c4, DT_FSL_IMX7D_I2C_I2C_4_RDC, false, false);
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RDC_SetPdapAccess(RDC, rdcPdapI2c4, RDC_DT_VAL(i2c4), false, false);
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/* Select I2C clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootI2c4, ccmRootmuxI2cOsc24m, 0, 0);
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/* Enable I2C clock */
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CCM_EnableRoot(CCM, ccmRootI2c4);
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CCM_ControlGate(CCM, ccmCcgrGateI2c4, ccmClockNeededRunWait);
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#endif /* CONFIG_I2C_4 */
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#endif
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}
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#endif /* CONFIG_I2C_IMX */
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@ -167,45 +167,45 @@ static void nxp_mcimx7_i2c_config(void)
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static void nxp_mcimx7_pwm_config(void)
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{
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#ifdef CONFIG_PWM_1
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#if DT_HAS_NODE(DT_NODELABEL(pwm1))
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/* We need to grasp board pwm exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapPwm1, DT_FSL_IMX7D_PWM_PWM_1_RDC, false, false);
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RDC_SetPdapAccess(RDC, rdcPdapPwm1, RDC_DT_VAL(pwm1), false, false);
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/* Select clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootPwm1, ccmRootmuxPwmOsc24m, 0, 0);
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/* Enable pwm clock */
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CCM_EnableRoot(CCM, ccmRootPwm1);
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CCM_ControlGate(CCM, ccmCcgrGatePwm1, ccmClockNeededAll);
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#endif /* #ifdef CONFIG_PWM_1 */
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#endif
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#ifdef CONFIG_PWM_2
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#if DT_HAS_NODE(DT_NODELABEL(pwm2))
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/* We need to grasp board pwm exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapPwm2, DT_FSL_IMX7D_PWM_PWM_2_RDC, false, false);
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RDC_SetPdapAccess(RDC, rdcPdapPwm2, RDC_DT_VAL(pwm2), false, false);
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/* Select clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootPwm2, ccmRootmuxPwmOsc24m, 0, 0);
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/* Enable pwm clock */
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CCM_EnableRoot(CCM, ccmRootPwm2);
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CCM_ControlGate(CCM, ccmCcgrGatePwm2, ccmClockNeededAll);
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#endif /* #ifdef CONFIG_PWM_2 */
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#endif
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#ifdef CONFIG_PWM_3
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#if DT_HAS_NODE(DT_NODELABEL(pwm3))
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/* We need to grasp board pwm exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapPwm3, DT_FSL_IMX7D_PWM_PWM_3_RDC, false, false);
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RDC_SetPdapAccess(RDC, rdcPdapPwm3, RDC_DT_VAL(pwm3), false, false);
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/* Select clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootPwm3, ccmRootmuxPwmOsc24m, 0, 0);
|
||||
/* Enable pwm clock */
|
||||
CCM_EnableRoot(CCM, ccmRootPwm3);
|
||||
CCM_ControlGate(CCM, ccmCcgrGatePwm3, ccmClockNeededAll);
|
||||
#endif /* #ifdef CONFIG_PWM_3 */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PWM_4
|
||||
#if DT_HAS_NODE(DT_NODELABEL(pwm4))
|
||||
/* We need to grasp board pwm exclusively */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapPwm4, DT_FSL_IMX7D_PWM_PWM_4_RDC, false, false);
|
||||
RDC_SetPdapAccess(RDC, rdcPdapPwm4, RDC_DT_VAL(pwm4), false, false);
|
||||
/* Select clock derived from OSC clock(24M) */
|
||||
CCM_UpdateRoot(CCM, ccmRootPwm4, ccmRootmuxPwmOsc24m, 0, 0);
|
||||
/* Enable pwm clock */
|
||||
CCM_EnableRoot(CCM, ccmRootPwm4);
|
||||
CCM_ControlGate(CCM, ccmCcgrGatePwm4, ccmClockNeededAll);
|
||||
#endif /* #ifdef CONFIG_PWM_4 */
|
||||
#endif
|
||||
|
||||
}
|
||||
#endif /* CONFIG_PWM_IMX */
|
||||
|
|
@ -214,7 +214,7 @@ static void nxp_mcimx7_pwm_config(void)
|
|||
static void nxp_mcimx7_mu_config(void)
|
||||
{
|
||||
/* Set access to MU B for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapMuB, DT_NXP_IMX_MU_MU_B_RDC, false, false);
|
||||
RDC_SetPdapAccess(RDC, rdcPdapMuB, RDC_DT_VAL(mub), false, false);
|
||||
|
||||
/* Enable clock gate for MU*/
|
||||
CCM_ControlGate(CCM, ccmCcgrGateMu, ccmClockNeededRun);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue