riscv: add support for thread local storage
Adds the necessary bits to initialize TLS in the stack area and sets up CPU registers during context switch. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
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6 changed files with 44 additions and 0 deletions
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@ -65,6 +65,7 @@ config RISCV
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bool
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select ARCH_IS_SET
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select HAS_DTS
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select ARCH_HAS_THREAD_LOCAL_STORAGE
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imply XIP
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help
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RISCV architecture
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@ -14,3 +14,4 @@ zephyr_library_sources(
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)
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zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
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zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c)
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@ -30,6 +30,11 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
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stack_init->a1 = (ulong_t)p1;
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stack_init->a2 = (ulong_t)p2;
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stack_init->a3 = (ulong_t)p3;
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#ifdef CONFIG_THREAD_LOCAL_STORAGE
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stack_init->tp = (ulong_t)thread->tls;
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#endif
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/*
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* Following the RISC-V architecture,
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* the MSTATUS register (used to globally enable/disable interrupt),
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35
arch/riscv/core/tls.c
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35
arch/riscv/core/tls.c
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@ -0,0 +1,35 @@
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/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <kernel_structs.h>
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#include <kernel_internal.h>
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#include <kernel_tls.h>
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#include <app_memory/app_memdomain.h>
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#include <sys/util.h>
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size_t arch_tls_stack_setup(struct k_thread *new_thread, char *stack_ptr)
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{
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/*
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* TLS area for RISC-V is simple without any extra
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* data.
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*/
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/*
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* Since we are populating things backwards,
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* setup the TLS data/bss area first.
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*/
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stack_ptr -= z_tls_data_size();
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z_tls_copy(stack_ptr);
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/*
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* Set thread TLS pointer which is used in
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* context switch to point to TLS area.
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*/
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new_thread->tls = POINTER_TO_UINT(stack_ptr);
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return z_tls_data_size();
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}
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@ -111,6 +111,7 @@ SECTIONS
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_image_text_end = .;
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#include <linker/common-rom.ld>
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#include <linker/thread-local-storage.ld>
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SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
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{
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@ -122,6 +122,7 @@ SECTIONS
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_image_rodata_start = .;
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#include <linker/common-rom.ld>
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#include <linker/thread-local-storage.ld>
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SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
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{
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