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arch: xtensa: replace DT_CPU_CLOCK_FREQUENCY with new dt macros

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Replace DT_CPU_CLOCK_FREQUENCY with a PATH based reference to cpu@0
(DT_PATH(cpus, cpu_0)) and than getting the clock_frequency property:

DT_CPU_CLOCK_FREQUENCY -> DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)

This lets us remove DT_CPU_CLOCK_FREQUENCY from dts_fixup.h

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-04-22 06:57:19 -05:00 • committed by Kumar Gala
commit 6784558b22
5 changed files with 2 additions and 25 deletions
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2
include/arch/xtensa/xtensa_rtos.h
View file

@ -47,7 +47,7 @@
#endif
#undef XT_CLOCK_FREQ
#define XT_CLOCK_FREQ DT_CPU_CLOCK_FREQUENCY
#define XT_CLOCK_FREQ DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
#ifndef XT_TIMER_INDEX
#if defined configXT_TIMER_INDEX

2
include/arch/xtensa/xtensa_timer.h
View file

@ -115,7 +115,7 @@
* anyway!).
*/
#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
#define XT_CLOCK_FREQ DT_CPU_CLOCK_FREQUENCY
#define XT_CLOCK_FREQ DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
#endif
#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)

10
soc/xtensa/esp32/dts_fixup.h
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@ -1,10 +0,0 @@
/*
* Copyright (c) 2018 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/* SoC level DTS fixup file */
#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY
/* End of SoC Level DTS fixup file */

2
soc/xtensa/intel_s1000/dts_fixup.h
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@ -2,8 +2,6 @@
/* SoC level DTS fixup file */
#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY
#define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS
#define DT_L2_SRAM_SIZE CONFIG_SRAM_SIZE * 1024

11
soc/xtensa/sample_controller/dts_fixup.h
View file

@ -1,11 +0,0 @@
/*
* Copyright (c) 2018 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/* SoC level DTS fixup file */
#define DT_CPU_CLOCK_FREQUENCY DT_SAMPLE_CONTROLLER_0_CLOCK_FREQUENCY
/* End of SoC Level DTS fixup file */