arch: xtensa: replace DT_CPU_CLOCK_FREQUENCY with new dt macros
Replace DT_CPU_CLOCK_FREQUENCY with a PATH based reference to cpu@0 (DT_PATH(cpus, cpu_0)) and than getting the clock_frequency property: DT_CPU_CLOCK_FREQUENCY -> DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) This lets us remove DT_CPU_CLOCK_FREQUENCY from dts_fixup.h Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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5 changed files with 2 additions and 25 deletions
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@ -47,7 +47,7 @@
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#endif
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#undef XT_CLOCK_FREQ
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#define XT_CLOCK_FREQ DT_CPU_CLOCK_FREQUENCY
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#define XT_CLOCK_FREQ DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
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#ifndef XT_TIMER_INDEX
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#if defined configXT_TIMER_INDEX
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@ -115,7 +115,7 @@
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* anyway!).
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*/
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#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
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#define XT_CLOCK_FREQ DT_CPU_CLOCK_FREQUENCY
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#define XT_CLOCK_FREQ DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
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#endif
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#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)
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@ -1,10 +0,0 @@
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/*
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* Copyright (c) 2018 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* SoC level DTS fixup file */
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#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY
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/* End of SoC Level DTS fixup file */
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@ -2,8 +2,6 @@
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/* SoC level DTS fixup file */
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#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY
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#define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS
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#define DT_L2_SRAM_SIZE CONFIG_SRAM_SIZE * 1024
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@ -1,11 +0,0 @@
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/*
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* Copyright (c) 2018 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* SoC level DTS fixup file */
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#define DT_CPU_CLOCK_FREQUENCY DT_SAMPLE_CONTROLLER_0_CLOCK_FREQUENCY
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/* End of SoC Level DTS fixup file */
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