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drivers/clock_controller: stm32: Prepare for dts based configuration

Browse source 
To allow transition to device tree based clock configuration on
stm32 targets, rework clock_control driver to use intermediate
STM32_ macros initially defined as the equivalent Kconfig macros
for now.
Propagate the change in all code using these macros.

The reason to introduce these new macros instead of configuring
Kconfig flags using dt kconfigfunctions is that we'll need
to be able to inform users that Kconfig flags are deprecated
once the whole family conversion is done, to encourage
out of tree users to adopt this new configuration scheme.

Note: For now STM32H7 series and code is excluded.
This is the same for some series specific code such as
PLL mul/div for L0/L1 and XTRE prescaler on F1 series.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2021-03-31 15:46:10 +02:00 • committed by Carles Cufí
commit 2691541ad2
11 changed files with 182 additions and 66 deletions
Download patch file Download diff file Expand all files Collapse all files

2
drivers/bluetooth/hci/ipm_stm32wb.c
View file

@ -371,7 +371,7 @@ static void start_ble_rf(void)
LL_RCC_ReleaseBackupDomainReset();
}
#ifdef CONFIG_CLOCK_STM32_LSE
#if STM32_LSE_CLOCK
/* Select LSE clock */
LL_RCC_LSE_Enable();
while (!LL_RCC_LSE_IsReady()) {

77
drivers/clock_control/clock_stm32_ll_common.c
View file

@ -40,7 +40,7 @@
#define __LL_RCC_CALC_HCLK_FREQ __LL_RCC_CALC_HCLK1_FREQ
#endif /* CONFIG_SOC_SERIES_STM32F0X */
#if CONFIG_CLOCK_STM32_AHB_PRESCALER > 1
#if STM32_AHB_PRESCALER > 1
/*
* AHB prescaler allows to set a HCLK frequency (feeding cortex systick)
* lower than SYSCLK frequency (actual core frequency).
@ -57,31 +57,22 @@
static void config_bus_clk_init(LL_UTILS_ClkInitTypeDef *clk_init)
{
#if defined(CONFIG_SOC_SERIES_STM32WBX)
clk_init->CPU1CLKDivider = ahb_prescaler(
CONFIG_CLOCK_STM32_CPU1_PRESCALER);
clk_init->CPU2CLKDivider = ahb_prescaler(
CONFIG_CLOCK_STM32_CPU2_PRESCALER);
clk_init->AHB4CLKDivider = ahb_prescaler(
CONFIG_CLOCK_STM32_AHB4_PRESCALER);
clk_init->CPU1CLKDivider = ahb_prescaler(STM32_CPU1_PRESCALER);
clk_init->CPU2CLKDivider = ahb_prescaler(STM32_CPU2_PRESCALER);
clk_init->AHB4CLKDivider = ahb_prescaler(STM32_AHB4_PRESCALER);
#elif defined(CONFIG_SOC_SERIES_STM32WLX)
clk_init->CPU1CLKDivider = ahb_prescaler(
CONFIG_CLOCK_STM32_CPU1_PRESCALER);
clk_init->CPU2CLKDivider = ahb_prescaler(
CONFIG_CLOCK_STM32_CPU2_PRESCALER);
clk_init->AHB3CLKDivider = ahb_prescaler(
CONFIG_CLOCK_STM32_AHB3_PRESCALER);
clk_init->CPU1CLKDivider = ahb_prescaler(STM32_CPU1_PRESCALER);
clk_init->CPU2CLKDivider = ahb_prescaler(STM32_CPU2_PRESCALER);
clk_init->AHB3CLKDivider = ahb_prescaler(STM32_AHB3_PRESCALER);
#else
clk_init->AHBCLKDivider = ahb_prescaler(
CONFIG_CLOCK_STM32_AHB_PRESCALER);
clk_init->AHBCLKDivider = ahb_prescaler(STM32_AHB_PRESCALER);
#endif /* CONFIG_SOC_SERIES_STM32WBX */
clk_init->APB1CLKDivider = apb1_prescaler(
CONFIG_CLOCK_STM32_APB1_PRESCALER);
clk_init->APB1CLKDivider = apb1_prescaler(STM32_APB1_PRESCALER);
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && \
!defined (CONFIG_SOC_SERIES_STM32G0X)
clk_init->APB2CLKDivider = apb2_prescaler(
CONFIG_CLOCK_STM32_APB2_PRESCALER);
clk_init->APB2CLKDivider = apb2_prescaler(STM32_APB2_PRESCALER);
#endif
}
@ -236,12 +227,10 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
* more likely to contain actual clock speed
*/
uint32_t ahb_clock = SystemCoreClock;
uint32_t apb1_clock = get_bus_clock(ahb_clock,
CONFIG_CLOCK_STM32_APB1_PRESCALER);
uint32_t apb1_clock = get_bus_clock(ahb_clock, STM32_APB1_PRESCALER);
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && \
!defined (CONFIG_SOC_SERIES_STM32G0X)
uint32_t apb2_clock = get_bus_clock(ahb_clock,
CONFIG_CLOCK_STM32_APB2_PRESCALER);
uint32_t apb2_clock = get_bus_clock(ahb_clock, STM32_APB2_PRESCALER);
#endif
ARG_UNUSED(clock);
@ -349,8 +338,7 @@ int stm32_clock_control_init(const struct device *dev)
{
LL_UTILS_ClkInitTypeDef s_ClkInitStruct;
uint32_t hclk_prescaler;
#if defined(CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE) || \
defined(CONFIG_CLOCK_STM32_SYSCLK_SRC_MSI)
#if STM32_SYSCLK_SRC_HSE || STM32_SYSCLK_SRC_MSI
uint32_t old_hclk_freq;
uint32_t new_hclk_freq;
#endif
@ -370,7 +358,7 @@ int stm32_clock_control_init(const struct device *dev)
/* Some clocks would be activated by default */
config_enable_default_clocks();
#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
#if STM32_SYSCLK_SRC_PLL
LL_UTILS_PLLInitTypeDef s_PLLInitStruct;
/* configure PLL input settings */
@ -403,21 +391,20 @@ int stm32_clock_control_init(const struct device *dev)
}
#endif
#ifdef CONFIG_CLOCK_STM32_PLL_Q_DIVISOR
#if STM32_PLL_Q_DIVISOR
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ,
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR
STM32_PLL_Q_DIVISOR
<< RCC_PLLCFGR_PLLQ_Pos);
#endif /* CONFIG_CLOCK_STM32_PLL_Q_DIVISOR */
#endif /* STM32_PLL_Q_DIVISOR */
#ifdef CONFIG_CLOCK_STM32_PLL_SRC_MSI
#if STM32_PLL_SRC_MSI
/* Set MSI Range */
LL_RCC_MSI_EnableRangeSelection();
LL_RCC_MSI_SetRange(CONFIG_CLOCK_STM32_MSI_RANGE
<< RCC_CR_MSIRANGE_Pos);
LL_RCC_MSI_SetRange(STM32_MSI_RANGE << RCC_CR_MSIRANGE_Pos);
LL_RCC_MSI_SetCalibTrimming(0);
#ifdef CONFIG_CLOCK_STM32_MSI_PLL_MODE
#if STM32_MSI_PLL_MODE
/* Enable MSI hardware auto calibration */
LL_RCC_MSI_EnablePLLMode();
#endif
@ -429,7 +416,7 @@ int stm32_clock_control_init(const struct device *dev)
LL_RCC_HSI_Disable();
LL_RCC_HSE_Disable();
#elif CONFIG_CLOCK_STM32_PLL_SRC_HSI
#elif STM32_PLL_SRC_HSI
/* Switch to PLL with HSI as clock source */
LL_PLL_ConfigSystemClock_HSI(&s_PLLInitStruct, &s_ClkInitStruct);
@ -437,10 +424,10 @@ int stm32_clock_control_init(const struct device *dev)
LL_RCC_HSE_Disable();
LL_RCC_MSI_Disable();
#elif CONFIG_CLOCK_STM32_PLL_SRC_HSE
#elif STM32_PLL_SRC_HSE
int hse_bypass;
if (IS_ENABLED(CONFIG_CLOCK_STM32_HSE_BYPASS)) {
if (IS_ENABLED(STM32_HSE_BYPASS)) {
hse_bypass = LL_UTILS_HSEBYPASS_ON;
} else {
hse_bypass = LL_UTILS_HSEBYPASS_OFF;
@ -464,9 +451,9 @@ int stm32_clock_control_init(const struct device *dev)
LL_RCC_HSI_Disable();
LL_RCC_MSI_Disable();
#endif /* CONFIG_CLOCK_STM32_PLL_SRC_* */
#endif /* STM32_PLL_SRC_* */
#elif CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE
#elif STM32_SYSCLK_SRC_HSE
old_hclk_freq = HAL_RCC_GetHCLKFreq();
@ -487,7 +474,7 @@ int stm32_clock_control_init(const struct device *dev)
/* Enable HSE if not enabled */
if (LL_RCC_HSE_IsReady() != 1) {
/* Check if need to enable HSE bypass feature or not */
if (IS_ENABLED(CONFIG_CLOCK_STM32_HSE_BYPASS)) {
if (IS_ENABLED(STM32_HSE_BYPASS)) {
LL_RCC_HSE_EnableBypass();
} else {
LL_RCC_HSE_DisableBypass();
@ -526,7 +513,7 @@ int stm32_clock_control_init(const struct device *dev)
LL_RCC_MSI_Disable();
LL_RCC_PLL_Disable();
#elif CONFIG_CLOCK_STM32_SYSCLK_SRC_MSI
#elif STM32_SYSCLK_SRC_MSI
old_hclk_freq = HAL_RCC_GetHCLKFreq();
@ -535,7 +522,7 @@ int stm32_clock_control_init(const struct device *dev)
new_hclk_freq =
__LL_RCC_CALC_HCLK_FREQ(
__LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGESEL_RUN,
CONFIG_CLOCK_STM32_MSI_RANGE << RCC_CR_MSIRANGE_Pos),
STM32_MSI_RANGE << RCC_CR_MSIRANGE_Pos),
hclk_prescaler);
#if defined(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC)
@ -551,9 +538,9 @@ int stm32_clock_control_init(const struct device *dev)
/* Set MSI Range */
LL_RCC_MSI_EnableRangeSelection();
LL_RCC_MSI_SetRange(CONFIG_CLOCK_STM32_MSI_RANGE << RCC_CR_MSIRANGE_Pos);
LL_RCC_MSI_SetRange(STM32_MSI_RANGE << RCC_CR_MSIRANGE_Pos);
#if defined(CONFIG_CLOCK_STM32_MSI_PLL_MODE)
#if STM32_MSI_PLL_MODE
/* Enable MSI hardware auto calibration */
LL_RCC_MSI_EnablePLLMode();
#endif
@ -599,7 +586,7 @@ int stm32_clock_control_init(const struct device *dev)
LL_RCC_HSI_Disable();
LL_RCC_PLL_Disable();
#elif CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI
#elif STM32_SYSCLK_SRC_HSI
stm32_clock_switch_to_hsi(hclk_prescaler);
@ -623,7 +610,7 @@ int stm32_clock_control_init(const struct device *dev)
LL_RCC_MSI_Disable();
LL_RCC_PLL_Disable();
#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_... */
#endif /* STM32_SYSCLK_SRC_... */
/* configure MCO1/MCO2 based on Kconfig */
stm32_clock_control_mco_init();

4
drivers/clock_control/clock_stm32_ll_common.h
View file

@ -32,9 +32,9 @@
#define MCO2_SOURCE LL_RCC_MCO2SOURCE_PLLCLK
#endif
#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
#if STM32_SYSCLK_SRC_PLL
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit);
#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
#endif /* STM32_SYSCLK_SRC_PLL */
void config_enable_default_clocks(void);
/* Section for functions not available in every Cube packages */

10
drivers/clock_control/clock_stm32f2_f4_f7.c
View file

@ -16,7 +16,7 @@
#include "clock_stm32_ll_common.h"
#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
#if STM32_SYSCLK_SRC_PLL
/* Macros to fill up division factors values */
#define z_pllm(v) LL_RCC_PLLM_DIV_ ## v
@ -30,11 +30,11 @@
*/
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
{
pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLL_M_DIVISOR);
pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER;
pllinit->PLLP = pllp(CONFIG_CLOCK_STM32_PLL_P_DIVISOR);
pllinit->PLLM = pllm(STM32_PLL_M_DIVISOR);
pllinit->PLLN = STM32_PLL_N_MULTIPLIER;
pllinit->PLLP = pllp(STM32_PLL_P_DIVISOR);
}
#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
#endif /* STM32_SYSCLK_SRC_PLL */
/**
* @brief Activate default clocks

12
drivers/clock_control/clock_stm32l4_l5_wb_wl.c
View file

@ -17,7 +17,7 @@
#include "clock_stm32_ll_common.h"
#include "stm32_hsem.h"
#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
#if STM32_SYSCLK_SRC_PLL
/* Macros to fill up division factors values */
#define z_pllm(v) LL_RCC_PLLM_DIV_ ## v
@ -31,9 +31,9 @@
*/
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
{
pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLL_M_DIVISOR);
pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER;
pllinit->PLLR = pllr(CONFIG_CLOCK_STM32_PLL_R_DIVISOR);
pllinit->PLLM = pllm(STM32_PLL_M_DIVISOR);
pllinit->PLLN = STM32_PLL_N_MULTIPLIER;
pllinit->PLLR = pllr(STM32_PLL_R_DIVISOR);
#ifdef PWR_CR5_R1MODE
/* set power boost mode for sys clock greater than 80MHz */
if (sys_clock_hw_cycles_per_sec() >= MHZ(80)) {
@ -41,14 +41,14 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
}
#endif /* PWR_CR5_R1MODE */
}
#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
#endif /* STM32_SYSCLK_SRC_PLL */
/**
* @brief Activate default clocks
*/
void config_enable_default_clocks(void)
{
#ifdef CONFIG_CLOCK_STM32_LSE
#if STM32_LSE_CLOCK
/* LSE belongs to the back-up domain, enable access.*/
#if defined(CONFIG_SOC_SERIES_STM32WBX)

2
drivers/counter/counter_ll_stm32_rtc.c
View file

@ -337,7 +337,7 @@ static int rtc_stm32_init(const struct device *dev)
while (LL_RCC_LSE_IsReady() != 1) {
}
#if defined(CONFIG_CLOCK_STM32_MSI_PLL_MODE)
#if STM32_MSI_PLL_MODE
/* Enable MSI hardware auto calibration */
LL_RCC_MSI_EnablePLLMode();
#endif

4
drivers/pwm/pwm_stm32.c
View file

@ -136,11 +136,11 @@ static int get_tim_clk(const struct stm32_pclken *pclken, uint32_t *tim_clk)
}
#else
if (pclken->bus == STM32_CLOCK_BUS_APB1) {
apb_psc = CONFIG_CLOCK_STM32_APB1_PRESCALER;
apb_psc = STM32_APB1_PRESCALER;
}
#if !defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_SOC_SERIES_STM32G0X)
else {
apb_psc = CONFIG_CLOCK_STM32_APB2_PRESCALER;
apb_psc = STM32_APB2_PRESCALER;
}
#endif
#endif

4
drivers/usb/device/usb_dc_stm32.c
View file

@ -241,7 +241,7 @@ static int usb_dc_stm32_clock_enable(void)
* device. For now, we only use MSI for USB if not already used as
* system clock source.
*/
#if defined(CONFIG_CLOCK_STM32_MSI_PLL_MODE) && !defined(CONFIG_CLOCK_STM32_SYSCLK_SRC_MSI)
#if STM32_MSI_PLL_MODE && !STM32_SYSCLK_SRC_MSI
LL_RCC_MSI_Enable();
while (!LL_RCC_MSI_IsReady()) {
/* Wait for MSI to become ready */
@ -256,7 +256,7 @@ static int usb_dc_stm32_clock_enable(void)
} else {
LOG_ERR("Unable to set USB clock source to PLL.");
}
#endif /* CONFIG_CLOCK_STM32_MSI_PLL_MODE && !CONFIG_CLOCK_STM32_SYSCLK_SRC_MSI */
#endif /* STM32_MSI_PLL_MODE && !STM32_SYSCLK_SRC_MSI */
#elif defined(RCC_CFGR_OTGFSPRE)
/* On STM32F105 and STM32F107 parts the USB OTGFSCLK is derived from

129
include/drivers/clock_control/stm32_clock_control.h
View file

@ -15,6 +15,135 @@
/* common clock control device node for all STM32 chips */
#define STM32_CLOCK_CONTROL_NODE DT_NODELABEL(rcc)
/*
* Kconfig to device tree transition for clocks on STM32 targets:
*
* Following definitions are provided to allow a smooth transition
* between Kconfig based to dts based clocks configuration.
* These symbols allow to have both configuration schemes used simultaneoulsy
* while giving precedence to dts based configuration once available on a
* target.
* Finally, once all in-tree users are converted to dts based configuration,
* we'll be able to generate deprecation warnings for out of tree users of
* Kconfig related symbols.
*/
#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_rcc), ahb_prescaler)
#define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler)
#else
#define STM32_AHB_PRESCALER CONFIG_CLOCK_STM32_AHB_PRESCALER
#endif
#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_rcc), apb1_prescaler)
#define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler)
#else
#define STM32_APB1_PRESCALER CONFIG_CLOCK_STM32_APB1_PRESCALER
#endif
#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_rcc), apb2_prescaler)
#define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler)
#else
#define STM32_APB2_PRESCALER CONFIG_CLOCK_STM32_APB2_PRESCALER
#endif
#define STM32_AHB3_PRESCALER CONFIG_CLOCK_STM32_AHB3_PRESCALER
#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32wb_rcc), ahb4_prescaler)
#define STM32_AHB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
#else
#define STM32_AHB4_PRESCALER CONFIG_CLOCK_STM32_AHB4_PRESCALER
#endif
#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32wb_rcc), cpu1_prescaler)
#define STM32_CPU1_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
#else
#define STM32_CPU1_PRESCALER CONFIG_CLOCK_STM32_CPU1_PRESCALER
#endif
#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32wb_rcc), cpu2_prescaler)
#define STM32_CPU2_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu2_prescaler)
#else
#define STM32_CPU2_PRESCALER CONFIG_CLOCK_STM32_CPU2_PRESCALER
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay)
#define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m)
#define STM32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul_n)
#define STM32_PLL_P_DIVISOR DT_PROP(DT_NODELABEL(pll), div_p)
#define STM32_PLL_Q_DIVISOR DT_PROP(DT_NODELABEL(pll), div_q)
#define STM32_PLL_R_DIVISOR DT_PROP(DT_NODELABEL(pll), div_r)
#else
#define STM32_PLL_M_DIVISOR CONFIG_CLOCK_STM32_PLL_M_DIVISOR
#define STM32_PLL_N_MULTIPLIER CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER
#define STM32_PLL_P_DIVISOR CONFIG_CLOCK_STM32_PLL_P_DIVISOR
#define STM32_PLL_Q_DIVISOR CONFIG_CLOCK_STM32_PLL_Q_DIVISOR
#define STM32_PLL_R_DIVISOR CONFIG_CLOCK_STM32_PLL_R_DIVISOR
#endif
#define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc))
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32_rcc, okay)
#define STM32_SYSCLK_SRC_PLL DT_NODE_HAS_PROP(DT_NODELABEL(rcc), clocks) && \
DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(pll))
#define STM32_SYSCLK_SRC_HSI DT_NODE_HAS_PROP(DT_NODELABEL(rcc), clocks) && \
DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
#define STM32_SYSCLK_SRC_HSE DT_NODE_HAS_PROP(DT_NODELABEL(rcc), clocks) && \
DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
#define STM32_SYSCLK_SRC_MSI DT_NODE_HAS_PROP(DT_NODELABEL(rcc), clocks) && \
DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
#else
#define STM32_SYSCLK_SRC_PLL CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
#define STM32_SYSCLK_SRC_HSI CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI
#define STM32_SYSCLK_SRC_HSE CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE
#define STM32_SYSCLK_SRC_MSI CONFIG_CLOCK_STM32_SYSCLK_SRC_MSI
#endif
#define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll))
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay)
#define STM32_PLL_SRC_MSI DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
#define STM32_PLL_SRC_HSI DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
#define STM32_PLL_SRC_HSE DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
#else
#define STM32_PLL_SRC_MSI CONFIG_CLOCK_STM32_PLL_SRC_MSI
#define STM32_PLL_SRC_HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI
#define STM32_PLL_SRC_HSE CONFIG_CLOCK_STM32_PLL_SRC_HSE
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay)
#define STM32_PLL_SRC_PLL2 DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(pll)), DT_NODELABEL(pll2))
#else
#define STM32_PLL_SRC_PLL2 CONFIG_CLOCK_STM32_PLL_SRC_PLL2
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay)
#define STM32_LSE_CLOCK DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
#else
#define STM32_LSE_CLOCK CONFIG_CLOCK_STM32_LSE
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay)
#define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range)
#else
#define STM32_MSI_RANGE CONFIG_CLOCK_STM32_MSI_RANGE
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay)
#define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode)
#else
#define STM32_MSI_PLL_MODE CONFIG_CLOCK_STM32_MSI_PLL_MODE
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32_hse_clock, okay)
#define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
#else
#define STM32_HSE_BYPASS CONFIG_CLOCK_STM32_HSE_BYPASS
#endif
struct stm32_pclken {
uint32_t bus;
uint32_t enr;

2
soc/arm/st_stm32/stm32l4/power.c
View file

@ -20,7 +20,7 @@
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
/* select MSI as wake-up system clock if configured, HSI otherwise */
#if defined(CONFIG_CLOCK_STM32_SYSCLK_SRC_MSI)
#if STM32_SYSCLK_SRC_MSI
#define RCC_STOP_WAKEUPCLOCK_SELECTED LL_RCC_STOP_WAKEUPCLOCK_MSI
#else
#define RCC_STOP_WAKEUPCLOCK_SELECTED LL_RCC_STOP_WAKEUPCLOCK_HSI

2
soc/arm/st_stm32/stm32l5/power.c
View file

@ -20,7 +20,7 @@
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
/* select MSI as wake-up system clock if configured, HSI otherwise */
#if defined(CONFIG_CLOCK_STM32_SYSCLK_SRC_MSI)
#if STM32_SYSCLK_SRC_MSI
#define RCC_STOP_WAKEUPCLOCK_SELECTED LL_RCC_STOP_WAKEUPCLOCK_MSI
#else
#define RCC_STOP_WAKEUPCLOCK_SELECTED LL_RCC_STOP_WAKEUPCLOCK_HSI