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MXRT600: Fix secure/non-secure definition for FLEXSPI

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The Flexspi memory address defines the location of the externally
attached flash to the MXRT600 based board. The flexspi has two
different memory spaces for secure and non-secure access that are
not aligned for the Flexspi register space and the memory map
address space. The normal method of handling this via the two
different dts files for secure/non-secure is not able to handle
this because a base address is applied uniformly across multiple
reg items.

Changes include:

- pull flexspi out of peripherals block to allow it to be explicitly
expressed in the respective secure/non-secure SOC DTS files.
- move the flash size definition to the board level definition and
use the size of the actual flash device found on the board.
:
Signed-off-by: David Leach <david.leach@nxp.com>
This commit is contained in:
David Leach 2021-11-08 23:35:00 -06:00 • committed by Carles Cufí
commit a09ba37334
6 changed files with 26 additions and 17 deletions
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3
boards/arm/mimxrt685_evk/Kconfig.defconfig
View file

@ -17,6 +17,9 @@ config SYSOSC_SETTLING_US
config FLASH_MCUX_FLEXSPI_MX25UM51345G
default y if FLASH
config FLASH_SIZE
default $(dt_node_int_prop_int,/soc/spi@134000/mx25um51345g@2,size,K)
config FLASH_MCUX_FLEXSPI_XIP
default y if FLASH
depends on MEMC_MCUX_FLEXSPI

3
boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts
View file

@ -204,10 +204,9 @@ i2s1: &flexcomm3 {
};
&flexspi {
reg = <0x50134000 0x4000>, <0x18000000 DT_SIZE_M(64)>;
mx25um51345g: mx25um51345g@2 {
compatible = "nxp,imx-flexspi-mx25um51345g";
size = <536870912>;
size = <DT_SIZE_M(64)>;
label = "MX25UM51345G";
reg = <2>;
spi-max-frequency = <200000000>;

6
dts/arm/nxp/nxp_rt6xx.dtsi
View file

@ -5,9 +5,6 @@
*/
#include <mem.h>
#include <arm/armv8-m.dtsi>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
/ {
soc {
@ -18,6 +15,9 @@
peripheral: peripheral@50000000 {
ranges = <0x0 0x50000000 0x10000000>;
};
flexspi: spi@134000 {
reg = <0x5134000 0x1000>, <0x18000000 DT_SIZE_M(64)>;
};
};
};

16
dts/arm/nxp/nxp_rt6xx_common.dtsi
View file

@ -116,14 +116,6 @@
port = <2>;
};
flexspi: spi@134000 {
compatible = "nxp,imx-flexspi";
reg = <0x134000 0x1000>;
interrupts = <42 0>;
label = "FLEXSPI";
#address-cells = <1>;
#size-cells = <0>;
};
flexcomm0: flexcomm@106000 {
compatible = "nxp,lpc-flexcomm";
@ -393,6 +385,14 @@
};
};
&flexspi {
compatible = "nxp,imx-flexspi";
interrupts = <42 0>;
label = "FLEXSPI";
#address-cells = <1>;
#size-cells = <0>;
};
&nvic {
arm,num-irq-priority-bits = <3>;
};

5
dts/arm/nxp/nxp_rt6xx_ns.dtsi
View file

@ -4,6 +4,8 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
/ {
soc {
sram: sram@20180000 {
@ -13,6 +15,9 @@
peripheral: peripheral@40000000 {
ranges = <0x0 0x40000000 0x10000000>;
};
flexspi: spi@134000 {
reg = <0x4134000 0x1000>, <0x08000000 DT_SIZE_M(64)>;
};
};
};

10
soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.series
View file

@ -17,11 +17,13 @@ config NUM_IRQS
config PM
select CODE_DATA_RELOCATION_SRAM
config FLASH_SIZE
default $(dt_node_reg_size_int,/soc/peripheral@50000000/spi@134000,1,K)
#
# The base address of the external flash comes from the FLEXSPI base
# address. The size of the flash is defined by what is populated and
# described in the board devicetree file.
#
config FLASH_BASE_ADDRESS
default $(dt_node_reg_addr_hex,/soc/peripheral@50000000/spi@134000,1)
default $(dt_node_reg_addr_hex,/soc/spi@134000,1)
config ENTROPY_MCUX_TRNG
default y if HAS_MCUX_TRNG