MXRT600: Fix secure/non-secure definition for FLEXSPI
The Flexspi memory address defines the location of the externally attached flash to the MXRT600 based board. The flexspi has two different memory spaces for secure and non-secure access that are not aligned for the Flexspi register space and the memory map address space. The normal method of handling this via the two different dts files for secure/non-secure is not able to handle this because a base address is applied uniformly across multiple reg items. Changes include: - pull flexspi out of peripherals block to allow it to be explicitly expressed in the respective secure/non-secure SOC DTS files. - move the flash size definition to the board level definition and use the size of the actual flash device found on the board. : Signed-off-by: David Leach <david.leach@nxp.com>
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1e5a830233
commit
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6 changed files with 26 additions and 17 deletions
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@ -17,6 +17,9 @@ config SYSOSC_SETTLING_US
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config FLASH_MCUX_FLEXSPI_MX25UM51345G
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default y if FLASH
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config FLASH_SIZE
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default $(dt_node_int_prop_int,/soc/spi@134000/mx25um51345g@2,size,K)
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config FLASH_MCUX_FLEXSPI_XIP
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default y if FLASH
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depends on MEMC_MCUX_FLEXSPI
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@ -204,10 +204,9 @@ i2s1: &flexcomm3 {
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};
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&flexspi {
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reg = <0x50134000 0x4000>, <0x18000000 DT_SIZE_M(64)>;
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mx25um51345g: mx25um51345g@2 {
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compatible = "nxp,imx-flexspi-mx25um51345g";
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size = <536870912>;
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size = <DT_SIZE_M(64)>;
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label = "MX25UM51345G";
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reg = <2>;
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spi-max-frequency = <200000000>;
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@ -5,9 +5,6 @@
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*/
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#include <mem.h>
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#include <arm/armv8-m.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/i2c/i2c.h>
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/ {
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soc {
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@ -18,6 +15,9 @@
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peripheral: peripheral@50000000 {
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ranges = <0x0 0x50000000 0x10000000>;
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};
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flexspi: spi@134000 {
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reg = <0x5134000 0x1000>, <0x18000000 DT_SIZE_M(64)>;
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};
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};
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};
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@ -116,14 +116,6 @@
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port = <2>;
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};
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flexspi: spi@134000 {
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compatible = "nxp,imx-flexspi";
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reg = <0x134000 0x1000>;
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interrupts = <42 0>;
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label = "FLEXSPI";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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flexcomm0: flexcomm@106000 {
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compatible = "nxp,lpc-flexcomm";
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@ -393,6 +385,14 @@
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};
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};
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&flexspi {
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compatible = "nxp,imx-flexspi";
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interrupts = <42 0>;
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label = "FLEXSPI";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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@ -4,6 +4,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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/ {
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soc {
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sram: sram@20180000 {
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@ -13,6 +15,9 @@
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peripheral: peripheral@40000000 {
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ranges = <0x0 0x40000000 0x10000000>;
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};
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flexspi: spi@134000 {
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reg = <0x4134000 0x1000>, <0x08000000 DT_SIZE_M(64)>;
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};
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};
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};
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@ -17,11 +17,13 @@ config NUM_IRQS
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config PM
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select CODE_DATA_RELOCATION_SRAM
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config FLASH_SIZE
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default $(dt_node_reg_size_int,/soc/peripheral@50000000/spi@134000,1,K)
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#
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# The base address of the external flash comes from the FLEXSPI base
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# address. The size of the flash is defined by what is populated and
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# described in the board devicetree file.
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#
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config FLASH_BASE_ADDRESS
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default $(dt_node_reg_addr_hex,/soc/peripheral@50000000/spi@134000,1)
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default $(dt_node_reg_addr_hex,/soc/spi@134000,1)
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config ENTROPY_MCUX_TRNG
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default y if HAS_MCUX_TRNG
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