arch/x86: Generalize cache manipulation functions
We assume that all x86 CPUs do have clflush instructions. And the cache line size is now provided through DTS. So detecting clflush instruction as well as the cache line size is no longer required at runtime and thus removed. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka
Anas Nashif
parent
16c4b65dce
commit
5e4e0298e9
9 changed files with 3 additions and 168 deletions
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@ -20,6 +20,7 @@ zephyr_library_sources_ifdef(CONFIG_MULTIBOOT multiboot.c)
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zephyr_library_sources_ifdef(CONFIG_ACPI acpi.c)
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zephyr_library_sources_ifdef(CONFIG_X86_MMU x86_mmu.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.c)
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zephyr_library_sources_ifdef(CONFIG_CACHE_MANAGEMENT cache.c)
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zephyr_library_sources_ifdef(CONFIG_X86_VERY_EARLY_CONSOLE early_serial.c)
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@ -144,34 +144,6 @@ config X86_FP_USE_SOFT_FLOAT
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endmenu
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config DCACHE_LINE_SIZE
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default 64 if CPU_ATOM
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config CLFLUSH_INSTRUCTION_SUPPORTED
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bool "CLFLUSH instruction supported"
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depends on !CLFLUSH_DETECT && CACHE_MANAGEMENT
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help
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An implementation of sys_cache_flush() that uses CLFLUSH is made
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available, instead of the one using WBINVD.
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This option should only be enabled if it is known in advance that the
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CPU supports the CLFLUSH instruction. It disables runtime detection of
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CLFLUSH support thereby reducing both memory footprint and boot time.
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config CLFLUSH_DETECT
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bool "Detect support of CLFLUSH instruction at runtime"
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depends on CACHE_MANAGEMENT
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help
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This option should be enabled if it is not known in advance whether the
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CPU supports the CLFLUSH instruction or not.
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The CPU is queried at boot time to determine which of the multiple
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implementations of sys_cache_flush() linked into the image is the
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correct one to use.
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If the CPU's support (or lack thereof) of CLFLUSH is known in advance, then
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disable this option and set CLFLUSH_INSTRUCTION_SUPPORTED as appropriate.
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config X86_DYNAMIC_IRQ_STUBS
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int "Number of dynamic interrupt stubs"
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depends on DYNAMIC_INTERRUPTS
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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* Copyright (c) 2021 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -16,37 +17,18 @@
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#include <toolchain.h>
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#include <cache.h>
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#include <stdbool.h>
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#include <cache.h>
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/*
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* these functions are defined in cache_s.S
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*/
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extern int z_is_clflush_available(void);
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extern void z_cache_flush_wbinvd(vaddr_t addr, size_t len);
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extern size_t z_cache_line_size_get(void);
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#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT)
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size_t sys_cache_line_size;
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#endif
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#if defined(CONFIG_CLFLUSH_INSTRUCTION_SUPPORTED) || \
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defined(CONFIG_CLFLUSH_DETECT)
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/**
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*
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* @brief Flush cache lines to main memory
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*
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* No alignment is required for either <virt> or <size>, but since
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* sys_cache_flush() iterates on the cache lines, a cache line alignment for
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* both is optimal.
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*
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* The cache line size is specified either via the CONFIG_DCACHE_LINE_SIZE
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* kconfig option or it is detected at runtime.
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* The cache line size is specified via the d-cache-line-size DTS property.
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*
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* @return N/A
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*/
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static void arch_dcache_flush(void *start_addr, size_t size)
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{
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size_t line_size = sys_dcache_line_size_get();
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@ -76,31 +58,3 @@ int arch_dcache_range(void *addr, size_t size, int op)
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return -ENOTSUP;
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}
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#endif /* CONFIG_CLFLUSH_INSTRUCTION_SUPPORTED || CLFLUSH_DETECT */
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#include <init.h>
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#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT)
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static void init_cache_line_size(void)
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{
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sys_cache_line_size = z_cache_line_size_get();
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}
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size_t arch_cache_line_size_get(void)
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{
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return sys_cache_line_size;
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}
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#endif
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static int init_dcache(const struct device *unused)
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{
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ARG_UNUSED(unused);
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#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT)
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init_cache_line_size();
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#endif
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return 0;
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}
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SYS_INIT(init_dcache, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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@ -9,8 +9,6 @@ elseif(CMAKE_C_COMPILER_ID STREQUAL "GNU")
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endif()
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zephyr_library_sources(
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ia32/cache.c
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ia32/cache_s.S
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ia32/crt0.S
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ia32/excstub.S
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ia32/intstub.S
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@ -1,78 +0,0 @@
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Cache manipulation
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*
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* This module contains functions for manipulating caches.
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*/
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#include <arch/x86/ia32/asm.h>
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#ifndef CONFIG_CLFLUSH_INSTRUCTION_SUPPORTED
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#if defined(CONFIG_CLFLUSH_DETECT)
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#define CACHE_FLUSH_NAME z_cache_flush_wbinvd
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#define CPUID_CFLSH_BIT (1 << 19)
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GTEXT(z_is_clflush_available)
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SECTION_FUNC(TEXT, z_is_clflush_available)
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pushl %ebx
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movl $1, %eax
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cpuid
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movl %edx, %eax
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andl $CPUID_CFLSH_BIT, %eax
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popl %ebx
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ret
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#else
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#define CACHE_FLUSH_NAME sys_cache_flush
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#endif
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/* externs (internal APIs) */
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GTEXT(CACHE_FLUSH_NAME)
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/**
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*
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* @brief Flush a page to main memory
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*
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* This implementation flushes the whole cache.
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*
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* C signature:
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*
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* void sys_cache_flush (vaddr_t virt, size_t size)
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*
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* Both parameters are ignored in this implementation.
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, CACHE_FLUSH_NAME)
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wbinvd
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ret
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#endif /* !CONFIG_CLFLUSH_INSTRUCTION_SUPPORTED */
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#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT)
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#define CPUID_CACHE_LINE_MASK (0xff << 8)
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GTEXT(z_cache_line_size_get)
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SECTION_FUNC(TEXT, z_cache_line_size_get)
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pushl %ebx
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movl $1, %eax
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cpuid
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movl %ebx, %eax
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andl $CPUID_CACHE_LINE_MASK, %eax
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shrl $5,%eax /* shift right 8 to get value, then multiple by 8
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* to get cache line size */
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popl %ebx
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ret
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#endif /* CONFIG_DCACHE_LINE_SIZE_DETECT */
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@ -41,9 +41,6 @@ endif # APIC_TIMER_TSC
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endif # APIC_TIMER
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config CLFLUSH_DETECT
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default y if CACHE_MANAGEMENT
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config X86_DYNAMIC_IRQ_STUBS
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default 16
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depends on DYNAMIC_INTERRUPTS
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@ -11,9 +11,6 @@ config SOC
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 25000000 if HPET_TIMER
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config CLFLUSH_DETECT
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default y if CACHE_MANAGEMENT
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if BT_UART
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config UART_PIPE_ON_DEV_NAME
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@ -41,9 +41,6 @@ endif # APIC_TIMER_TSC
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endif # APIC_TIMER
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config CLFLUSH_DETECT
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default y if CACHE_MANAGEMENT
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config X86_DYNAMIC_IRQ_STUBS
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default 16
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depends on DYNAMIC_INTERRUPTS
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@ -11,7 +11,4 @@ config SOC
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 25000000 if HPET_TIMER
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config CLFLUSH_DETECT
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default y if CACHE_MANAGEMENT
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endif
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