intel_adsp: move imr configs to headers
Move those defines and values back to headers. Kconfig is not a good place for this, later this should move to DTS. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
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af3d5331a1
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01438a1998
13 changed files with 57 additions and 63 deletions
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@ -10,7 +10,7 @@
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#if defined(CONFIG_SOC_ESP32)
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#include "soc/soc_memory_layout.h"
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#elif defined(CONFIG_SOC_FAMILY_INTEL_ADSP)
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#include "soc.h"
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#include "debug_helpers.h"
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#endif
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static int mask, cause;
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@ -57,22 +57,6 @@ config ADSP_WIN3_OFFSET
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printk/log output) within the reserved region at the start
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of HP-SRAM.
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config IMR_MANIFEST_ADDR
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hex "Address of boot manifest struct within IMR memory"
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default 0xb0032000
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help
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Address where the rimage manifest struct is placed upon
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boot. Must be synchronized between Zephyr's linkage, the
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hardware, ROM and rimage configuration. Don't touch except
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with great care.
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config IMR_DATA_ADDR
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hex "Address of bootloader .data section within IMR memory"
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default 0xb0039000
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help
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Location to place .data contents in IMR memory during
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bootloader linkage.
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config ADSP_TRACE_SIMCALL
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bool "Emit SIMCALL output in addition to window tracing"
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help
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@ -15,9 +15,6 @@ config SOC
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string
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default "intel_ace15_mtpm"
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config IMR_MANIFEST_ADDR
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default 0xa1042000
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config MP_NUM_CPUS
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default 3
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@ -35,7 +35,10 @@
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* memory. There's no ability to change this offset, it's a magic
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* number from rimage we simply need to honor.
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*/
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
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#define IMR_BOOT_LDR_DATA_BASE (0xA1048000+0x1000)
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#define IMR_BOOT_LDR_MANIFEST_BASE 0xA1042000
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (IMR_BOOT_LDR_MANIFEST_BASE + 0x6000)
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#define ADSP_L1_CACHE_PREFCTL_VALUE 0x1038
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@ -24,12 +24,6 @@ config ADSP_WIN0_OFFSET
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config ADSP_WIN3_OFFSET
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default 0
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config IMR_MANIFEST_ADDR
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default 0xb0004000
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config IMR_DATA_ADDR
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default 0xb0002000
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config SMP
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default y
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@ -35,7 +35,10 @@
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* memory. There's no ability to change this offset, it's a magic
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* number from rimage we simply need to honor.
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*/
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
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#define IMR_BOOT_LDR_DATA_BASE 0xB0002000
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#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0004000
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (IMR_BOOT_LDR_MANIFEST_BASE + 0x6000)
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#define ADSP_L1_CACHE_PREFCTL_VALUE 0
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@ -35,7 +35,9 @@
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* memory. There's no ability to change this offset, it's a magic
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* number from rimage we simply need to honor.
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*/
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
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#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (IMR_BOOT_LDR_MANIFEST_BASE + 0x6000)
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#define ADSP_L1_CACHE_PREFCTL_VALUE 0
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@ -35,7 +35,10 @@
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* memory. There's no ability to change this offset, it's a magic
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* number from rimage we simply need to honor.
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*/
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
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#define IMR_BOOT_LDR_DATA_BASE 0xB0039000
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#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (IMR_BOOT_LDR_MANIFEST_BASE + 0x6000)
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#define ADSP_L1_CACHE_PREFCTL_VALUE 0
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@ -35,7 +35,10 @@
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* memory. There's no ability to change this offset, it's a magic
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* number from rimage we simply need to honor.
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*/
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
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#define IMR_BOOT_LDR_DATA_BASE 0xB0039000
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#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (IMR_BOOT_LDR_MANIFEST_BASE + 0x6000)
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#define ADSP_L1_CACHE_PREFCTL_VALUE 0x1038
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@ -58,7 +58,7 @@ __asm__(".pushsection .boot_entry.text, \"ax\" \n\t"
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* enter C code successfully, and calls boot_core0()
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*/
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#define STRINGIFY_MACRO(x) Z_STRINGIFY(x)
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#define IMRSTACK STRINGIFY_MACRO(CONFIG_IMR_MANIFEST_ADDR)
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#define IMRSTACK STRINGIFY_MACRO(IMR_BOOT_LDR_MANIFEST_BASE)
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__asm__(".section .imr.z_boot_asm_entry, \"x\" \n\t"
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".align 4 \n\t"
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"z_boot_asm_entry: \n\t"
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@ -110,7 +110,7 @@ static __imr void parse_module(struct sof_man_fw_header *hdr,
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__imr void parse_manifest(void)
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{
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struct sof_man_fw_desc *desc =
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(struct sof_man_fw_desc *)CONFIG_IMR_MANIFEST_ADDR;
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(struct sof_man_fw_desc *)IMR_BOOT_LDR_MANIFEST_BASE;
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struct sof_man_fw_header *hdr = &desc->header;
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struct sof_man_module *mod;
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int i;
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@ -1,9 +0,0 @@
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/* Copyright (c) 2021 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ZEPHYR_SOC_INTEL_ADSP_MEM
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#define _ZEPHYR_SOC_INTEL_ADSP_MEM
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#include <adsp_memory.h>
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#endif /* _ZEPHYR_SOC_INTEL_ADSP_MEM */
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35
soc/xtensa/intel_adsp/common/include/debug_helpers.h
Normal file
35
soc/xtensa/intel_adsp/common/include/debug_helpers.h
Normal file
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@ -0,0 +1,35 @@
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/* Copyright (c) 2022 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_INTEL_ADSP_DEBUG_HELPERS_H_
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#define ZEPHYR_SOC_INTEL_ADSP_DEBUG_HELPERS_H_
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#include <adsp_memory.h>
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extern char _text_start[];
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extern char _text_end[];
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extern char _imr_start[];
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extern char _imr_end[];
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extern char _end[];
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extern char _heap_sentry[];
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extern char _cached_start[];
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extern char _cached_end[];
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static inline bool intel_adsp_ptr_executable(const void *p)
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{
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return (p >= (void *)_text_start && p <= (void *)_text_end) ||
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(p >= (void *)_imr_start && p <= (void *)_imr_end);
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}
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static inline bool intel_adsp_ptr_is_sane(uint32_t sp)
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{
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return ((char *)sp >= _end && (char *)sp <= _heap_sentry) ||
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((char *)sp >= _cached_start && (char *)sp <= _cached_end) ||
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(sp >= (IMR_BOOT_LDR_MANIFEST_BASE - CONFIG_ISR_STACK_SIZE)
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&& sp <= IMR_BOOT_LDR_MANIFEST_BASE);
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}
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#endif /* ZEPHYR_SOC_INTEL_ADSP_DEBUG_HELPERS_H_ */
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@ -59,15 +59,6 @@
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#define DSP_WCT_CS_TT(x) BIT(4 + x)
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extern char _text_start[];
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extern char _text_end[];
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extern char _imr_start[];
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extern char _imr_end[];
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extern char _end[];
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extern char _heap_sentry[];
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extern char _cached_start[];
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extern char _cached_end[];
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extern void soc_trace_init(void);
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extern void z_soc_irq_init(void);
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extern void z_soc_irq_enable(uint32_t irq);
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@ -110,19 +101,7 @@ extern bool soc_cpus_active[CONFIG_MP_NUM_CPUS];
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*/
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int soc_adsp_halt_cpu(int id);
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static inline bool intel_adsp_ptr_executable(const void *p)
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{
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return (p >= (void *)_text_start && p <= (void *)_text_end) ||
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(p >= (void *)_imr_start && p <= (void *)_imr_end);
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}
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static inline bool intel_adsp_ptr_is_sane(uint32_t sp)
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{
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return ((char *)sp >= _end && (char *)sp <= _heap_sentry) ||
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((char *)sp >= _cached_start && (char *)sp <= _cached_end) ||
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(sp >= (CONFIG_IMR_MANIFEST_ADDR - CONFIG_ISR_STACK_SIZE)
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&& sp <= CONFIG_IMR_MANIFEST_ADDR);
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}
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static ALWAYS_INLINE void z_idelay(int n)
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{
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