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intel_adsp: move imr configs to headers

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Move those defines and values back to headers. Kconfig is not a good
place for this, later this should move to DTS.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2022-07-14 11:23:22 -04:00
commit 01438a1998
13 changed files with 57 additions and 63 deletions
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2
arch/xtensa/core/xtensa_backtrace.c
View file

@ -10,7 +10,7 @@
#if defined(CONFIG_SOC_ESP32)
#include "soc/soc_memory_layout.h"
#elif defined(CONFIG_SOC_FAMILY_INTEL_ADSP)
#include "soc.h"
#include "debug_helpers.h"
#endif
static int mask, cause;

16
soc/xtensa/intel_adsp/Kconfig
View file

@ -57,22 +57,6 @@ config ADSP_WIN3_OFFSET
printk/log output) within the reserved region at the start
of HP-SRAM.
config IMR_MANIFEST_ADDR
hex "Address of boot manifest struct within IMR memory"
default 0xb0032000
help
Address where the rimage manifest struct is placed upon
boot. Must be synchronized between Zephyr's linkage, the
hardware, ROM and rimage configuration. Don't touch except
with great care.
config IMR_DATA_ADDR
hex "Address of bootloader .data section within IMR memory"
default 0xb0039000
help
Location to place .data contents in IMR memory during
bootloader linkage.
config ADSP_TRACE_SIMCALL
bool "Emit SIMCALL output in addition to window tracing"
help

3
soc/xtensa/intel_adsp/ace_v1x/Kconfig.defconfig.series
View file

@ -15,9 +15,6 @@ config SOC
string
default "intel_ace15_mtpm"
config IMR_MANIFEST_ADDR
default 0xa1042000
config MP_NUM_CPUS
default 3

5
soc/xtensa/intel_adsp/ace_v1x/include/adsp_memory.h
View file

@ -35,7 +35,10 @@
* memory. There's no ability to change this offset, it's a magic
* number from rimage we simply need to honor.
*/
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
#define IMR_BOOT_LDR_DATA_BASE (0xA1048000+0x1000)
#define IMR_BOOT_LDR_MANIFEST_BASE 0xA1042000
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (IMR_BOOT_LDR_MANIFEST_BASE + 0x6000)
#define ADSP_L1_CACHE_PREFCTL_VALUE 0x1038

6
soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series
View file

@ -24,12 +24,6 @@ config ADSP_WIN0_OFFSET
config ADSP_WIN3_OFFSET
default 0
config IMR_MANIFEST_ADDR
default 0xb0004000
config IMR_DATA_ADDR
default 0xb0002000
config SMP
default y

5
soc/xtensa/intel_adsp/cavs_v15/include/adsp_memory.h
View file

@ -35,7 +35,10 @@
* memory. There's no ability to change this offset, it's a magic
* number from rimage we simply need to honor.
*/
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
#define IMR_BOOT_LDR_DATA_BASE 0xB0002000
#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0004000
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (IMR_BOOT_LDR_MANIFEST_BASE + 0x6000)
#define ADSP_L1_CACHE_PREFCTL_VALUE 0

4
soc/xtensa/intel_adsp/cavs_v18/include/adsp_memory.h
View file

@ -35,7 +35,9 @@
* memory. There's no ability to change this offset, it's a magic
* number from rimage we simply need to honor.
*/
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (IMR_BOOT_LDR_MANIFEST_BASE + 0x6000)
#define ADSP_L1_CACHE_PREFCTL_VALUE 0

5
soc/xtensa/intel_adsp/cavs_v20/include/adsp_memory.h
View file

@ -35,7 +35,10 @@
* memory. There's no ability to change this offset, it's a magic
* number from rimage we simply need to honor.
*/
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
#define IMR_BOOT_LDR_DATA_BASE 0xB0039000
#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (IMR_BOOT_LDR_MANIFEST_BASE + 0x6000)
#define ADSP_L1_CACHE_PREFCTL_VALUE 0

5
soc/xtensa/intel_adsp/cavs_v25/include/adsp_memory.h
View file

@ -35,7 +35,10 @@
* memory. There's no ability to change this offset, it's a magic
* number from rimage we simply need to honor.
*/
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (CONFIG_IMR_MANIFEST_ADDR + 0x6000)
#define IMR_BOOT_LDR_DATA_BASE 0xB0039000
#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (IMR_BOOT_LDR_MANIFEST_BASE + 0x6000)
#define ADSP_L1_CACHE_PREFCTL_VALUE 0x1038

4
soc/xtensa/intel_adsp/common/boot.c
View file

@ -58,7 +58,7 @@ __asm__(".pushsection .boot_entry.text, \"ax\" \n\t"
* enter C code successfully, and calls boot_core0()
*/
#define STRINGIFY_MACRO(x) Z_STRINGIFY(x)
#define IMRSTACK STRINGIFY_MACRO(CONFIG_IMR_MANIFEST_ADDR)
#define IMRSTACK STRINGIFY_MACRO(IMR_BOOT_LDR_MANIFEST_BASE)
__asm__(".section .imr.z_boot_asm_entry, \"x\" \n\t"
".align 4 \n\t"
"z_boot_asm_entry: \n\t"
@ -110,7 +110,7 @@ static __imr void parse_module(struct sof_man_fw_header *hdr,
__imr void parse_manifest(void)
{
struct sof_man_fw_desc *desc =
(struct sof_man_fw_desc *)CONFIG_IMR_MANIFEST_ADDR;
(struct sof_man_fw_desc *)IMR_BOOT_LDR_MANIFEST_BASE;
struct sof_man_fw_header *hdr = &desc->header;
struct sof_man_module *mod;
int i;

9
soc/xtensa/intel_adsp/common/include/cavs-mem.h
View file

@ -1,9 +0,0 @@
/* Copyright (c) 2021 Intel Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ZEPHYR_SOC_INTEL_ADSP_MEM
#define _ZEPHYR_SOC_INTEL_ADSP_MEM
#include <adsp_memory.h>
#endif /* _ZEPHYR_SOC_INTEL_ADSP_MEM */

35
soc/xtensa/intel_adsp/common/include/debug_helpers.h Normal file
View file

@ -0,0 +1,35 @@
/* Copyright (c) 2022 Intel Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_DEBUG_HELPERS_H_
#define ZEPHYR_SOC_INTEL_ADSP_DEBUG_HELPERS_H_
#include <adsp_memory.h>
extern char _text_start[];
extern char _text_end[];
extern char _imr_start[];
extern char _imr_end[];
extern char _end[];
extern char _heap_sentry[];
extern char _cached_start[];
extern char _cached_end[];
static inline bool intel_adsp_ptr_executable(const void *p)
{
return (p >= (void *)_text_start && p <= (void *)_text_end) ||
(p >= (void *)_imr_start && p <= (void *)_imr_end);
}
static inline bool intel_adsp_ptr_is_sane(uint32_t sp)
{
return ((char *)sp >= _end && (char *)sp <= _heap_sentry) ||
((char *)sp >= _cached_start && (char *)sp <= _cached_end) ||
(sp >= (IMR_BOOT_LDR_MANIFEST_BASE - CONFIG_ISR_STACK_SIZE)
&& sp <= IMR_BOOT_LDR_MANIFEST_BASE);
}
#endif /* ZEPHYR_SOC_INTEL_ADSP_DEBUG_HELPERS_H_ */

21
soc/xtensa/intel_adsp/common/include/soc.h
View file

@ -59,15 +59,6 @@
#define DSP_WCT_CS_TT(x) BIT(4 + x)
extern char _text_start[];
extern char _text_end[];
extern char _imr_start[];
extern char _imr_end[];
extern char _end[];
extern char _heap_sentry[];
extern char _cached_start[];
extern char _cached_end[];
extern void soc_trace_init(void);
extern void z_soc_irq_init(void);
extern void z_soc_irq_enable(uint32_t irq);
@ -110,19 +101,7 @@ extern bool soc_cpus_active[CONFIG_MP_NUM_CPUS];
*/
int soc_adsp_halt_cpu(int id);
static inline bool intel_adsp_ptr_executable(const void *p)
{
return (p >= (void *)_text_start && p <= (void *)_text_end) ||
(p >= (void *)_imr_start && p <= (void *)_imr_end);
}
static inline bool intel_adsp_ptr_is_sane(uint32_t sp)
{
return ((char *)sp >= _end && (char *)sp <= _heap_sentry) ||
((char *)sp >= _cached_start && (char *)sp <= _cached_end) ||
(sp >= (CONFIG_IMR_MANIFEST_ADDR - CONFIG_ISR_STACK_SIZE)
&& sp <= CONFIG_IMR_MANIFEST_ADDR);
}
static ALWAYS_INLINE void z_idelay(int n)
{